1  /*
2   * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for any
5   * purpose with or without fee is hereby granted, provided that the above
6   * copyright notice and this permission notice appear in all copies.
7   *
8   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9   * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10   * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11   * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12   * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13   * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14   * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15   */
16  
17  #ifndef _COEX_TX_STATUS_H_
18  #define _COEX_TX_STATUS_H_
19  #if !defined(__ASSEMBLER__)
20  #endif
21  
22  #define NUM_OF_DWORDS_COEX_TX_STATUS 4
23  
24  #define NUM_OF_QWORDS_COEX_TX_STATUS 2
25  
26  
27  struct coex_tx_status {
28  #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
29               uint32_t reserved_0a                                             :  7, // [6:0]
30                        tx_bw                                                   :  3, // [9:7]
31                        tx_status_reason                                        :  3, // [12:10]
32                        tx_wait_ack                                             :  1, // [13:13]
33                        fes_tx_is_gen_frame                                     :  1, // [14:14]
34                        sch_tx_burst_ongoing                                    :  1, // [15:15]
35                        current_tx_duration                                     : 16; // [31:16]
36               uint32_t next_rx_active_time                                     : 16, // [15:0]
37                        remaining_fes_time                                      : 16; // [31:16]
38               uint32_t tx_antenna_mask                                         :  8, // [7:0]
39                        shared_ant_tx_pwr                                       :  8, // [15:8]
40                        other_ant_tx_pwr                                        :  8, // [23:16]
41                        reserved_2                                              :  8; // [31:24]
42               uint32_t tlv64_padding                                           : 32; // [31:0]
43  #else
44               uint32_t current_tx_duration                                     : 16, // [31:16]
45                        sch_tx_burst_ongoing                                    :  1, // [15:15]
46                        fes_tx_is_gen_frame                                     :  1, // [14:14]
47                        tx_wait_ack                                             :  1, // [13:13]
48                        tx_status_reason                                        :  3, // [12:10]
49                        tx_bw                                                   :  3, // [9:7]
50                        reserved_0a                                             :  7; // [6:0]
51               uint32_t remaining_fes_time                                      : 16, // [31:16]
52                        next_rx_active_time                                     : 16; // [15:0]
53               uint32_t reserved_2                                              :  8, // [31:24]
54                        other_ant_tx_pwr                                        :  8, // [23:16]
55                        shared_ant_tx_pwr                                       :  8, // [15:8]
56                        tx_antenna_mask                                         :  8; // [7:0]
57               uint32_t tlv64_padding                                           : 32; // [31:0]
58  #endif
59  };
60  
61  
62  /* Description		RESERVED_0A
63  
64  			<legal 0>
65  */
66  
67  #define COEX_TX_STATUS_RESERVED_0A_OFFSET                                           0x0000000000000000
68  #define COEX_TX_STATUS_RESERVED_0A_LSB                                              0
69  #define COEX_TX_STATUS_RESERVED_0A_MSB                                              6
70  #define COEX_TX_STATUS_RESERVED_0A_MASK                                             0x000000000000007f
71  
72  
73  /* Description		TX_BW
74  
75  			The BW of the upcoming transmission.
76  			Note: Coex might have changed this from the original request.
77  			See coex related fields below
78  
79  			<enum 0 20_mhz>20 Mhz BW
80  			<enum 1 40_mhz>40 Mhz BW
81  			<enum 2 80_mhz>80 Mhz BW
82  			<enum 3 160_mhz>160 Mhz BW
83  			<enum 4 320_mhz>320 Mhz BW
84  			<enum 5 240_mhz>240 Mhz BW
85  */
86  
87  #define COEX_TX_STATUS_TX_BW_OFFSET                                                 0x0000000000000000
88  #define COEX_TX_STATUS_TX_BW_LSB                                                    7
89  #define COEX_TX_STATUS_TX_BW_MSB                                                    9
90  #define COEX_TX_STATUS_TX_BW_MASK                                                   0x0000000000000380
91  
92  
93  /* Description		TX_STATUS_REASON
94  
95  			<enum 0     FES_tx_start> TXPCU sends this status at the
96  			 start of SCH initiated transmission (when the commands
97  			are given to the PHY). This includes the transmission of
98  			 RTS and CTS
99  			Note that based on field 'Fes_tx_is_gen_frame' COEX can
100  			derive if this is a protection frame or regular PPDU.
101  
102  			<enum 1     FES_tx_end> TXPCU sends this status at the end
103  			 of SCH initiated transmission (when PHY TX has confirmed
104  			 the transmit over the medium has finished)
105  
106  			<enum 2     FES_end> TXPCU sends this status at the end
107  			of of the entire frame exchange sequence. This includes
108  			reception (or lack of..) of the ACK/BA/CTS frame
109  			TXPCU sends this FES after it has sent the TX_FES_STATUS
110  			 TLV(s). This also sent in case of 11ax basic trigger response
111  			 transmissions, when an ACK/BA is expected, and that got
112  			 received.
113  			<enum 3     Response_tx_start> TXPCU sends this status at
114  			 the start of Self gen initiated response transmission (when
115  			 the commands are given to the PHY)
116  			<enum 4     Response_tx_end> TXPCU sends this status at
117  			the end of Self gen initiated response transmission (when
118  			 PHY TX has confirmed the transmit over the medium has finished)
119  
120  
121  			<enum 5     No_tx_ongoing> TXPCU sends this TLV when forced
122  			 by SW to do so. It is used to be able to get TXPCU and
123  			coex synchronized again in case of some error handling scenarios
124  
125  
126  			<legal 0-5>
127  */
128  
129  #define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET                                      0x0000000000000000
130  #define COEX_TX_STATUS_TX_STATUS_REASON_LSB                                         10
131  #define COEX_TX_STATUS_TX_STATUS_REASON_MSB                                         12
132  #define COEX_TX_STATUS_TX_STATUS_REASON_MASK                                        0x0000000000001c00
133  
134  
135  /* Description		TX_WAIT_ACK
136  
137  			Field can only be set for the 'FES_tx_end' scenario.
138  			TXPCU sets this bit to 1 when it is waiting for an ACK/BA
139  			 or CTS Response.
140  */
141  
142  #define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET                                           0x0000000000000000
143  #define COEX_TX_STATUS_TX_WAIT_ACK_LSB                                              13
144  #define COEX_TX_STATUS_TX_WAIT_ACK_MSB                                              13
145  #define COEX_TX_STATUS_TX_WAIT_ACK_MASK                                             0x0000000000002000
146  
147  
148  /* Description		FES_TX_IS_GEN_FRAME
149  
150  			Field only valid in case tx_status_reason indicates FES_tx_start
151  			 or FES_tx_end.
152  
153  			Field is set to 1 if the frame transmitted is a self generated
154  			 frame like RTS, CTS 2 self or NDP
155  */
156  
157  #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET                                   0x0000000000000000
158  #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB                                      14
159  #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB                                      14
160  #define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK                                     0x0000000000004000
161  
162  
163  /* Description		SCH_TX_BURST_ONGOING
164  
165  			The proposed change by HWSCH  requires TXPCU to reflect
166  			TX_FES_SETUP.sch_tx_burst_ongoing field intoCOEX_TX_STATUS.sch_tx_burst_ongoing
167  			 field, when tx_status_reason is FES_end.
168  			SCH will overwrite this bit (that is set it to 1), when
169  			TXPCU set the tx_status_reason to FES_end, and SCH determines
170  			 that this FES is followed by other SIFS bursting based
171  			Scheduler commands.
172  			<legal all>
173  */
174  
175  #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET                                  0x0000000000000000
176  #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB                                     15
177  #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB                                     15
178  #define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK                                    0x0000000000008000
179  
180  
181  /* Description		CURRENT_TX_DURATION
182  
183  			In case of FES related transmission:
184  			TXPCU sends current transmission time at the beginning of
185  			 transmission. This time covers the entire (PPDU) tx_frame.
186  			This field is only valid when 'tx_status_reason' is equal
187  			 to FES_tx_start or Response_tx_start. In other scenarios
188  			 it is set to 0
189  			In us units <legal all>
190  */
191  
192  #define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET                                   0x0000000000000000
193  #define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB                                      16
194  #define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB                                      31
195  #define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK                                     0x00000000ffff0000
196  
197  
198  /* Description		NEXT_RX_ACTIVE_TIME
199  
200  			In case of FES transmission:
201  			The expected receive duration for ACK/CTS/BA frame after
202  			 current transmission has finished. This field should be
203  			 set at both the start and end of the transmission.  When
204  			 no frame reception is expected, this field is 0
205  
206  			In case of Response transmission or Trigger Response transmission:
207  
208  			The expected receive duration for upcoming reception. This
209  			 field has the same value as the transmitted duration field.
210  
211  
212  			Note that for this scenario, there might be an other TX
213  			generated during this specified time. It is not known to
214  			 this device what the transmitter is planning to do in the
215  			 remainder of the TXOP. In other words, this value represents
216  			 the best guess, but might not be fully accurate.
217  
218  			In us units
219  			<legal all>
220  */
221  
222  #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET                                   0x0000000000000000
223  #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB                                      32
224  #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB                                      47
225  #define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK                                     0x0000ffff00000000
226  
227  
228  /* Description		REMAINING_FES_TIME
229  
230  			In case of FES transmission:
231  			TXPCU sends the remaining FES time it expects to occupy
232  			the media.
233  			At the 'FES_tx_start', this value is the current_tx_duration
234  			 + value of inserted duration field.
235  			At the 'FES_tx_end', this value is equal to the duration
236  			 field in the just transmitted frame.
237  			At the 'FES_end', this value is the remaining FES duration
238  			 value. Note that this value should only be non zero in
239  			case of SIFS burting type of transmissions.
240  			In case of a FES failure, like reponse frame not received,
241  			this field is set to 0
242  
243  			In case of Self Gen response transmission (includes Trigger
244  			 response):
245  			At the 'Response_tx_start', this field has the same value
246  			 as the Current_tx_duration  + inserted duration field
247  			At the 'Response_tx_end', this field has the same value
248  			as the inserted duration field
249  			<legal all>
250  */
251  
252  #define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET                                    0x0000000000000000
253  #define COEX_TX_STATUS_REMAINING_FES_TIME_LSB                                       48
254  #define COEX_TX_STATUS_REMAINING_FES_TIME_MSB                                       63
255  #define COEX_TX_STATUS_REMAINING_FES_TIME_MASK                                      0xffff000000000000
256  
257  
258  /* Description		TX_ANTENNA_MASK
259  
260  			The actual used antennas for this transmission
261  
262  			For debug purpose only. PDG should not have modified the
263  			 value given by the Coex.
264  
265  			<legal all>
266  */
267  
268  #define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET                                       0x0000000000000008
269  #define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB                                          0
270  #define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB                                          7
271  #define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK                                         0x00000000000000ff
272  
273  
274  /* Description		SHARED_ANT_TX_PWR
275  
276  			Actual tx power on the shared antenna
277  			TXPCU sends at the beginning of transmission when tx_frame
278  			 is on.
279  
280  			For debug purpose only. PDG should not have modified the
281  			 value given by the Coex.
282  
283  			Transmit Power in s6.2 format.
284  			In units of 0.25 dBm
285  			<legal all>
286  */
287  
288  #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET                                     0x0000000000000008
289  #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB                                        8
290  #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB                                        15
291  #define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK                                       0x000000000000ff00
292  
293  
294  /* Description		OTHER_ANT_TX_PWR
295  
296  			Actual tx power on the 'unshared' antenna(s)
297  			TXPCU sends at the beginning of transmission when tx_frame
298  			 is on.
299  
300  			For debug purpose only. PDG should not have modified the
301  			 value given by the Coex.
302  
303  			Transmit Power in s6.2 format.
304  			In units of 0.25 dBm
305  			<legal all>
306  */
307  
308  #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET                                      0x0000000000000008
309  #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB                                         16
310  #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB                                         23
311  #define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK                                        0x0000000000ff0000
312  
313  
314  /* Description		RESERVED_2
315  
316  			Generator should set to 0, consumer shall ignore <legal
317  			0>
318  */
319  
320  #define COEX_TX_STATUS_RESERVED_2_OFFSET                                            0x0000000000000008
321  #define COEX_TX_STATUS_RESERVED_2_LSB                                               24
322  #define COEX_TX_STATUS_RESERVED_2_MSB                                               31
323  #define COEX_TX_STATUS_RESERVED_2_MASK                                              0x00000000ff000000
324  
325  
326  /* Description		TLV64_PADDING
327  
328  			Automatic DWORD padding inserted while converting TLV32
329  			to TLV64 for 64 bit ARCH
330  			<legal 0>
331  */
332  
333  #define COEX_TX_STATUS_TLV64_PADDING_OFFSET                                         0x0000000000000008
334  #define COEX_TX_STATUS_TLV64_PADDING_LSB                                            32
335  #define COEX_TX_STATUS_TLV64_PADDING_MSB                                            63
336  #define COEX_TX_STATUS_TLV64_PADDING_MASK                                           0xffffffff00000000
337  
338  
339  
340  #endif   // COEX_TX_STATUS
341