1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _BUFFER_ADDR_INFO_H_ 19 #define _BUFFER_ADDR_INFO_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 24 25 26 struct buffer_addr_info { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 uint32_t buffer_addr_31_0 : 32; // [31:0] 29 uint32_t buffer_addr_39_32 : 8, // [7:0] 30 return_buffer_manager : 4, // [11:8] 31 sw_buffer_cookie : 20; // [31:12] 32 #else 33 uint32_t buffer_addr_31_0 : 32; // [31:0] 34 uint32_t sw_buffer_cookie : 20, // [31:12] 35 return_buffer_manager : 4, // [11:8] 36 buffer_addr_39_32 : 8; // [7:0] 37 #endif 38 }; 39 40 41 /* Description BUFFER_ADDR_31_0 42 43 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 44 descriptor OR Link Descriptor 45 46 In case of 'NULL' pointer, this field is set to 0 47 <legal all> 48 */ 49 50 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 51 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 52 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 53 #define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 54 55 56 /* Description BUFFER_ADDR_39_32 57 58 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 59 descriptor OR Link Descriptor 60 61 In case of 'NULL' pointer, this field is set to 0 62 <legal all> 63 */ 64 65 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 66 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 67 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 68 #define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 69 70 71 /* Description RETURN_BUFFER_MANAGER 72 73 Consumer: WBM 74 Producer: SW/FW 75 76 In case of 'NULL' pointer, this field is set to 0 77 78 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 79 descriptor OR link descriptor that is being pointed to 80 shall be returned after the frame has been processed. It 81 is used by WBM for routing purposes. 82 83 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 84 to the WMB buffer idle list 85 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 86 to the WBM idle link descriptor idle list, where the chip 87 0 WBM is chosen in case of a multi-chip config 88 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 89 to the chip 1 WBM idle link descriptor idle list 90 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 91 to the chip 2 WBM idle link descriptor idle list 92 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 93 returned to chip 3 WBM idle link descriptor idle list 94 <enum 4 FW_BM> This buffer shall be returned to the FW 95 <enum 5 SW0_BM> This buffer shall be returned to the SW, 96 ring 0 97 <enum 6 SW1_BM> This buffer shall be returned to the SW, 98 ring 1 99 <enum 7 SW2_BM> This buffer shall be returned to the SW, 100 ring 2 101 <enum 8 SW3_BM> This buffer shall be returned to the SW, 102 ring 3 103 <enum 9 SW4_BM> This buffer shall be returned to the SW, 104 ring 4 105 <enum 10 SW5_BM> This buffer shall be returned to the SW, 106 ring 5 107 <enum 11 SW6_BM> This buffer shall be returned to the SW, 108 ring 6 109 110 <legal 0-12> 111 */ 112 113 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 114 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 115 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 116 #define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 117 118 119 /* Description SW_BUFFER_COOKIE 120 121 Cookie field exclusively used by SW. 122 123 In case of 'NULL' pointer, this field is set to 0 124 125 HW ignores the contents, accept that it passes the programmed 126 value on to other descriptors together with the physical 127 address 128 129 Field can be used by SW to for example associate the buffers 130 physical address with the virtual address 131 The bit definitions as used by SW are within SW HLD specification 132 133 134 NOTE1: 135 The three most significant bits can have a special meaning 136 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 137 and field transmit_bw_restriction is set 138 139 In case of NON punctured transmission: 140 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 141 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 142 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 143 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 144 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 145 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 146 Sw_buffer_cookie[19:18] = 2'b11: reserved 147 148 In case of punctured transmission: 149 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 150 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 151 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 152 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 153 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 154 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 155 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 156 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 157 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 158 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 159 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 160 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 161 Sw_buffer_cookie[19:18] = 2'b11: reserved 162 163 Note: a punctured transmission is indicated by the presence 164 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 165 166 <legal all> 167 */ 168 169 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 170 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 171 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 172 #define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 173 174 175 176 #endif // BUFFER_ADDR_INFO 177