1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SW_MONITOR_RING_H_ 18 #define _SW_MONITOR_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_details.h" 23 #include "buffer_addr_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 29 // 4-5 struct buffer_addr_info status_buff_addr_info; 30 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], frameless_bar[11], status_buf_count[15:12], end_of_ppdu[16], reserved_6a[31:17] 31 // 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] 32 // 33 // ################ END SUMMARY ################# 34 35 #define NUM_OF_DWORDS_SW_MONITOR_RING 8 36 37 struct sw_monitor_ring { 38 struct rx_mpdu_details reo_level_mpdu_frame_info; 39 struct buffer_addr_info status_buff_addr_info; 40 uint32_t rxdma_push_reason : 2, //[1:0] 41 rxdma_error_code : 5, //[6:2] 42 mpdu_fragment_number : 4, //[10:7] 43 frameless_bar : 1, //[11] 44 status_buf_count : 4, //[15:12] 45 end_of_ppdu : 1, //[16] 46 reserved_6a : 15; //[31:17] 47 uint32_t phy_ppdu_id : 16, //[15:0] 48 reserved_7a : 4, //[19:16] 49 ring_id : 8, //[27:20] 50 looping_count : 4; //[31:28] 51 }; 52 53 /* 54 55 struct rx_mpdu_details reo_level_mpdu_frame_info 56 57 Consumer: SW 58 59 Producer: RXDMA 60 61 62 63 Details related to the MPDU being pushed to SW, valid 64 only if end_of_ppdu is set to 0 65 66 struct buffer_addr_info status_buff_addr_info 67 68 Consumer: SW 69 70 Producer: RXDMA 71 72 73 74 Details of the physical address of the first status 75 buffer used for the PPDU (either the PPDU that included the 76 MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU 77 whose end is indicated through end_of_ppdu = 1) 78 79 rxdma_push_reason 80 81 Indicates why RXDMA pushed the frame to this ring 82 83 84 85 <enum 0 rxdma_error_detected> RXDMA detected an error an 86 pushed this frame to this queue 87 88 <enum 1 rxdma_routing_instruction> RXDMA pushed the 89 frame to this queue per received routing instructions. No 90 error within RXDMA was detected 91 92 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 93 result the MSDU link descriptor might not have the 94 last_msdu_in_mpdu_flag set, but instead WBM might just see a 95 NULL pointer in the MSDU link descriptor. This is to be 96 considered a normal condition for this scenario. 97 98 99 100 <legal 0 - 2> 101 102 rxdma_error_code 103 104 Field only valid when rxdma_push_reason is set to 105 'rxdma_error_detected.' 106 107 108 109 <enum 0 rxdma_overflow_err>MPDU frame is not complete 110 due to a FIFO overflow error in RXPCU. 111 112 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 113 due to receiving incomplete MPDU from the PHY 114 115 116 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 117 error or CRYPTO received an encrypted frame, but did not get 118 a valid corresponding key id in the peer entry. 119 120 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 121 error 122 123 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 124 unencrypted frame error when encrypted was expected 125 126 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 127 length error 128 129 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 130 number of MSDUs allowed in an MPDU got exceeded 131 132 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 133 error 134 135 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 136 parsing error 137 138 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 139 during SA search 140 141 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 142 during DA search 143 144 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 145 timeout during flow search 146 147 <enum 13 rxdma_flush_request>RXDMA received a flush 148 request 149 150 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 151 present as well as a fragmented MPDU. A-MSDU defragmentation 152 is not supported in Lithium SW so this is treated as an 153 error. 154 155 mpdu_fragment_number 156 157 Field only valid when Reo_level_mpdu_frame_info. 158 Rx_mpdu_desc_info_details.Fragment_flag is set and 159 end_of_ppdu is set to 0. 160 161 162 163 The fragment number from the 802.11 header. 164 165 166 167 Note that the sequence number is embedded in the field: 168 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 169 Mpdu_sequence_number 170 171 172 173 <legal all> 174 175 frameless_bar 176 177 When set, this SW monitor ring struct contains BAR info 178 from a multi TID BAR frame. The original multi TID BAR frame 179 itself contained all the REO info for the first TID, but all 180 the subsequent TID info and their linkage to the REO 181 descriptors is passed down as 'frameless' BAR info. 182 183 184 185 The only fields valid in this descriptor when this bit 186 is within the 187 188 Reo_level_mpdu_frame_info: 189 190 Within Rx_mpdu_desc_info_details: 191 192 Mpdu_Sequence_number 193 194 BAR_frame 195 196 Peer_meta_data 197 198 All other fields shall be set to 0. 199 200 201 202 <legal all> 203 204 status_buf_count 205 206 A count of status buffers used so far for the PPDU 207 (either the PPDU that included the MPDU being pushed to SW 208 if end_of_ppdu = 0, or the PPDU whose end is indicated 209 through end_of_ppdu = 1) 210 211 end_of_ppdu 212 213 Pine RXDMA can be configured to generate a separate 214 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 215 through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 216 demarcate PPDUs. 217 218 219 220 For such a descriptor, this bit is set to 1 and fields 221 Reo_level_mpdu_frame_info, mpdu_fragment_number and 222 Frameless_bar are all set to 0. 223 224 225 226 Otherwise this bit is set to 0. 227 228 reserved_6a 229 230 <legal 0> 231 232 phy_ppdu_id 233 234 A PPDU counter value that PHY increments for every PPDU 235 received 236 237 The counter value wraps around. Pine RXDMA can be 238 configured to copy this from the RX_PPDU_START TLV for every 239 output descriptor. 240 241 242 243 <legal all> 244 245 reserved_7a 246 247 <legal 0> 248 249 ring_id 250 251 Consumer: SW/REO/DEBUG 252 253 Producer: SRNG (of RXDMA) 254 255 256 257 For debugging. 258 259 This field is filled in by the SRNG module. 260 261 It help to identify the ring that is being looked <legal 262 all> 263 264 looping_count 265 266 Consumer: SW/REO/DEBUG 267 268 Producer: SRNG (of RXDMA) 269 270 271 272 For debugging. 273 274 This field is filled in by the SRNG module. 275 276 277 278 A count value that indicates the number of times the 279 producer of entries into this Ring has looped around the 280 ring. 281 282 At initialization time, this value is set to 0. On the 283 first loop, this value is set to 1. After the max value is 284 reached allowed by the number of bits for this field, the 285 count value continues with 0 again. 286 287 288 289 In case SW is the consumer of the ring entries, it can 290 use this field to figure out up to where the producer of 291 entries has created new entries. This eliminates the need to 292 check where the head pointer' of the ring is located once 293 the SW starts processing an interrupt indicating that new 294 entries have been put into this ring... 295 296 297 298 Also note that SW if it wants only needs to look at the 299 LSB bit of this count value. 300 301 <legal all> 302 */ 303 304 305 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 306 307 308 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 309 310 311 /* Description SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 312 313 Address (lower 32 bits) of the MSDU buffer OR 314 MSDU_EXTENSION descriptor OR Link Descriptor 315 316 317 318 In case of 'NULL' pointer, this field is set to 0 319 320 <legal all> 321 */ 322 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 323 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 324 #define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 325 326 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 327 328 Address (upper 8 bits) of the MSDU buffer OR 329 MSDU_EXTENSION descriptor OR Link Descriptor 330 331 332 333 In case of 'NULL' pointer, this field is set to 0 334 335 <legal all> 336 */ 337 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 338 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 339 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 340 341 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 342 343 Consumer: WBM 344 345 Producer: SW/FW 346 347 348 349 In case of 'NULL' pointer, this field is set to 0 350 351 352 353 Indicates to which buffer manager the buffer OR 354 MSDU_EXTENSION descriptor OR link descriptor that is being 355 pointed to shall be returned after the frame has been 356 processed. It is used by WBM for routing purposes. 357 358 359 360 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 361 to the WMB buffer idle list 362 363 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 364 returned to the WMB idle link descriptor idle list 365 366 <enum 2 FW_BM> This buffer shall be returned to the FW 367 368 <enum 3 SW0_BM> This buffer shall be returned to the SW, 369 ring 0 370 371 <enum 4 SW1_BM> This buffer shall be returned to the SW, 372 ring 1 373 374 <enum 5 SW2_BM> This buffer shall be returned to the SW, 375 ring 2 376 377 <enum 6 SW3_BM> This buffer shall be returned to the SW, 378 ring 3 379 380 <enum 7 SW4_BM> This buffer shall be returned to the SW, 381 ring 4 382 383 384 385 <legal all> 386 */ 387 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 388 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 389 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 390 391 /* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 392 393 Cookie field exclusively used by SW. 394 395 396 397 In case of 'NULL' pointer, this field is set to 0 398 399 400 401 HW ignores the contents, accept that it passes the 402 programmed value on to other descriptors together with the 403 physical address 404 405 406 407 Field can be used by SW to for example associate the 408 buffers physical address with the virtual address 409 410 The bit definitions as used by SW are within SW HLD 411 specification 412 413 414 415 NOTE1: 416 417 The three most significant bits can have a special 418 meaning in case this struct is embedded in a TX_MPDU_DETAILS 419 STRUCT, and field transmit_bw_restriction is set 420 421 422 423 In case of NON punctured transmission: 424 425 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 426 427 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 428 429 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 430 431 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 432 433 434 435 In case of punctured transmission: 436 437 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 438 439 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 440 441 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 442 443 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 444 445 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 446 447 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 448 449 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 450 451 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 452 453 454 455 Note: a punctured transmission is indicated by the 456 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 457 TLV 458 459 460 461 NOTE 2:The five most significant bits can have a special 462 meaning in case this struct is embedded in an 463 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 464 configured for passing on the additional info 465 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 466 (FR56821). This is not supported in HastingsPrime, Pine or 467 Moselle. 468 469 470 471 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 472 control field 473 474 475 476 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 477 indicates MPDUs with a QoS control field. 478 479 480 481 482 483 <legal all> 484 */ 485 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 486 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 487 #define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 488 489 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 490 491 492 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 493 494 Consumer: REO/SW/FW 495 496 Producer: RXDMA 497 498 499 500 The number of MSDUs within the MPDU 501 502 <legal all> 503 */ 504 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 505 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 506 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 507 508 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 509 510 Consumer: REO/SW/FW 511 512 Producer: RXDMA 513 514 515 516 The field can have two different meanings based on the 517 setting of field 'BAR_frame': 518 519 520 521 'BAR_frame' is NOT set: 522 523 The MPDU sequence number of the received frame. 524 525 526 527 'BAR_frame' is set. 528 529 The MPDU Start sequence number from the BAR frame 530 531 <legal all> 532 */ 533 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 534 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 535 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 536 537 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 538 539 Consumer: REO/SW/FW 540 541 Producer: RXDMA 542 543 544 545 When set, this MPDU is a fragment and REO should forward 546 this fragment MPDU to the REO destination ring without any 547 reorder checks, pn checks or bitmap update. This implies 548 that REO is forwarding the pointer to the MSDU link 549 descriptor. The destination ring is coming from a 550 programmable register setting in REO 551 552 553 554 <legal all> 555 */ 556 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 557 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 558 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 559 560 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 561 562 Consumer: REO/SW/FW 563 564 Producer: RXDMA 565 566 567 568 The retry bit setting from the MPDU header of the 569 received frame 570 571 <legal all> 572 */ 573 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 574 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 575 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 576 577 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 578 579 Consumer: REO/SW/FW 580 581 Producer: RXDMA 582 583 584 585 When set, the MPDU was received as part of an A-MPDU. 586 587 <legal all> 588 */ 589 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 590 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 591 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 592 593 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 594 595 Consumer: REO/SW/FW 596 597 Producer: RXDMA 598 599 600 601 When set, the received frame is a BAR frame. After 602 processing, this frame shall be pushed to SW or deleted. 603 604 <legal all> 605 */ 606 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 607 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 608 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 609 610 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 611 612 Consumer: REO/SW/FW 613 614 Producer: RXDMA 615 616 617 618 Copied here by RXDMA from RX_MPDU_END 619 620 When not set, REO will Not perform a PN sequence number 621 check 622 */ 623 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 624 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 625 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 626 627 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 628 629 When set, OLE found a valid SA entry for all MSDUs in 630 this MPDU 631 632 <legal all> 633 */ 634 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 635 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 636 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 637 638 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 639 640 When set, at least 1 MSDU within the MPDU has an 641 unsuccessful MAC source address search due to the expiration 642 of the search timer. 643 644 <legal all> 645 */ 646 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 647 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 648 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 649 650 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 651 652 When set, OLE found a valid DA entry for all MSDUs in 653 this MPDU 654 655 <legal all> 656 */ 657 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 658 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 659 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 660 661 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 662 663 Field Only valid if da_is_valid is set 664 665 666 667 When set, at least one of the DA addresses is a 668 Multicast or Broadcast address. 669 670 <legal all> 671 */ 672 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 673 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 674 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 675 676 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 677 678 When set, at least 1 MSDU within the MPDU has an 679 unsuccessful MAC destination address search due to the 680 expiration of the search timer. 681 682 <legal all> 683 */ 684 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 685 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 686 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 687 688 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 689 690 Field only valid when first_msdu_in_mpdu_flag is set. 691 692 693 694 When set, the contents in the MSDU buffer contains a 695 'RAW' MPDU. This 'RAW' MPDU might be spread out over 696 multiple MSDU buffers. 697 698 <legal all> 699 */ 700 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 701 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 702 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 703 704 /* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 705 706 The More Fragment bit setting from the MPDU header of 707 the received frame 708 709 710 711 <legal all> 712 */ 713 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 714 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 715 #define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 716 717 /* Description SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 718 719 Meta data that SW has programmed in the Peer table entry 720 of the transmitting STA. 721 722 <legal all> 723 */ 724 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 725 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 726 #define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 727 728 /* EXTERNAL REFERENCE : struct buffer_addr_info status_buff_addr_info */ 729 730 731 /* Description SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0 732 733 Address (lower 32 bits) of the MSDU buffer OR 734 MSDU_EXTENSION descriptor OR Link Descriptor 735 736 737 738 In case of 'NULL' pointer, this field is set to 0 739 740 <legal all> 741 */ 742 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 743 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 744 #define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 745 746 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32 747 748 Address (upper 8 bits) of the MSDU buffer OR 749 MSDU_EXTENSION descriptor OR Link Descriptor 750 751 752 753 In case of 'NULL' pointer, this field is set to 0 754 755 <legal all> 756 */ 757 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 758 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 759 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 760 761 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER 762 763 Consumer: WBM 764 765 Producer: SW/FW 766 767 768 769 In case of 'NULL' pointer, this field is set to 0 770 771 772 773 Indicates to which buffer manager the buffer OR 774 MSDU_EXTENSION descriptor OR link descriptor that is being 775 pointed to shall be returned after the frame has been 776 processed. It is used by WBM for routing purposes. 777 778 779 780 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 781 to the WMB buffer idle list 782 783 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 784 returned to the WMB idle link descriptor idle list 785 786 <enum 2 FW_BM> This buffer shall be returned to the FW 787 788 <enum 3 SW0_BM> This buffer shall be returned to the SW, 789 ring 0 790 791 <enum 4 SW1_BM> This buffer shall be returned to the SW, 792 ring 1 793 794 <enum 5 SW2_BM> This buffer shall be returned to the SW, 795 ring 2 796 797 <enum 6 SW3_BM> This buffer shall be returned to the SW, 798 ring 3 799 800 <enum 7 SW4_BM> This buffer shall be returned to the SW, 801 ring 4 802 803 804 805 <legal all> 806 */ 807 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 808 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 809 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 810 811 /* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE 812 813 Cookie field exclusively used by SW. 814 815 816 817 In case of 'NULL' pointer, this field is set to 0 818 819 820 821 HW ignores the contents, accept that it passes the 822 programmed value on to other descriptors together with the 823 physical address 824 825 826 827 Field can be used by SW to for example associate the 828 buffers physical address with the virtual address 829 830 The bit definitions as used by SW are within SW HLD 831 specification 832 833 834 835 NOTE1: 836 837 The three most significant bits can have a special 838 meaning in case this struct is embedded in a TX_MPDU_DETAILS 839 STRUCT, and field transmit_bw_restriction is set 840 841 842 843 In case of NON punctured transmission: 844 845 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 846 847 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 848 849 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 850 851 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 852 853 854 855 In case of punctured transmission: 856 857 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 858 859 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 860 861 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 862 863 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 864 865 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 866 867 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 868 869 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 870 871 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 872 873 874 875 Note: a punctured transmission is indicated by the 876 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 877 TLV 878 879 880 881 NOTE 2:The five most significant bits can have a special 882 meaning in case this struct is embedded in an 883 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 884 configured for passing on the additional info 885 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 886 (FR56821). This is not supported in HastingsPrime, Pine or 887 Moselle. 888 889 890 891 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 892 control field 893 894 895 896 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 897 indicates MPDUs with a QoS control field. 898 899 900 901 902 903 <legal all> 904 */ 905 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 906 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 907 #define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 908 909 /* Description SW_MONITOR_RING_6_RXDMA_PUSH_REASON 910 911 Indicates why RXDMA pushed the frame to this ring 912 913 914 915 <enum 0 rxdma_error_detected> RXDMA detected an error an 916 pushed this frame to this queue 917 918 <enum 1 rxdma_routing_instruction> RXDMA pushed the 919 frame to this queue per received routing instructions. No 920 error within RXDMA was detected 921 922 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 923 result the MSDU link descriptor might not have the 924 last_msdu_in_mpdu_flag set, but instead WBM might just see a 925 NULL pointer in the MSDU link descriptor. This is to be 926 considered a normal condition for this scenario. 927 928 929 930 <legal 0 - 2> 931 */ 932 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 933 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_LSB 0 934 #define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 935 936 /* Description SW_MONITOR_RING_6_RXDMA_ERROR_CODE 937 938 Field only valid when rxdma_push_reason is set to 939 'rxdma_error_detected.' 940 941 942 943 <enum 0 rxdma_overflow_err>MPDU frame is not complete 944 due to a FIFO overflow error in RXPCU. 945 946 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 947 due to receiving incomplete MPDU from the PHY 948 949 950 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 951 error or CRYPTO received an encrypted frame, but did not get 952 a valid corresponding key id in the peer entry. 953 954 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 955 error 956 957 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 958 unencrypted frame error when encrypted was expected 959 960 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 961 length error 962 963 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 964 number of MSDUs allowed in an MPDU got exceeded 965 966 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 967 error 968 969 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 970 parsing error 971 972 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 973 during SA search 974 975 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 976 during DA search 977 978 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 979 timeout during flow search 980 981 <enum 13 rxdma_flush_request>RXDMA received a flush 982 request 983 984 <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 985 present as well as a fragmented MPDU. A-MSDU defragmentation 986 is not supported in Lithium SW so this is treated as an 987 error. 988 */ 989 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 990 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_LSB 2 991 #define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 992 993 /* Description SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER 994 995 Field only valid when Reo_level_mpdu_frame_info. 996 Rx_mpdu_desc_info_details.Fragment_flag is set and 997 end_of_ppdu is set to 0. 998 999 1000 1001 The fragment number from the 802.11 header. 1002 1003 1004 1005 Note that the sequence number is embedded in the field: 1006 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 1007 Mpdu_sequence_number 1008 1009 1010 1011 <legal all> 1012 */ 1013 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 1014 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 1015 #define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 1016 1017 /* Description SW_MONITOR_RING_6_FRAMELESS_BAR 1018 1019 When set, this SW monitor ring struct contains BAR info 1020 from a multi TID BAR frame. The original multi TID BAR frame 1021 itself contained all the REO info for the first TID, but all 1022 the subsequent TID info and their linkage to the REO 1023 descriptors is passed down as 'frameless' BAR info. 1024 1025 1026 1027 The only fields valid in this descriptor when this bit 1028 is within the 1029 1030 Reo_level_mpdu_frame_info: 1031 1032 Within Rx_mpdu_desc_info_details: 1033 1034 Mpdu_Sequence_number 1035 1036 BAR_frame 1037 1038 Peer_meta_data 1039 1040 All other fields shall be set to 0. 1041 1042 1043 1044 <legal all> 1045 */ 1046 #define SW_MONITOR_RING_6_FRAMELESS_BAR_OFFSET 0x00000018 1047 #define SW_MONITOR_RING_6_FRAMELESS_BAR_LSB 11 1048 #define SW_MONITOR_RING_6_FRAMELESS_BAR_MASK 0x00000800 1049 1050 /* Description SW_MONITOR_RING_6_STATUS_BUF_COUNT 1051 1052 A count of status buffers used so far for the PPDU 1053 (either the PPDU that included the MPDU being pushed to SW 1054 if end_of_ppdu = 0, or the PPDU whose end is indicated 1055 through end_of_ppdu = 1) 1056 */ 1057 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_OFFSET 0x00000018 1058 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_LSB 12 1059 #define SW_MONITOR_RING_6_STATUS_BUF_COUNT_MASK 0x0000f000 1060 1061 /* Description SW_MONITOR_RING_6_END_OF_PPDU 1062 1063 Pine RXDMA can be configured to generate a separate 1064 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 1065 through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 1066 demarcate PPDUs. 1067 1068 1069 1070 For such a descriptor, this bit is set to 1 and fields 1071 Reo_level_mpdu_frame_info, mpdu_fragment_number and 1072 Frameless_bar are all set to 0. 1073 1074 1075 1076 Otherwise this bit is set to 0. 1077 */ 1078 #define SW_MONITOR_RING_6_END_OF_PPDU_OFFSET 0x00000018 1079 #define SW_MONITOR_RING_6_END_OF_PPDU_LSB 16 1080 #define SW_MONITOR_RING_6_END_OF_PPDU_MASK 0x00010000 1081 1082 /* Description SW_MONITOR_RING_6_RESERVED_6A 1083 1084 <legal 0> 1085 */ 1086 #define SW_MONITOR_RING_6_RESERVED_6A_OFFSET 0x00000018 1087 #define SW_MONITOR_RING_6_RESERVED_6A_LSB 17 1088 #define SW_MONITOR_RING_6_RESERVED_6A_MASK 0xfffe0000 1089 1090 /* Description SW_MONITOR_RING_7_PHY_PPDU_ID 1091 1092 A PPDU counter value that PHY increments for every PPDU 1093 received 1094 1095 The counter value wraps around. Pine RXDMA can be 1096 configured to copy this from the RX_PPDU_START TLV for every 1097 output descriptor. 1098 1099 1100 1101 <legal all> 1102 */ 1103 #define SW_MONITOR_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c 1104 #define SW_MONITOR_RING_7_PHY_PPDU_ID_LSB 0 1105 #define SW_MONITOR_RING_7_PHY_PPDU_ID_MASK 0x0000ffff 1106 1107 /* Description SW_MONITOR_RING_7_RESERVED_7A 1108 1109 <legal 0> 1110 */ 1111 #define SW_MONITOR_RING_7_RESERVED_7A_OFFSET 0x0000001c 1112 #define SW_MONITOR_RING_7_RESERVED_7A_LSB 16 1113 #define SW_MONITOR_RING_7_RESERVED_7A_MASK 0x000f0000 1114 1115 /* Description SW_MONITOR_RING_7_RING_ID 1116 1117 Consumer: SW/REO/DEBUG 1118 1119 Producer: SRNG (of RXDMA) 1120 1121 1122 1123 For debugging. 1124 1125 This field is filled in by the SRNG module. 1126 1127 It help to identify the ring that is being looked <legal 1128 all> 1129 */ 1130 #define SW_MONITOR_RING_7_RING_ID_OFFSET 0x0000001c 1131 #define SW_MONITOR_RING_7_RING_ID_LSB 20 1132 #define SW_MONITOR_RING_7_RING_ID_MASK 0x0ff00000 1133 1134 /* Description SW_MONITOR_RING_7_LOOPING_COUNT 1135 1136 Consumer: SW/REO/DEBUG 1137 1138 Producer: SRNG (of RXDMA) 1139 1140 1141 1142 For debugging. 1143 1144 This field is filled in by the SRNG module. 1145 1146 1147 1148 A count value that indicates the number of times the 1149 producer of entries into this Ring has looped around the 1150 ring. 1151 1152 At initialization time, this value is set to 0. On the 1153 first loop, this value is set to 1. After the max value is 1154 reached allowed by the number of bits for this field, the 1155 count value continues with 0 again. 1156 1157 1158 1159 In case SW is the consumer of the ring entries, it can 1160 use this field to figure out up to where the producer of 1161 entries has created new entries. This eliminates the need to 1162 check where the head pointer' of the ring is located once 1163 the SW starts processing an interrupt indicating that new 1164 entries have been put into this ring... 1165 1166 1167 1168 Also note that SW if it wants only needs to look at the 1169 LSB bit of this count value. 1170 1171 <legal all> 1172 */ 1173 #define SW_MONITOR_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1174 #define SW_MONITOR_RING_7_LOOPING_COUNT_LSB 28 1175 #define SW_MONITOR_RING_7_LOOPING_COUNT_MASK 0xf0000000 1176 1177 1178 #endif // _SW_MONITOR_RING_H_ 1179