1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_END_H_ 18 #define _RX_MSDU_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 27 // 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30] 28 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], cumulative_l3_checksum[31:16] 29 // 3 rule_indication_31_0[31:0] 30 // 4 rule_indication_63_32[31:0] 31 // 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16] 32 // 6 ipv6_options_crc[31:0] 33 // 7 tcp_seq_number[31:0] 34 // 8 tcp_ack_number[31:0] 35 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 36 // 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], tcp_udp_chksum_fail[30], ip_chksum_fail[31] 37 // 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] 38 // 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26] 39 // 13 fse_metadata[31:0] 40 // 14 cce_metadata[15:0], sa_sw_peer_id[31:16] 41 // 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10] 42 // 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 43 // 44 // ################ END SUMMARY ################# 45 46 #define NUM_OF_DWORDS_RX_MSDU_END 17 47 48 struct rx_msdu_end { 49 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 50 sw_frame_group_id : 7, //[8:2] 51 reserved_0 : 7, //[15:9] 52 phy_ppdu_id : 16; //[31:16] 53 uint32_t ip_hdr_chksum : 16, //[15:0] 54 reported_mpdu_length : 14, //[29:16] 55 reserved_1a : 2; //[31:30] 56 uint32_t key_id_octet : 8, //[7:0] 57 cce_super_rule : 6, //[13:8] 58 cce_classify_not_done_truncate : 1, //[14] 59 cce_classify_not_done_cce_dis : 1, //[15] 60 cumulative_l3_checksum : 16; //[31:16] 61 uint32_t rule_indication_31_0 : 32; //[31:0] 62 uint32_t rule_indication_63_32 : 32; //[31:0] 63 uint32_t da_offset : 6, //[5:0] 64 sa_offset : 6, //[11:6] 65 da_offset_valid : 1, //[12] 66 sa_offset_valid : 1, //[13] 67 reserved_5a : 2, //[15:14] 68 l3_type : 16; //[31:16] 69 uint32_t ipv6_options_crc : 32; //[31:0] 70 uint32_t tcp_seq_number : 32; //[31:0] 71 uint32_t tcp_ack_number : 32; //[31:0] 72 uint32_t tcp_flag : 9, //[8:0] 73 lro_eligible : 1, //[9] 74 reserved_9a : 6, //[15:10] 75 window_size : 16; //[31:16] 76 uint32_t tcp_udp_chksum : 16, //[15:0] 77 sa_idx_timeout : 1, //[16] 78 da_idx_timeout : 1, //[17] 79 msdu_limit_error : 1, //[18] 80 flow_idx_timeout : 1, //[19] 81 flow_idx_invalid : 1, //[20] 82 wifi_parser_error : 1, //[21] 83 amsdu_parser_error : 1, //[22] 84 sa_is_valid : 1, //[23] 85 da_is_valid : 1, //[24] 86 da_is_mcbc : 1, //[25] 87 l3_header_padding : 2, //[27:26] 88 first_msdu : 1, //[28] 89 last_msdu : 1, //[29] 90 tcp_udp_chksum_fail : 1, //[30] 91 ip_chksum_fail : 1; //[31] 92 uint32_t sa_idx : 16, //[15:0] 93 da_idx_or_sw_peer_id : 16; //[31:16] 94 uint32_t msdu_drop : 1, //[0] 95 reo_destination_indication : 5, //[5:1] 96 flow_idx : 20, //[25:6] 97 reserved_12a : 6; //[31:26] 98 uint32_t fse_metadata : 32; //[31:0] 99 uint32_t cce_metadata : 16, //[15:0] 100 sa_sw_peer_id : 16; //[31:16] 101 uint32_t aggregation_count : 8, //[7:0] 102 flow_aggregation_continuation : 1, //[8] 103 fisa_timeout : 1, //[9] 104 reserved_15a : 22; //[31:10] 105 uint32_t cumulative_l4_checksum : 16, //[15:0] 106 cumulative_ip_length : 16; //[31:16] 107 }; 108 109 /* 110 111 rxpcu_mpdu_filter_in_category 112 113 Field indicates what the reason was that this MPDU frame 114 was allowed to come into the receive path by RXPCU 115 116 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 117 frame filter programming of rxpcu 118 119 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 120 regular frame filter and would have been dropped, were it 121 not for the frame fitting into the 'monitor_client' 122 category. 123 124 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 125 regular frame filter and also did not pass the 126 rxpcu_monitor_client filter. It would have been dropped 127 accept that it did pass the 'monitor_other' category. 128 129 <legal 0-2> 130 131 sw_frame_group_id 132 133 SW processes frames based on certain classifications. 134 This field indicates to what sw classification this MPDU is 135 mapped. 136 137 The classification is given in priority order 138 139 140 141 <enum 0 sw_frame_group_NDP_frame> 142 143 144 145 <enum 1 sw_frame_group_Multicast_data> 146 147 <enum 2 sw_frame_group_Unicast_data> 148 149 <enum 3 sw_frame_group_Null_data > This includes mpdus 150 of type Data Null as well as QoS Data Null 151 152 153 154 <enum 4 sw_frame_group_mgmt_0000 > 155 156 <enum 5 sw_frame_group_mgmt_0001 > 157 158 <enum 6 sw_frame_group_mgmt_0010 > 159 160 <enum 7 sw_frame_group_mgmt_0011 > 161 162 <enum 8 sw_frame_group_mgmt_0100 > 163 164 <enum 9 sw_frame_group_mgmt_0101 > 165 166 <enum 10 sw_frame_group_mgmt_0110 > 167 168 <enum 11 sw_frame_group_mgmt_0111 > 169 170 <enum 12 sw_frame_group_mgmt_1000 > 171 172 <enum 13 sw_frame_group_mgmt_1001 > 173 174 <enum 14 sw_frame_group_mgmt_1010 > 175 176 <enum 15 sw_frame_group_mgmt_1011 > 177 178 <enum 16 sw_frame_group_mgmt_1100 > 179 180 <enum 17 sw_frame_group_mgmt_1101 > 181 182 <enum 18 sw_frame_group_mgmt_1110 > 183 184 <enum 19 sw_frame_group_mgmt_1111 > 185 186 187 188 <enum 20 sw_frame_group_ctrl_0000 > 189 190 <enum 21 sw_frame_group_ctrl_0001 > 191 192 <enum 22 sw_frame_group_ctrl_0010 > 193 194 <enum 23 sw_frame_group_ctrl_0011 > 195 196 <enum 24 sw_frame_group_ctrl_0100 > 197 198 <enum 25 sw_frame_group_ctrl_0101 > 199 200 <enum 26 sw_frame_group_ctrl_0110 > 201 202 <enum 27 sw_frame_group_ctrl_0111 > 203 204 <enum 28 sw_frame_group_ctrl_1000 > 205 206 <enum 29 sw_frame_group_ctrl_1001 > 207 208 <enum 30 sw_frame_group_ctrl_1010 > 209 210 <enum 31 sw_frame_group_ctrl_1011 > 211 212 <enum 32 sw_frame_group_ctrl_1100 > 213 214 <enum 33 sw_frame_group_ctrl_1101 > 215 216 <enum 34 sw_frame_group_ctrl_1110 > 217 218 <enum 35 sw_frame_group_ctrl_1111 > 219 220 221 222 <enum 36 sw_frame_group_unsupported> This covers type 3 223 and protocol version != 0 224 225 226 227 228 229 230 <legal 0-37> 231 232 reserved_0 233 234 <legal 0> 235 236 phy_ppdu_id 237 238 A ppdu counter value that PHY increments for every PPDU 239 received. The counter value wraps around 240 241 <legal all> 242 243 ip_hdr_chksum 244 245 This can include the IP header checksum or the pseudo 246 header checksum used by TCP/UDP checksum. 247 248 (with the first byte in the MSB and the second byte in 249 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 250 w.r.t. the byte order in a packet) 251 252 reported_mpdu_length 253 254 MPDU length before decapsulation. Only valid when 255 first_msdu is set. This field is taken directly from the 256 length field of the A-MPDU delimiter or the preamble length 257 field for non-A-MPDU frames. 258 259 reserved_1a 260 261 <legal 0> 262 263 key_id_octet 264 265 The key ID octet from the IV. Only valid when 266 first_msdu is set. 267 268 cce_super_rule 269 270 Indicates the super filter rule 271 272 cce_classify_not_done_truncate 273 274 Classification failed due to truncated frame 275 276 cce_classify_not_done_cce_dis 277 278 Classification failed due to CCE global disable 279 280 cumulative_l3_checksum 281 282 FISA: IP header checksum including the total MSDU length 283 that is part of this flow aggregated so far, reported if 284 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 285 286 287 288 Set to zero in chips not supporting FISA, e.g. Pine 289 290 <legal all> 291 292 rule_indication_31_0 293 294 Bitmap indicating which of rules 31-0 have matched 295 296 rule_indication_63_32 297 298 Bitmap indicating which of rules 63-32 have matched 299 300 da_offset 301 302 Offset into MSDU buffer for DA 303 304 sa_offset 305 306 Offset into MSDU buffer for SA 307 308 da_offset_valid 309 310 da_offset field is valid. This will be set to 0 in case 311 of a dynamic A-MSDU when DA is compressed 312 313 sa_offset_valid 314 315 sa_offset field is valid. This will be set to 0 in case 316 of a dynamic A-MSDU when SA is compressed 317 318 reserved_5a 319 320 <legal 0> 321 322 l3_type 323 324 The 16-bit type value indicating the type of L3 later 325 extracted from LLC/SNAP, set to zero if SNAP is not 326 available 327 328 ipv6_options_crc 329 330 32 bit CRC computed out of IP v6 extension headers 331 332 tcp_seq_number 333 334 TCP sequence number (as a number assembled from a TCP 335 packet in big-endian order, i.e. requiring a byte-swap for 336 little-endian FW/SW w.r.t. the byte order in a packet) 337 338 339 340 In Pine, if 'RXOLE_R0_MISC_CONFIG. 341 OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from 342 'RX_MSDU_START' will be reported here: 343 344 Controlled by multiple RxOLE registers for TCP/UDP over 345 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 346 or IPv6 src/dest addresses is reported; or, Toeplitz hash 347 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 348 src/dest ports is reported. The Flow_id_toeplitz hash can 349 also be reported here. Usually the hash reported here is the 350 one used for hash-based REO routing (see 351 use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). 352 Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 353 src/dest addresses and L4 protocol can be reported here. 354 355 (Unsupported in HastingsPrime) 356 357 tcp_ack_number 358 359 TCP acknowledge number (as a number assembled from a TCP 360 packet in big-endian order, i.e. requiring a byte-swap for 361 little-endian FW/SW w.r.t. the byte order in a packet) 362 363 364 365 In Pine, if 'RXOLE_R0_MISC_CONFIG. 366 OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from 367 'RX_MSDU_START' will be reported here: 368 369 Toeplitz hash of 5-tuple {IP source address, IP 370 destination address, IP source port, IP destination port, L4 371 protocol} in case of non-IPSec. In case of IPSec - Toeplitz 372 hash of 4-tuple {IP source address, IP destination address, 373 SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over 374 IPv4 or IPv6 src/dest addresses and L4 protocol can be 375 reported here. 376 377 The relevant Toeplitz key registers are provided in 378 RxOLE's instance of common parser module. These registers 379 are separate from the Toeplitz keys used by ASE/FSE modules 380 inside RxOLE. The actual value will be passed on from common 381 parser module to RxOLE in one of the WHO_* TLVs. 382 383 (Unsupported in HastingsPrime) 384 385 tcp_flag 386 387 TCP flags 388 389 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 390 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 391 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 392 the byte order in a packet) 393 394 lro_eligible 395 396 Computed out of TCP and IP fields to indicate that this 397 MSDU is eligible for LRO 398 399 reserved_9a 400 401 NOTE: DO not assign a field... Internally used in 402 RXOLE.. 403 404 <legal 0> 405 406 window_size 407 408 TCP receive window size (as a number assembled from a 409 TCP packet in big-endian order, i.e. requiring a byte-swap 410 for little-endian FW/SW w.r.t. the byte order in a packet) 411 412 413 414 In Pine, if 'RXOLE_R0_MISC_CONFIG. 415 OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from 416 'RX_MSDU_START' will be reported in the 14 LSBs here: 417 418 MSDU length in bytes after decapsulation. This field is 419 still valid for MPDU frames without A-MSDU. It still 420 represents MSDU length after decapsulation. 421 422 (Unsupported in HastingsPrime) 423 424 tcp_udp_chksum 425 426 The value of the computed TCP/UDP checksum. A mode bit 427 selects whether this checksum is the full checksum or the 428 partial checksum which does not include the pseudo header. 429 (with the first byte in the MSB and the second byte in the 430 LSB, i.e. requiring a byte-swap for little-endian FW/SW 431 w.r.t. the byte order in a packet) 432 433 sa_idx_timeout 434 435 Indicates an unsuccessful MAC source address search due 436 to the expiring of the search timer. 437 438 da_idx_timeout 439 440 Indicates an unsuccessful MAC destination address search 441 due to the expiring of the search timer. 442 443 msdu_limit_error 444 445 Indicates that the MSDU threshold was exceeded and thus 446 all the rest of the MSDUs will not be scattered and will not 447 be decapsulated but will be DMA'ed in RAW format as a single 448 MSDU buffer 449 450 flow_idx_timeout 451 452 Indicates an unsuccessful flow search due to the 453 expiring of the search timer. 454 455 <legal all> 456 457 flow_idx_invalid 458 459 flow id is not valid 460 461 <legal all> 462 463 wifi_parser_error 464 465 Indicates that the WiFi frame has one of the following 466 errors 467 468 o has less than minimum allowed bytes as per standard 469 470 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 471 472 <legal all> 473 474 amsdu_parser_error 475 476 A-MSDU could not be properly de-agregated. 477 478 <legal all> 479 480 sa_is_valid 481 482 Indicates that OLE found a valid SA entry 483 484 da_is_valid 485 486 Indicates that OLE found a valid DA entry 487 488 da_is_mcbc 489 490 Field Only valid if da_is_valid is set 491 492 493 494 Indicates the DA address was a Multicast of Broadcast 495 address. 496 497 l3_header_padding 498 499 Number of bytes padded to make sure that the L3 header 500 will always start of a Dword boundary 501 502 first_msdu 503 504 Indicates the first MSDU of A-MSDU. If both first_msdu 505 and last_msdu are set in the MSDU then this is a 506 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 507 A-MSDU shall have both first_mpdu and last_mpdu bits set to 508 0. 509 510 last_msdu 511 512 Indicates the last MSDU of the A-MSDU. MPDU end status 513 is only valid when last_msdu is set. 514 515 tcp_udp_chksum_fail 516 517 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 518 set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be 519 reported here: 520 521 Indicates that the computed checksum (tcp_udp_chksum) 522 did not match the checksum in the TCP/UDP header. 523 524 (unsupported in HastingsPrime) 525 526 ip_chksum_fail 527 528 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 529 set, ip_chksum_fail from 'RX_MSDU_START' will be reported in 530 the MSB here: 531 532 Indicates that the computed checksum (ip_hdr_chksum) did 533 not match the checksum in the IP header. 534 535 (unsupported in HastingsPrime) 536 537 sa_idx 538 539 The offset in the address table which matches the MAC 540 source address. 541 542 da_idx_or_sw_peer_id 543 544 Based on a register configuration in RXOLE, this field 545 will contain: 546 547 The offset in the address table which matches the MAC 548 destination address 549 550 OR: 551 552 sw_peer_id from the address search entry corresponding 553 to the destination address of the MSDU 554 555 msdu_drop 556 557 When set, REO shall drop this MSDU and not forward it to 558 any other ring... 559 560 <legal all> 561 562 reo_destination_indication 563 564 The ID of the REO exit ring where the MSDU frame shall 565 push after (MPDU level) reordering has finished. 566 567 568 569 <enum 0 reo_destination_tcl> Reo will push the frame 570 into the REO2TCL ring 571 572 <enum 1 reo_destination_sw1> Reo will push the frame 573 into the REO2SW1 ring 574 575 <enum 2 reo_destination_sw2> Reo will push the frame 576 into the REO2SW2 ring 577 578 <enum 3 reo_destination_sw3> Reo will push the frame 579 into the REO2SW3 ring 580 581 <enum 4 reo_destination_sw4> Reo will push the frame 582 into the REO2SW4 ring 583 584 <enum 5 reo_destination_release> Reo will push the frame 585 into the REO_release ring 586 587 <enum 6 reo_destination_fw> Reo will push the frame into 588 the REO2FW ring 589 590 <enum 7 reo_destination_sw5> Reo will push the frame 591 into the REO2SW5 ring (REO remaps this in chips without 592 REO2SW5 ring, e.g. Pine) 593 594 <enum 8 reo_destination_sw6> Reo will push the frame 595 into the REO2SW6 ring (REO remaps this in chips without 596 REO2SW6 ring, e.g. Pine) 597 598 <enum 9 reo_destination_9> REO remaps this <enum 10 599 reo_destination_10> REO remaps this 600 601 <enum 11 reo_destination_11> REO remaps this 602 603 <enum 12 reo_destination_12> REO remaps this <enum 13 604 reo_destination_13> REO remaps this 605 606 <enum 14 reo_destination_14> REO remaps this 607 608 <enum 15 reo_destination_15> REO remaps this 609 610 <enum 16 reo_destination_16> REO remaps this 611 612 <enum 17 reo_destination_17> REO remaps this 613 614 <enum 18 reo_destination_18> REO remaps this 615 616 <enum 19 reo_destination_19> REO remaps this 617 618 <enum 20 reo_destination_20> REO remaps this 619 620 <enum 21 reo_destination_21> REO remaps this 621 622 <enum 22 reo_destination_22> REO remaps this 623 624 <enum 23 reo_destination_23> REO remaps this 625 626 <enum 24 reo_destination_24> REO remaps this 627 628 <enum 25 reo_destination_25> REO remaps this 629 630 <enum 26 reo_destination_26> REO remaps this 631 632 <enum 27 reo_destination_27> REO remaps this 633 634 <enum 28 reo_destination_28> REO remaps this 635 636 <enum 29 reo_destination_29> REO remaps this 637 638 <enum 30 reo_destination_30> REO remaps this 639 640 <enum 31 reo_destination_31> REO remaps this 641 642 643 644 <legal all> 645 646 flow_idx 647 648 Flow table index 649 650 <legal all> 651 652 reserved_12a 653 654 <legal 0> 655 656 fse_metadata 657 658 FSE related meta data: 659 660 <legal all> 661 662 cce_metadata 663 664 CCE related meta data: 665 666 <legal all> 667 668 sa_sw_peer_id 669 670 sw_peer_id from the address search entry corresponding 671 to the source address of the MSDU 672 673 <legal all> 674 675 aggregation_count 676 677 FISA: Number of MSDU's aggregated so far 678 679 680 681 Set to zero in chips not supporting FISA, e.g. Pine 682 683 <legal all> 684 685 flow_aggregation_continuation 686 687 FISA: To indicate that this MSDU can be aggregated with 688 the previous packet with the same flow id 689 690 691 692 Set to zero in chips not supporting FISA, e.g. Pine 693 694 <legal all> 695 696 fisa_timeout 697 698 FISA: To indicate that the aggregation has restarted for 699 this flow due to timeout 700 701 702 703 Set to zero in chips not supporting FISA, e.g. Pine 704 705 <legal all> 706 707 reserved_15a 708 709 <legal 0> 710 711 cumulative_l4_checksum 712 713 FISA: checksum for MSDU's that is part of this flow 714 aggregated so far 715 716 717 718 Set to zero in chips not supporting FISA, e.g. Pine 719 720 <legal all> 721 722 cumulative_ip_length 723 724 FISA: Total MSDU length that is part of this flow 725 aggregated so far 726 727 728 729 Set to zero in chips not supporting FISA, e.g. Pine 730 731 <legal all> 732 */ 733 734 735 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 736 737 Field indicates what the reason was that this MPDU frame 738 was allowed to come into the receive path by RXPCU 739 740 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 741 frame filter programming of rxpcu 742 743 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 744 regular frame filter and would have been dropped, were it 745 not for the frame fitting into the 'monitor_client' 746 category. 747 748 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 749 regular frame filter and also did not pass the 750 rxpcu_monitor_client filter. It would have been dropped 751 accept that it did pass the 'monitor_other' category. 752 753 <legal 0-2> 754 */ 755 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 756 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 757 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 758 759 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 760 761 SW processes frames based on certain classifications. 762 This field indicates to what sw classification this MPDU is 763 mapped. 764 765 The classification is given in priority order 766 767 768 769 <enum 0 sw_frame_group_NDP_frame> 770 771 772 773 <enum 1 sw_frame_group_Multicast_data> 774 775 <enum 2 sw_frame_group_Unicast_data> 776 777 <enum 3 sw_frame_group_Null_data > This includes mpdus 778 of type Data Null as well as QoS Data Null 779 780 781 782 <enum 4 sw_frame_group_mgmt_0000 > 783 784 <enum 5 sw_frame_group_mgmt_0001 > 785 786 <enum 6 sw_frame_group_mgmt_0010 > 787 788 <enum 7 sw_frame_group_mgmt_0011 > 789 790 <enum 8 sw_frame_group_mgmt_0100 > 791 792 <enum 9 sw_frame_group_mgmt_0101 > 793 794 <enum 10 sw_frame_group_mgmt_0110 > 795 796 <enum 11 sw_frame_group_mgmt_0111 > 797 798 <enum 12 sw_frame_group_mgmt_1000 > 799 800 <enum 13 sw_frame_group_mgmt_1001 > 801 802 <enum 14 sw_frame_group_mgmt_1010 > 803 804 <enum 15 sw_frame_group_mgmt_1011 > 805 806 <enum 16 sw_frame_group_mgmt_1100 > 807 808 <enum 17 sw_frame_group_mgmt_1101 > 809 810 <enum 18 sw_frame_group_mgmt_1110 > 811 812 <enum 19 sw_frame_group_mgmt_1111 > 813 814 815 816 <enum 20 sw_frame_group_ctrl_0000 > 817 818 <enum 21 sw_frame_group_ctrl_0001 > 819 820 <enum 22 sw_frame_group_ctrl_0010 > 821 822 <enum 23 sw_frame_group_ctrl_0011 > 823 824 <enum 24 sw_frame_group_ctrl_0100 > 825 826 <enum 25 sw_frame_group_ctrl_0101 > 827 828 <enum 26 sw_frame_group_ctrl_0110 > 829 830 <enum 27 sw_frame_group_ctrl_0111 > 831 832 <enum 28 sw_frame_group_ctrl_1000 > 833 834 <enum 29 sw_frame_group_ctrl_1001 > 835 836 <enum 30 sw_frame_group_ctrl_1010 > 837 838 <enum 31 sw_frame_group_ctrl_1011 > 839 840 <enum 32 sw_frame_group_ctrl_1100 > 841 842 <enum 33 sw_frame_group_ctrl_1101 > 843 844 <enum 34 sw_frame_group_ctrl_1110 > 845 846 <enum 35 sw_frame_group_ctrl_1111 > 847 848 849 850 <enum 36 sw_frame_group_unsupported> This covers type 3 851 and protocol version != 0 852 853 854 855 856 857 858 <legal 0-37> 859 */ 860 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 861 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 862 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 863 864 /* Description RX_MSDU_END_0_RESERVED_0 865 866 <legal 0> 867 */ 868 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 869 #define RX_MSDU_END_0_RESERVED_0_LSB 9 870 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 871 872 /* Description RX_MSDU_END_0_PHY_PPDU_ID 873 874 A ppdu counter value that PHY increments for every PPDU 875 received. The counter value wraps around 876 877 <legal all> 878 */ 879 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 880 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 881 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 882 883 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 884 885 This can include the IP header checksum or the pseudo 886 header checksum used by TCP/UDP checksum. 887 888 (with the first byte in the MSB and the second byte in 889 the LSB, i.e. requiring a byte-swap for little-endian FW/SW 890 w.r.t. the byte order in a packet) 891 */ 892 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 893 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 894 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 895 896 /* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH 897 898 MPDU length before decapsulation. Only valid when 899 first_msdu is set. This field is taken directly from the 900 length field of the A-MPDU delimiter or the preamble length 901 field for non-A-MPDU frames. 902 */ 903 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 904 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 905 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 906 907 /* Description RX_MSDU_END_1_RESERVED_1A 908 909 <legal 0> 910 */ 911 #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 912 #define RX_MSDU_END_1_RESERVED_1A_LSB 30 913 #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 914 915 /* Description RX_MSDU_END_2_KEY_ID_OCTET 916 917 The key ID octet from the IV. Only valid when 918 first_msdu is set. 919 */ 920 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 921 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 922 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 923 924 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 925 926 Indicates the super filter rule 927 */ 928 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 929 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 930 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 931 932 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 933 934 Classification failed due to truncated frame 935 */ 936 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 937 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 938 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 939 940 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 941 942 Classification failed due to CCE global disable 943 */ 944 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 945 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 946 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 947 948 /* Description RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM 949 950 FISA: IP header checksum including the total MSDU length 951 that is part of this flow aggregated so far, reported if 952 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 953 954 955 956 Set to zero in chips not supporting FISA, e.g. Pine 957 958 <legal all> 959 */ 960 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 961 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 962 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 963 964 /* Description RX_MSDU_END_3_RULE_INDICATION_31_0 965 966 Bitmap indicating which of rules 31-0 have matched 967 */ 968 #define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c 969 #define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 970 #define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff 971 972 /* Description RX_MSDU_END_4_RULE_INDICATION_63_32 973 974 Bitmap indicating which of rules 63-32 have matched 975 */ 976 #define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 977 #define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 978 #define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff 979 980 /* Description RX_MSDU_END_5_DA_OFFSET 981 982 Offset into MSDU buffer for DA 983 */ 984 #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 985 #define RX_MSDU_END_5_DA_OFFSET_LSB 0 986 #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f 987 988 /* Description RX_MSDU_END_5_SA_OFFSET 989 990 Offset into MSDU buffer for SA 991 */ 992 #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 993 #define RX_MSDU_END_5_SA_OFFSET_LSB 6 994 #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 995 996 /* Description RX_MSDU_END_5_DA_OFFSET_VALID 997 998 da_offset field is valid. This will be set to 0 in case 999 of a dynamic A-MSDU when DA is compressed 1000 */ 1001 #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 1002 #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 1003 #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 1004 1005 /* Description RX_MSDU_END_5_SA_OFFSET_VALID 1006 1007 sa_offset field is valid. This will be set to 0 in case 1008 of a dynamic A-MSDU when SA is compressed 1009 */ 1010 #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 1011 #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 1012 #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 1013 1014 /* Description RX_MSDU_END_5_RESERVED_5A 1015 1016 <legal 0> 1017 */ 1018 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 1019 #define RX_MSDU_END_5_RESERVED_5A_LSB 14 1020 #define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 1021 1022 /* Description RX_MSDU_END_5_L3_TYPE 1023 1024 The 16-bit type value indicating the type of L3 later 1025 extracted from LLC/SNAP, set to zero if SNAP is not 1026 available 1027 */ 1028 #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 1029 #define RX_MSDU_END_5_L3_TYPE_LSB 16 1030 #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 1031 1032 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 1033 1034 32 bit CRC computed out of IP v6 extension headers 1035 */ 1036 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 1037 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 1038 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 1039 1040 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 1041 1042 TCP sequence number (as a number assembled from a TCP 1043 packet in big-endian order, i.e. requiring a byte-swap for 1044 little-endian FW/SW w.r.t. the byte order in a packet) 1045 1046 1047 1048 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1049 OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from 1050 'RX_MSDU_START' will be reported here: 1051 1052 Controlled by multiple RxOLE registers for TCP/UDP over 1053 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 1054 or IPv6 src/dest addresses is reported; or, Toeplitz hash 1055 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 1056 src/dest ports is reported. The Flow_id_toeplitz hash can 1057 also be reported here. Usually the hash reported here is the 1058 one used for hash-based REO routing (see 1059 use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). 1060 Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 1061 src/dest addresses and L4 protocol can be reported here. 1062 1063 (Unsupported in HastingsPrime) 1064 */ 1065 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 1066 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 1067 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 1068 1069 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 1070 1071 TCP acknowledge number (as a number assembled from a TCP 1072 packet in big-endian order, i.e. requiring a byte-swap for 1073 little-endian FW/SW w.r.t. the byte order in a packet) 1074 1075 1076 1077 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1078 OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from 1079 'RX_MSDU_START' will be reported here: 1080 1081 Toeplitz hash of 5-tuple {IP source address, IP 1082 destination address, IP source port, IP destination port, L4 1083 protocol} in case of non-IPSec. In case of IPSec - Toeplitz 1084 hash of 4-tuple {IP source address, IP destination address, 1085 SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over 1086 IPv4 or IPv6 src/dest addresses and L4 protocol can be 1087 reported here. 1088 1089 The relevant Toeplitz key registers are provided in 1090 RxOLE's instance of common parser module. These registers 1091 are separate from the Toeplitz keys used by ASE/FSE modules 1092 inside RxOLE. The actual value will be passed on from common 1093 parser module to RxOLE in one of the WHO_* TLVs. 1094 1095 (Unsupported in HastingsPrime) 1096 */ 1097 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 1098 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 1099 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 1100 1101 /* Description RX_MSDU_END_9_TCP_FLAG 1102 1103 TCP flags 1104 1105 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit 1106 in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 1107 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 1108 the byte order in a packet) 1109 */ 1110 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 1111 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 1112 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 1113 1114 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 1115 1116 Computed out of TCP and IP fields to indicate that this 1117 MSDU is eligible for LRO 1118 */ 1119 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 1120 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 1121 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 1122 1123 /* Description RX_MSDU_END_9_RESERVED_9A 1124 1125 NOTE: DO not assign a field... Internally used in 1126 RXOLE.. 1127 1128 <legal 0> 1129 */ 1130 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1131 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1132 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1133 1134 /* Description RX_MSDU_END_9_WINDOW_SIZE 1135 1136 TCP receive window size (as a number assembled from a 1137 TCP packet in big-endian order, i.e. requiring a byte-swap 1138 for little-endian FW/SW w.r.t. the byte order in a packet) 1139 1140 1141 1142 In Pine, if 'RXOLE_R0_MISC_CONFIG. 1143 OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from 1144 'RX_MSDU_START' will be reported in the 14 LSBs here: 1145 1146 MSDU length in bytes after decapsulation. This field is 1147 still valid for MPDU frames without A-MSDU. It still 1148 represents MSDU length after decapsulation. 1149 1150 (Unsupported in HastingsPrime) 1151 */ 1152 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1153 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1154 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1155 1156 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM 1157 1158 The value of the computed TCP/UDP checksum. A mode bit 1159 selects whether this checksum is the full checksum or the 1160 partial checksum which does not include the pseudo header. 1161 (with the first byte in the MSB and the second byte in the 1162 LSB, i.e. requiring a byte-swap for little-endian FW/SW 1163 w.r.t. the byte order in a packet) 1164 */ 1165 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 1166 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 1167 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff 1168 1169 /* Description RX_MSDU_END_10_SA_IDX_TIMEOUT 1170 1171 Indicates an unsuccessful MAC source address search due 1172 to the expiring of the search timer. 1173 */ 1174 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 1175 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 1176 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 1177 1178 /* Description RX_MSDU_END_10_DA_IDX_TIMEOUT 1179 1180 Indicates an unsuccessful MAC destination address search 1181 due to the expiring of the search timer. 1182 */ 1183 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 1184 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 1185 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 1186 1187 /* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR 1188 1189 Indicates that the MSDU threshold was exceeded and thus 1190 all the rest of the MSDUs will not be scattered and will not 1191 be decapsulated but will be DMA'ed in RAW format as a single 1192 MSDU buffer 1193 */ 1194 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 1195 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 1196 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 1197 1198 /* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT 1199 1200 Indicates an unsuccessful flow search due to the 1201 expiring of the search timer. 1202 1203 <legal all> 1204 */ 1205 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 1206 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 1207 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 1208 1209 /* Description RX_MSDU_END_10_FLOW_IDX_INVALID 1210 1211 flow id is not valid 1212 1213 <legal all> 1214 */ 1215 #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 1216 #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 1217 #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 1218 1219 /* Description RX_MSDU_END_10_WIFI_PARSER_ERROR 1220 1221 Indicates that the WiFi frame has one of the following 1222 errors 1223 1224 o has less than minimum allowed bytes as per standard 1225 1226 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 1227 1228 <legal all> 1229 */ 1230 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 1231 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 1232 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 1233 1234 /* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR 1235 1236 A-MSDU could not be properly de-agregated. 1237 1238 <legal all> 1239 */ 1240 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 1241 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 1242 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 1243 1244 /* Description RX_MSDU_END_10_SA_IS_VALID 1245 1246 Indicates that OLE found a valid SA entry 1247 */ 1248 #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 1249 #define RX_MSDU_END_10_SA_IS_VALID_LSB 23 1250 #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 1251 1252 /* Description RX_MSDU_END_10_DA_IS_VALID 1253 1254 Indicates that OLE found a valid DA entry 1255 */ 1256 #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 1257 #define RX_MSDU_END_10_DA_IS_VALID_LSB 24 1258 #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 1259 1260 /* Description RX_MSDU_END_10_DA_IS_MCBC 1261 1262 Field Only valid if da_is_valid is set 1263 1264 1265 1266 Indicates the DA address was a Multicast of Broadcast 1267 address. 1268 */ 1269 #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 1270 #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 1271 #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 1272 1273 /* Description RX_MSDU_END_10_L3_HEADER_PADDING 1274 1275 Number of bytes padded to make sure that the L3 header 1276 will always start of a Dword boundary 1277 */ 1278 #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 1279 #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 1280 #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 1281 1282 /* Description RX_MSDU_END_10_FIRST_MSDU 1283 1284 Indicates the first MSDU of A-MSDU. If both first_msdu 1285 and last_msdu are set in the MSDU then this is a 1286 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 1287 A-MSDU shall have both first_mpdu and last_mpdu bits set to 1288 0. 1289 */ 1290 #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 1291 #define RX_MSDU_END_10_FIRST_MSDU_LSB 28 1292 #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 1293 1294 /* Description RX_MSDU_END_10_LAST_MSDU 1295 1296 Indicates the last MSDU of the A-MSDU. MPDU end status 1297 is only valid when last_msdu is set. 1298 */ 1299 #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 1300 #define RX_MSDU_END_10_LAST_MSDU_LSB 29 1301 #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 1302 1303 /* Description RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL 1304 1305 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 1306 set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be 1307 reported here: 1308 1309 Indicates that the computed checksum (tcp_udp_chksum) 1310 did not match the checksum in the TCP/UDP header. 1311 1312 (unsupported in HastingsPrime) 1313 */ 1314 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 1315 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 1316 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 1317 1318 /* Description RX_MSDU_END_10_IP_CHKSUM_FAIL 1319 1320 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is 1321 set, ip_chksum_fail from 'RX_MSDU_START' will be reported in 1322 the MSB here: 1323 1324 Indicates that the computed checksum (ip_hdr_chksum) did 1325 not match the checksum in the IP header. 1326 1327 (unsupported in HastingsPrime) 1328 */ 1329 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 1330 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 1331 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 1332 1333 /* Description RX_MSDU_END_11_SA_IDX 1334 1335 The offset in the address table which matches the MAC 1336 source address. 1337 */ 1338 #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c 1339 #define RX_MSDU_END_11_SA_IDX_LSB 0 1340 #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff 1341 1342 /* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID 1343 1344 Based on a register configuration in RXOLE, this field 1345 will contain: 1346 1347 The offset in the address table which matches the MAC 1348 destination address 1349 1350 OR: 1351 1352 sw_peer_id from the address search entry corresponding 1353 to the destination address of the MSDU 1354 */ 1355 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 1356 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 1357 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 1358 1359 /* Description RX_MSDU_END_12_MSDU_DROP 1360 1361 When set, REO shall drop this MSDU and not forward it to 1362 any other ring... 1363 1364 <legal all> 1365 */ 1366 #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 1367 #define RX_MSDU_END_12_MSDU_DROP_LSB 0 1368 #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 1369 1370 /* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION 1371 1372 The ID of the REO exit ring where the MSDU frame shall 1373 push after (MPDU level) reordering has finished. 1374 1375 1376 1377 <enum 0 reo_destination_tcl> Reo will push the frame 1378 into the REO2TCL ring 1379 1380 <enum 1 reo_destination_sw1> Reo will push the frame 1381 into the REO2SW1 ring 1382 1383 <enum 2 reo_destination_sw2> Reo will push the frame 1384 into the REO2SW2 ring 1385 1386 <enum 3 reo_destination_sw3> Reo will push the frame 1387 into the REO2SW3 ring 1388 1389 <enum 4 reo_destination_sw4> Reo will push the frame 1390 into the REO2SW4 ring 1391 1392 <enum 5 reo_destination_release> Reo will push the frame 1393 into the REO_release ring 1394 1395 <enum 6 reo_destination_fw> Reo will push the frame into 1396 the REO2FW ring 1397 1398 <enum 7 reo_destination_sw5> Reo will push the frame 1399 into the REO2SW5 ring (REO remaps this in chips without 1400 REO2SW5 ring, e.g. Pine) 1401 1402 <enum 8 reo_destination_sw6> Reo will push the frame 1403 into the REO2SW6 ring (REO remaps this in chips without 1404 REO2SW6 ring, e.g. Pine) 1405 1406 <enum 9 reo_destination_9> REO remaps this <enum 10 1407 reo_destination_10> REO remaps this 1408 1409 <enum 11 reo_destination_11> REO remaps this 1410 1411 <enum 12 reo_destination_12> REO remaps this <enum 13 1412 reo_destination_13> REO remaps this 1413 1414 <enum 14 reo_destination_14> REO remaps this 1415 1416 <enum 15 reo_destination_15> REO remaps this 1417 1418 <enum 16 reo_destination_16> REO remaps this 1419 1420 <enum 17 reo_destination_17> REO remaps this 1421 1422 <enum 18 reo_destination_18> REO remaps this 1423 1424 <enum 19 reo_destination_19> REO remaps this 1425 1426 <enum 20 reo_destination_20> REO remaps this 1427 1428 <enum 21 reo_destination_21> REO remaps this 1429 1430 <enum 22 reo_destination_22> REO remaps this 1431 1432 <enum 23 reo_destination_23> REO remaps this 1433 1434 <enum 24 reo_destination_24> REO remaps this 1435 1436 <enum 25 reo_destination_25> REO remaps this 1437 1438 <enum 26 reo_destination_26> REO remaps this 1439 1440 <enum 27 reo_destination_27> REO remaps this 1441 1442 <enum 28 reo_destination_28> REO remaps this 1443 1444 <enum 29 reo_destination_29> REO remaps this 1445 1446 <enum 30 reo_destination_30> REO remaps this 1447 1448 <enum 31 reo_destination_31> REO remaps this 1449 1450 1451 1452 <legal all> 1453 */ 1454 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 1455 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 1456 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e 1457 1458 /* Description RX_MSDU_END_12_FLOW_IDX 1459 1460 Flow table index 1461 1462 <legal all> 1463 */ 1464 #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 1465 #define RX_MSDU_END_12_FLOW_IDX_LSB 6 1466 #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 1467 1468 /* Description RX_MSDU_END_12_RESERVED_12A 1469 1470 <legal 0> 1471 */ 1472 #define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 1473 #define RX_MSDU_END_12_RESERVED_12A_LSB 26 1474 #define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 1475 1476 /* Description RX_MSDU_END_13_FSE_METADATA 1477 1478 FSE related meta data: 1479 1480 <legal all> 1481 */ 1482 #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 1483 #define RX_MSDU_END_13_FSE_METADATA_LSB 0 1484 #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff 1485 1486 /* Description RX_MSDU_END_14_CCE_METADATA 1487 1488 CCE related meta data: 1489 1490 <legal all> 1491 */ 1492 #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 1493 #define RX_MSDU_END_14_CCE_METADATA_LSB 0 1494 #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff 1495 1496 /* Description RX_MSDU_END_14_SA_SW_PEER_ID 1497 1498 sw_peer_id from the address search entry corresponding 1499 to the source address of the MSDU 1500 1501 <legal all> 1502 */ 1503 #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 1504 #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 1505 #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 1506 1507 /* Description RX_MSDU_END_15_AGGREGATION_COUNT 1508 1509 FISA: Number of MSDU's aggregated so far 1510 1511 1512 1513 Set to zero in chips not supporting FISA, e.g. Pine 1514 1515 <legal all> 1516 */ 1517 #define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c 1518 #define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 1519 #define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff 1520 1521 /* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION 1522 1523 FISA: To indicate that this MSDU can be aggregated with 1524 the previous packet with the same flow id 1525 1526 1527 1528 Set to zero in chips not supporting FISA, e.g. Pine 1529 1530 <legal all> 1531 */ 1532 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c 1533 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 1534 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 1535 1536 /* Description RX_MSDU_END_15_FISA_TIMEOUT 1537 1538 FISA: To indicate that the aggregation has restarted for 1539 this flow due to timeout 1540 1541 1542 1543 Set to zero in chips not supporting FISA, e.g. Pine 1544 1545 <legal all> 1546 */ 1547 #define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c 1548 #define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 1549 #define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 1550 1551 /* Description RX_MSDU_END_15_RESERVED_15A 1552 1553 <legal 0> 1554 */ 1555 #define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c 1556 #define RX_MSDU_END_15_RESERVED_15A_LSB 10 1557 #define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 1558 1559 /* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM 1560 1561 FISA: checksum for MSDU's that is part of this flow 1562 aggregated so far 1563 1564 1565 1566 Set to zero in chips not supporting FISA, e.g. Pine 1567 1568 <legal all> 1569 */ 1570 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 1571 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 1572 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 1573 1574 /* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH 1575 1576 FISA: Total MSDU length that is part of this flow 1577 aggregated so far 1578 1579 1580 1581 Set to zero in chips not supporting FISA, e.g. Pine 1582 1583 <legal all> 1584 */ 1585 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 1586 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 1587 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 1588 1589 1590 #endif // _RX_MSDU_END_H_ 1591