1 /*
2  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _RX_MPDU_LINK_PTR_H_
18 #define _RX_MPDU_LINK_PTR_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #include "buffer_addr_info.h"
23 
24 // ################ START SUMMARY #################
25 //
26 //	Dword	Fields
27 //	0-1	struct buffer_addr_info mpdu_link_desc_addr_info;
28 //
29 // ################ END SUMMARY #################
30 
31 #define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
32 
33 struct rx_mpdu_link_ptr {
34     struct            buffer_addr_info                       mpdu_link_desc_addr_info;
35 };
36 
37 /*
38 
39 struct buffer_addr_info mpdu_link_desc_addr_info
40 
41 			Details of the physical address of an MPDU link
42 			descriptor
43 */
44 
45 
46  /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
47 
48 
49 /* Description		RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
50 
51 			Address (lower 32 bits) of the MSDU buffer OR
52 			MSDU_EXTENSION descriptor OR Link Descriptor
53 
54 
55 
56 			In case of 'NULL' pointer, this field is set to 0
57 
58 			<legal all>
59 */
60 #define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
61 #define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
62 #define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
63 
64 /* Description		RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
65 
66 			Address (upper 8 bits) of the MSDU buffer OR
67 			MSDU_EXTENSION descriptor OR Link Descriptor
68 
69 
70 
71 			In case of 'NULL' pointer, this field is set to 0
72 
73 			<legal all>
74 */
75 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
76 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
77 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
78 
79 /* Description		RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
80 
81 			Consumer: WBM
82 
83 			Producer: SW/FW
84 
85 
86 
87 			In case of 'NULL' pointer, this field is set to 0
88 
89 
90 
91 			Indicates to which buffer manager the buffer OR
92 			MSDU_EXTENSION descriptor OR link descriptor that is being
93 			pointed to shall be returned after the frame has been
94 			processed. It is used by WBM for routing purposes.
95 
96 
97 
98 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
99 			to the WMB buffer idle list
100 
101 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
102 			returned to the WMB idle link descriptor idle list
103 
104 			<enum 2 FW_BM> This buffer shall be returned to the FW
105 
106 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
107 			ring 0
108 
109 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
110 			ring 1
111 
112 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
113 			ring 2
114 
115 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
116 			ring 3
117 
118 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
119 			ring 4
120 
121 
122 
123 			<legal all>
124 */
125 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
126 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
127 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
128 
129 /* Description		RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
130 
131 			Cookie field exclusively used by SW.
132 
133 
134 
135 			In case of 'NULL' pointer, this field is set to 0
136 
137 
138 
139 			HW ignores the contents, accept that it passes the
140 			programmed value on to other descriptors together with the
141 			physical address
142 
143 
144 
145 			Field can be used by SW to for example associate the
146 			buffers physical address with the virtual address
147 
148 			The bit definitions as used by SW are within SW HLD
149 			specification
150 
151 
152 
153 			NOTE1:
154 
155 			The three most significant bits can have a special
156 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
157 			STRUCT, and field transmit_bw_restriction is set
158 
159 
160 
161 			In case of NON punctured transmission:
162 
163 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
164 
165 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
166 
167 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
168 
169 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
170 
171 
172 
173 			In case of punctured transmission:
174 
175 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
176 
177 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
178 
179 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
180 
181 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
182 
183 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
184 
185 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
186 
187 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
188 
189 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
190 
191 
192 
193 			Note: a punctured transmission is indicated by the
194 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
195 			TLV
196 
197 
198 
199 			NOTE 2:The five most significant bits can have a special
200 			meaning in case this struct is embedded in an
201 			RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
202 			configured for passing on the additional info
203 			from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
204 			(FR56821). This is not supported in HastingsPrime, Pine or
205 			Moselle.
206 
207 
208 
209 			Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
210 			control field
211 
212 
213 
214 			Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
215 			indicates MPDUs with a QoS control field.
216 
217 
218 
219 
220 
221 			<legal all>
222 */
223 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
224 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
225 #define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
226 
227 
228 #endif // _RX_MPDU_LINK_PTR_H_
229