1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_FLOW_SEARCH_ENTRY_H_ 18 #define _RX_FLOW_SEARCH_ENTRY_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 src_ip_127_96[31:0] 27 // 1 src_ip_95_64[31:0] 28 // 2 src_ip_63_32[31:0] 29 // 3 src_ip_31_0[31:0] 30 // 4 dest_ip_127_96[31:0] 31 // 5 dest_ip_95_64[31:0] 32 // 6 dest_ip_63_32[31:0] 33 // 7 dest_ip_31_0[31:0] 34 // 8 src_port[15:0], dest_port[31:16] 35 // 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30] 36 // 10 metadata[31:0] 37 // 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8] 38 // 12 msdu_byte_count[31:0] 39 // 13 timestamp[31:0] 40 // 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] 41 // 15 tcp_sequence_number[31:0] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 46 47 struct rx_flow_search_entry { 48 uint32_t src_ip_127_96 : 32; //[31:0] 49 uint32_t src_ip_95_64 : 32; //[31:0] 50 uint32_t src_ip_63_32 : 32; //[31:0] 51 uint32_t src_ip_31_0 : 32; //[31:0] 52 uint32_t dest_ip_127_96 : 32; //[31:0] 53 uint32_t dest_ip_95_64 : 32; //[31:0] 54 uint32_t dest_ip_63_32 : 32; //[31:0] 55 uint32_t dest_ip_31_0 : 32; //[31:0] 56 uint32_t src_port : 16, //[15:0] 57 dest_port : 16; //[31:16] 58 uint32_t l4_protocol : 8, //[7:0] 59 valid : 1, //[8] 60 reserved_9 : 15, //[23:9] 61 reo_destination_indication : 5, //[28:24] 62 msdu_drop : 1, //[29] 63 reo_destination_handler : 2; //[31:30] 64 uint32_t metadata : 32; //[31:0] 65 uint32_t aggregation_count : 7, //[6:0] 66 lro_eligible : 1, //[7] 67 msdu_count : 24; //[31:8] 68 uint32_t msdu_byte_count : 32; //[31:0] 69 uint32_t timestamp : 32; //[31:0] 70 uint32_t cumulative_l4_checksum : 16, //[15:0] 71 cumulative_ip_length : 16; //[31:16] 72 uint32_t tcp_sequence_number : 32; //[31:0] 73 }; 74 75 /* 76 77 src_ip_127_96 78 79 Uppermost 32 bits of source IPv6 address or prefix as 80 per Common Parser register field IP_DA_SA_PREFIX (with the 81 first byte in the MSB and the last byte in the LSB, i.e. 82 requiring a byte-swap for little-endian SW w.r.t. the byte 83 order in an IPv6 packet) 84 85 <legal all> 86 87 src_ip_95_64 88 89 Next 32 bits of source IPv6 address or prefix (requiring 90 a byte-swap for little-endian SW) <legal all> 91 92 src_ip_63_32 93 94 Next 32 bits of source IPv6 address or lowest 32 bits of 95 prefix (requiring a byte-swap for little-endian SW) 96 97 <legal all> 98 99 src_ip_31_0 100 101 Lowest 32 bits of source IPv6 address, or source IPv4 102 address (requiring a byte-swap for little-endian SW w.r.t. 103 the byte order in an IPv6 or IPv4 packet) 104 105 <legal all> 106 107 dest_ip_127_96 108 109 Uppermost 32 bits of destination IPv6 address or prefix 110 as per Common Parser register field IP_DA_SA_PREFIX (with 111 the first byte in the MSB and the last byte in the LSB, i.e. 112 requiring a byte-swap for little-endian SW w.r.t. the byte 113 order as in an IPv6 packet) 114 115 <legal all> 116 117 dest_ip_95_64 118 119 Next 32 bits of destination IPv6 address or prefix 120 (requiring a byte-swap for little-endian SW) 121 122 <legal all> 123 124 dest_ip_63_32 125 126 Next 32 bits of destination IPv6 address or lowest 32 127 bits of prefix (requiring a byte-swap for little-endian SW) 128 129 <legal all> 130 131 dest_ip_31_0 132 133 Lowest 32 bits of destination IPv6 address, or 134 destination IPv4 address (requiring a byte-swap for 135 little-endian SW w.r.t. the byte order in an IPv6 or IPv4 136 packet) 137 138 <legal all> 139 140 src_port 141 142 LSB of SPI in case of ESP/AH 143 144 else source port in case of TCP/UDP without IPsec, 145 146 else zeros in case of ICMP (with the first/third byte in 147 the MSB and the second/fourth byte in the LSB, i.e. 148 requiring a byte-swap for little-endian SW w.r.t. the byte 149 order as in an IPv6 or IPv4 packet) <legal all> 150 151 dest_port 152 153 MSB of SPI in case of ESP/AH 154 155 else destination port in case of TCP/UDP without IPsec, 156 157 else zeros in case of ICMP (with the first byte in the 158 MSB and the second byte in the LSB, i.e. requiring a 159 byte-swap for little-endian SW w.r.t. the byte order as in 160 an IPv6 or IPv4 packet) 161 162 <legal all> 163 164 l4_protocol 165 166 IPsec or L4 protocol 167 168 169 170 <enum 1 ICMPV4> 171 172 <enum 6 TCP> 173 174 <enum 17 UDP> 175 176 <enum 50 ESP> 177 178 <enum 51 AH> 179 180 <enum 58 ICMPV6> 181 182 <legal 1, 6, 17, 50, 51, 58> 183 184 valid 185 186 Indicates validity of entry 187 188 <legal all> 189 190 reserved_9 191 192 <legal 0> 193 194 reo_destination_indication 195 196 The ID of the REO exit ring where the MSDU frame shall 197 push after (MPDU level) reordering has finished. 198 199 200 201 <enum 0 reo_destination_tcl> Reo will push the frame 202 into the REO2TCL ring 203 204 <enum 1 reo_destination_sw1> Reo will push the frame 205 into the REO2SW1 ring 206 207 <enum 2 reo_destination_sw2> Reo will push the frame 208 into the REO2SW2 ring 209 210 <enum 3 reo_destination_sw3> Reo will push the frame 211 into the REO2SW3 ring 212 213 <enum 4 reo_destination_sw4> Reo will push the frame 214 into the REO2SW4 ring 215 216 <enum 5 reo_destination_release> Reo will push the frame 217 into the REO_release ring 218 219 <enum 6 reo_destination_fw> Reo will push the frame into 220 the REO2FW ring 221 222 <enum 7 reo_destination_sw5> Reo will push the frame 223 into the REO2SW5 ring (REO remaps this in chips without 224 REO2SW5 ring, e.g. Pine) 225 226 <enum 8 reo_destination_sw6> Reo will push the frame 227 into the REO2SW6 ring (REO remaps this in chips without 228 REO2SW6 ring, e.g. Pine) 229 230 <enum 9 reo_destination_9> REO remaps this <enum 10 231 reo_destination_10> REO remaps this 232 233 <enum 11 reo_destination_11> REO remaps this 234 235 <enum 12 reo_destination_12> REO remaps this <enum 13 236 reo_destination_13> REO remaps this 237 238 <enum 14 reo_destination_14> REO remaps this 239 240 <enum 15 reo_destination_15> REO remaps this 241 242 <enum 16 reo_destination_16> REO remaps this 243 244 <enum 17 reo_destination_17> REO remaps this 245 246 <enum 18 reo_destination_18> REO remaps this 247 248 <enum 19 reo_destination_19> REO remaps this 249 250 <enum 20 reo_destination_20> REO remaps this 251 252 <enum 21 reo_destination_21> REO remaps this 253 254 <enum 22 reo_destination_22> REO remaps this 255 256 <enum 23 reo_destination_23> REO remaps this 257 258 <enum 24 reo_destination_24> REO remaps this 259 260 <enum 25 reo_destination_25> REO remaps this 261 262 <enum 26 reo_destination_26> REO remaps this 263 264 <enum 27 reo_destination_27> REO remaps this 265 266 <enum 28 reo_destination_28> REO remaps this 267 268 <enum 29 reo_destination_29> REO remaps this 269 270 <enum 30 reo_destination_30> REO remaps this 271 272 <enum 31 reo_destination_31> REO remaps this 273 274 275 276 <legal all> 277 278 msdu_drop 279 280 Overriding indication to REO to forward to REO release 281 ring 282 283 <legal all> 284 285 reo_destination_handler 286 287 Indicates how to decide the REO destination indication 288 289 <enum 0 RXFT_USE_FT> Follow this entry 290 291 <enum 1 RXFT_USE_ASPT> Use address search+peer table 292 entry 293 294 <enum 2 RXFT_USE_FT2> Follow this entry 295 296 <enum 3 RXFT_USE_CCE> Use CCE super-rule 297 298 <legal all> 299 300 metadata 301 302 Value to be passed to SW if this flow search entry 303 matches 304 305 <legal all> 306 307 aggregation_count 308 309 FISA: Number'of MSDU's aggregated so far 310 311 312 313 Set to zero in chips not supporting FISA, e.g. Pine 314 315 <legal all> 316 317 lro_eligible 318 319 FISA: To indicate whether the previous MSDU for this 320 flow is eligible for LRO/FISA 321 322 323 324 Set to zero in chips not supporting FISA, e.g. Pine 325 326 <legal all> 327 328 msdu_count 329 330 Number of Rx MSDUs matching this flow 331 332 <legal all> 333 334 msdu_byte_count 335 336 Number of bytes in Rx MSDUs matching this flow 337 338 <legal all> 339 340 timestamp 341 342 Time of last reception (as measured at Rx OLE) matching 343 this flow 344 345 <legal all> 346 347 cumulative_l4_checksum 348 349 FISA: checksum 'or MSDU's that is part of this flow 350 aggregated so far 351 352 353 354 Set to zero in chips not supporting FISA, e.g. Pine 355 356 <legal all> 357 358 cumulative_ip_length 359 360 FISA: Total MSDU length that is part of this flow 361 aggregated so far 362 363 364 365 Set to zero in chips not supporting FISA, e.g. Pine 366 367 <legal all> 368 369 tcp_sequence_number 370 371 FISA: TCP Sequence number of the last packet in this 372 flow to detect sequence number jump 373 374 375 376 Set to zero in chips not supporting FISA, e.g. Pine 377 378 <legal all> 379 */ 380 381 382 /* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96 383 384 Uppermost 32 bits of source IPv6 address or prefix as 385 per Common Parser register field IP_DA_SA_PREFIX (with the 386 first byte in the MSB and the last byte in the LSB, i.e. 387 requiring a byte-swap for little-endian SW w.r.t. the byte 388 order in an IPv6 packet) 389 390 <legal all> 391 */ 392 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 393 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 394 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff 395 396 /* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64 397 398 Next 32 bits of source IPv6 address or prefix (requiring 399 a byte-swap for little-endian SW) <legal all> 400 */ 401 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 402 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 403 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff 404 405 /* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32 406 407 Next 32 bits of source IPv6 address or lowest 32 bits of 408 prefix (requiring a byte-swap for little-endian SW) 409 410 <legal all> 411 */ 412 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 413 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 414 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff 415 416 /* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0 417 418 Lowest 32 bits of source IPv6 address, or source IPv4 419 address (requiring a byte-swap for little-endian SW w.r.t. 420 the byte order in an IPv6 or IPv4 packet) 421 422 <legal all> 423 */ 424 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c 425 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 426 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff 427 428 /* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96 429 430 Uppermost 32 bits of destination IPv6 address or prefix 431 as per Common Parser register field IP_DA_SA_PREFIX (with 432 the first byte in the MSB and the last byte in the LSB, i.e. 433 requiring a byte-swap for little-endian SW w.r.t. the byte 434 order as in an IPv6 packet) 435 436 <legal all> 437 */ 438 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 439 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 440 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff 441 442 /* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64 443 444 Next 32 bits of destination IPv6 address or prefix 445 (requiring a byte-swap for little-endian SW) 446 447 <legal all> 448 */ 449 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 450 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 451 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff 452 453 /* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32 454 455 Next 32 bits of destination IPv6 address or lowest 32 456 bits of prefix (requiring a byte-swap for little-endian SW) 457 458 <legal all> 459 */ 460 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 461 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 462 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff 463 464 /* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0 465 466 Lowest 32 bits of destination IPv6 address, or 467 destination IPv4 address (requiring a byte-swap for 468 little-endian SW w.r.t. the byte order in an IPv6 or IPv4 469 packet) 470 471 <legal all> 472 */ 473 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c 474 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 475 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff 476 477 /* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT 478 479 LSB of SPI in case of ESP/AH 480 481 else source port in case of TCP/UDP without IPsec, 482 483 else zeros in case of ICMP (with the first/third byte in 484 the MSB and the second/fourth byte in the LSB, i.e. 485 requiring a byte-swap for little-endian SW w.r.t. the byte 486 order as in an IPv6 or IPv4 packet) <legal all> 487 */ 488 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 489 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 490 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff 491 492 /* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT 493 494 MSB of SPI in case of ESP/AH 495 496 else destination port in case of TCP/UDP without IPsec, 497 498 else zeros in case of ICMP (with the first byte in the 499 MSB and the second byte in the LSB, i.e. requiring a 500 byte-swap for little-endian SW w.r.t. the byte order as in 501 an IPv6 or IPv4 packet) 502 503 <legal all> 504 */ 505 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 506 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 507 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 508 509 /* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL 510 511 IPsec or L4 protocol 512 513 514 515 <enum 1 ICMPV4> 516 517 <enum 6 TCP> 518 519 <enum 17 UDP> 520 521 <enum 50 ESP> 522 523 <enum 51 AH> 524 525 <enum 58 ICMPV6> 526 527 <legal 1, 6, 17, 50, 51, 58> 528 */ 529 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 530 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 531 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff 532 533 /* Description RX_FLOW_SEARCH_ENTRY_9_VALID 534 535 Indicates validity of entry 536 537 <legal all> 538 */ 539 #define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 540 #define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 541 #define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 542 543 /* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9 544 545 <legal 0> 546 */ 547 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 548 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 549 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 550 551 /* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION 552 553 The ID of the REO exit ring where the MSDU frame shall 554 push after (MPDU level) reordering has finished. 555 556 557 558 <enum 0 reo_destination_tcl> Reo will push the frame 559 into the REO2TCL ring 560 561 <enum 1 reo_destination_sw1> Reo will push the frame 562 into the REO2SW1 ring 563 564 <enum 2 reo_destination_sw2> Reo will push the frame 565 into the REO2SW2 ring 566 567 <enum 3 reo_destination_sw3> Reo will push the frame 568 into the REO2SW3 ring 569 570 <enum 4 reo_destination_sw4> Reo will push the frame 571 into the REO2SW4 ring 572 573 <enum 5 reo_destination_release> Reo will push the frame 574 into the REO_release ring 575 576 <enum 6 reo_destination_fw> Reo will push the frame into 577 the REO2FW ring 578 579 <enum 7 reo_destination_sw5> Reo will push the frame 580 into the REO2SW5 ring (REO remaps this in chips without 581 REO2SW5 ring, e.g. Pine) 582 583 <enum 8 reo_destination_sw6> Reo will push the frame 584 into the REO2SW6 ring (REO remaps this in chips without 585 REO2SW6 ring, e.g. Pine) 586 587 <enum 9 reo_destination_9> REO remaps this <enum 10 588 reo_destination_10> REO remaps this 589 590 <enum 11 reo_destination_11> REO remaps this 591 592 <enum 12 reo_destination_12> REO remaps this <enum 13 593 reo_destination_13> REO remaps this 594 595 <enum 14 reo_destination_14> REO remaps this 596 597 <enum 15 reo_destination_15> REO remaps this 598 599 <enum 16 reo_destination_16> REO remaps this 600 601 <enum 17 reo_destination_17> REO remaps this 602 603 <enum 18 reo_destination_18> REO remaps this 604 605 <enum 19 reo_destination_19> REO remaps this 606 607 <enum 20 reo_destination_20> REO remaps this 608 609 <enum 21 reo_destination_21> REO remaps this 610 611 <enum 22 reo_destination_22> REO remaps this 612 613 <enum 23 reo_destination_23> REO remaps this 614 615 <enum 24 reo_destination_24> REO remaps this 616 617 <enum 25 reo_destination_25> REO remaps this 618 619 <enum 26 reo_destination_26> REO remaps this 620 621 <enum 27 reo_destination_27> REO remaps this 622 623 <enum 28 reo_destination_28> REO remaps this 624 625 <enum 29 reo_destination_29> REO remaps this 626 627 <enum 30 reo_destination_30> REO remaps this 628 629 <enum 31 reo_destination_31> REO remaps this 630 631 632 633 <legal all> 634 */ 635 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 636 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 637 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 638 639 /* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP 640 641 Overriding indication to REO to forward to REO release 642 ring 643 644 <legal all> 645 */ 646 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 647 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 648 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 649 650 /* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER 651 652 Indicates how to decide the REO destination indication 653 654 <enum 0 RXFT_USE_FT> Follow this entry 655 656 <enum 1 RXFT_USE_ASPT> Use address search+peer table 657 entry 658 659 <enum 2 RXFT_USE_FT2> Follow this entry 660 661 <enum 3 RXFT_USE_CCE> Use CCE super-rule 662 663 <legal all> 664 */ 665 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 666 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 667 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 668 669 /* Description RX_FLOW_SEARCH_ENTRY_10_METADATA 670 671 Value to be passed to SW if this flow search entry 672 matches 673 674 <legal all> 675 */ 676 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 677 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 678 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff 679 680 /* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT 681 682 FISA: Number'of MSDU's aggregated so far 683 684 685 686 Set to zero in chips not supporting FISA, e.g. Pine 687 688 <legal all> 689 */ 690 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c 691 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 692 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f 693 694 /* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE 695 696 FISA: To indicate whether the previous MSDU for this 697 flow is eligible for LRO/FISA 698 699 700 701 Set to zero in chips not supporting FISA, e.g. Pine 702 703 <legal all> 704 */ 705 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c 706 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 707 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 708 709 /* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT 710 711 Number of Rx MSDUs matching this flow 712 713 <legal all> 714 */ 715 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c 716 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 717 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 718 719 /* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT 720 721 Number of bytes in Rx MSDUs matching this flow 722 723 <legal all> 724 */ 725 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 726 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 727 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff 728 729 /* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP 730 731 Time of last reception (as measured at Rx OLE) matching 732 this flow 733 734 <legal all> 735 */ 736 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 737 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 738 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff 739 740 /* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM 741 742 FISA: checksum 'or MSDU's that is part of this flow 743 aggregated so far 744 745 746 747 Set to zero in chips not supporting FISA, e.g. Pine 748 749 <legal all> 750 */ 751 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 752 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 753 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 754 755 /* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH 756 757 FISA: Total MSDU length that is part of this flow 758 aggregated so far 759 760 761 762 Set to zero in chips not supporting FISA, e.g. Pine 763 764 <legal all> 765 */ 766 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 767 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 768 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 769 770 /* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER 771 772 FISA: TCP Sequence number of the last packet in this 773 flow to detect sequence number jump 774 775 776 777 Set to zero in chips not supporting FISA, e.g. Pine 778 779 <legal all> 780 */ 781 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c 782 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 783 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff 784 785 786 #endif // _RX_FLOW_SEARCH_ENTRY_H_ 787