1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __REO_REG_SEQ_REG_H__ 18 #define __REO_REG_SEQ_REG_H__ 19 20 #include "seq_hwio.h" 21 #include "reo_reg_seq_hwiobase.h" 22 #ifdef SCALE_INCLUDES 23 #include "HALhwio.h" 24 #else 25 #include "msmhwio.h" 26 #endif 27 28 29 /////////////////////////////////////////////////////////////////////////////////////////////// 30 // Register Data for Block REO_REG 31 /////////////////////////////////////////////////////////////////////////////////////////////// 32 33 //// Register REO_R0_GENERAL_ENABLE //// 34 35 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 36 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 37 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xfbffff7f 38 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 39 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 40 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 41 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 42 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 43 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 44 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 45 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 46 do {\ 47 HWIO_INTLOCK(); \ 48 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 49 HWIO_INTFREE();\ 50 } while (0) 51 52 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 53 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x1f 54 55 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 56 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 0x1e 57 58 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 59 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 0x1d 60 61 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 62 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1c 63 64 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x08000000 65 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1b 66 67 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x03800000 68 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x17 69 70 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00400000 71 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x16 72 73 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00200000 74 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x15 75 76 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00100000 77 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x14 78 79 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00080000 80 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x13 81 82 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00040000 83 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x12 84 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00020000 86 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x11 87 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00010000 89 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0x10 90 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00008000 92 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xf 93 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00004000 95 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xe 96 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00002000 98 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xd 99 100 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00001000 101 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xc 102 103 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000e00 104 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x9 105 106 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000100 107 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x8 108 109 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 110 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 111 112 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 113 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 114 115 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 116 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 117 118 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 119 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 120 121 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 122 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 123 124 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 125 126 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 127 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 128 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0x77777777 129 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 0 130 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 131 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 132 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 133 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 134 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 135 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 136 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 137 do {\ 138 HWIO_INTLOCK(); \ 139 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 140 HWIO_INTFREE();\ 141 } while (0) 142 143 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0x70000000 144 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1c 145 146 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x07000000 147 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x18 148 149 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00700000 150 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x14 151 152 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00070000 153 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x10 154 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x00007000 156 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0xc 157 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000700 159 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0x8 160 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00000070 162 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0x4 163 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000007 165 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x0 166 167 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 168 169 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 170 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 171 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0x77777777 172 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 0 173 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 174 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 176 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 177 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 178 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 179 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 180 do {\ 181 HWIO_INTLOCK(); \ 182 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 183 HWIO_INTFREE();\ 184 } while (0) 185 186 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0x70000000 187 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1c 188 189 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x07000000 190 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x18 191 192 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00700000 193 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x14 194 195 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00070000 196 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x10 197 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x00007000 199 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0xc 200 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000700 202 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0x8 203 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00000070 205 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0x4 206 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000007 208 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x0 209 210 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 211 212 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 213 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 214 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0x77777777 215 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 0 216 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 217 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 219 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 220 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 221 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 222 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 223 do {\ 224 HWIO_INTLOCK(); \ 225 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 226 HWIO_INTFREE();\ 227 } while (0) 228 229 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0x70000000 230 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1c 231 232 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x07000000 233 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x18 234 235 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00700000 236 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x14 237 238 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00070000 239 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x10 240 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x00007000 242 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0xc 243 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000700 245 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0x8 246 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00000070 248 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0x4 249 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000007 251 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x0 252 253 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 254 255 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 256 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 257 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0x77777777 258 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 0 259 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 260 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 262 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 263 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 264 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 265 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 266 do {\ 267 HWIO_INTLOCK(); \ 268 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 269 HWIO_INTFREE();\ 270 } while (0) 271 272 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0x70000000 273 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1c 274 275 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x07000000 276 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x18 277 278 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00700000 279 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x14 280 281 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00070000 282 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x10 283 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x00007000 285 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0xc 286 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000700 288 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0x8 289 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00000070 291 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0x4 292 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000007 294 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x0 295 296 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 297 298 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 299 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 300 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0x77777777 301 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 0 302 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 303 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 304 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 305 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 306 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 307 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 308 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 309 do {\ 310 HWIO_INTLOCK(); \ 311 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 312 HWIO_INTFREE();\ 313 } while (0) 314 315 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0x70000000 316 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1c 317 318 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x07000000 319 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x18 320 321 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00700000 322 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x14 323 324 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00070000 325 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x10 326 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x00007000 328 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0xc 329 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000700 331 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0x8 332 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00000070 334 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0x4 335 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000007 337 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x0 338 339 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 340 341 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 342 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 343 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0x77777777 344 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 0 345 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 346 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 348 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 349 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 350 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 351 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 352 do {\ 353 HWIO_INTLOCK(); \ 354 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 355 HWIO_INTFREE();\ 356 } while (0) 357 358 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0x70000000 359 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1c 360 361 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x07000000 362 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x18 363 364 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00700000 365 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x14 366 367 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00070000 368 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x10 369 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x00007000 371 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0xc 372 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000700 374 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0x8 375 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00000070 377 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0x4 378 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000007 380 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x0 381 382 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 383 384 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 385 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 386 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0x77777777 387 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 0 388 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 389 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 391 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 392 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 393 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 394 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 395 do {\ 396 HWIO_INTLOCK(); \ 397 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 398 HWIO_INTFREE();\ 399 } while (0) 400 401 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0x70000000 402 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1c 403 404 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x07000000 405 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x18 406 407 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00700000 408 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x14 409 410 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00070000 411 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x10 412 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x00007000 414 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0xc 415 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000700 417 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0x8 418 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00000070 420 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0x4 421 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000007 423 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x0 424 425 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 426 427 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 428 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 429 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0x77777777 430 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 0 431 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 432 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 434 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 435 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 436 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 437 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 438 do {\ 439 HWIO_INTLOCK(); \ 440 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 441 HWIO_INTFREE();\ 442 } while (0) 443 444 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0x70000000 445 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1c 446 447 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x07000000 448 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x18 449 450 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00700000 451 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x14 452 453 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00070000 454 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x10 455 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x00007000 457 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0xc 458 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000700 460 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0x8 461 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00000070 463 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0x4 464 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000007 466 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x0 467 468 //// Register REO_R0_TIMESTAMP //// 469 470 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 471 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 472 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 473 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 474 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 475 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 476 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 477 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 478 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 479 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 480 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 481 do {\ 482 HWIO_INTLOCK(); \ 483 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 484 HWIO_INTFREE();\ 485 } while (0) 486 487 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 488 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 489 490 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 491 492 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 493 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 494 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x77777777 495 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 496 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 497 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 498 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 499 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 500 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 501 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 502 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 503 do {\ 504 HWIO_INTLOCK(); \ 505 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 506 HWIO_INTFREE();\ 507 } while (0) 508 509 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x70000000 510 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x1c 511 512 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x07000000 513 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x18 514 515 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00700000 516 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0x14 517 518 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00070000 519 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0x10 520 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00007000 522 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0xc 523 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000700 525 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x8 526 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000070 528 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x4 529 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 531 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 532 533 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 534 535 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 537 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x77777777 538 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 540 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 541 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 542 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 543 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 544 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 545 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 546 do {\ 547 HWIO_INTLOCK(); \ 548 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 549 HWIO_INTFREE();\ 550 } while (0) 551 552 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x70000000 553 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0x1c 554 555 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x07000000 556 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0x18 557 558 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00700000 559 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x14 560 561 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x00070000 562 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x10 563 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00007000 565 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0xc 566 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000700 568 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x8 569 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x00000070 571 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 0x4 572 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x00000007 574 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0x0 575 576 //// Register REO_R0_IDLE_REQ_CTRL //// 577 578 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 579 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 580 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 581 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 582 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 583 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 584 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 585 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 586 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 587 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 588 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 589 do {\ 590 HWIO_INTLOCK(); \ 591 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 592 HWIO_INTFREE();\ 593 } while (0) 594 595 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 596 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 597 598 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 599 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 600 601 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 602 603 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 604 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 605 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 606 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 607 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 608 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 609 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 610 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 611 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 612 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 613 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 614 do {\ 615 HWIO_INTLOCK(); \ 616 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 617 HWIO_INTFREE();\ 618 } while (0) 619 620 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 621 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 622 623 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 624 625 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 626 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 627 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 628 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 629 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 630 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 632 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 633 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 634 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 635 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 636 do {\ 637 HWIO_INTLOCK(); \ 638 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 639 HWIO_INTFREE();\ 640 } while (0) 641 642 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 643 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 644 645 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 646 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 647 648 //// Register REO_R0_RXDMA2REO0_RING_ID //// 649 650 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 651 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 652 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 653 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 654 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 655 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 656 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 657 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 658 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 659 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 660 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 661 do {\ 662 HWIO_INTLOCK(); \ 663 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 664 HWIO_INTFREE();\ 665 } while (0) 666 667 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 668 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 669 670 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 671 672 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 673 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 674 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 675 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 676 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 677 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 678 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 679 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 680 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 681 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 682 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 683 do {\ 684 HWIO_INTLOCK(); \ 685 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 686 HWIO_INTFREE();\ 687 } while (0) 688 689 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 690 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 691 692 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 693 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 694 695 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 696 697 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 698 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 699 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff 700 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 701 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 702 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 703 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 704 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 705 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 706 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 707 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 708 do {\ 709 HWIO_INTLOCK(); \ 710 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 711 HWIO_INTFREE();\ 712 } while (0) 713 714 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 715 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe 716 717 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 718 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 719 720 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 721 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 722 723 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 724 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 725 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 727 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 728 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 730 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 731 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 733 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 734 735 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 736 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 737 738 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 739 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 740 741 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 742 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 743 744 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 745 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 746 747 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 748 749 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 750 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 751 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 752 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 753 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 754 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 755 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 756 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 757 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 758 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 759 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 760 do {\ 761 HWIO_INTLOCK(); \ 762 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 763 HWIO_INTFREE();\ 764 } while (0) 765 766 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 767 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 768 769 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 770 771 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 772 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 773 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 774 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 775 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 776 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 777 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 778 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 779 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 780 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 781 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 782 do {\ 783 HWIO_INTLOCK(); \ 784 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 785 HWIO_INTFREE();\ 786 } while (0) 787 788 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 789 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 790 791 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 792 793 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 794 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 795 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 796 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 797 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 798 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 799 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 800 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 801 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 802 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 803 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 804 do {\ 805 HWIO_INTLOCK(); \ 806 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 807 HWIO_INTFREE();\ 808 } while (0) 809 810 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 811 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 812 813 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 814 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 815 816 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 817 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 818 819 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 820 821 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 822 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 823 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 824 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 825 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 826 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 827 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 828 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 829 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 830 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 831 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 832 do {\ 833 HWIO_INTLOCK(); \ 834 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 835 HWIO_INTFREE();\ 836 } while (0) 837 838 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 839 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 840 841 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 842 843 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 844 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 845 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 846 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 847 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 848 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 849 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 850 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 851 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 852 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 853 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 854 do {\ 855 HWIO_INTLOCK(); \ 856 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 857 HWIO_INTFREE();\ 858 } while (0) 859 860 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 861 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 862 863 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 864 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 865 866 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 867 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 868 869 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 870 871 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 872 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 873 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 874 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 875 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 876 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 877 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 878 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 879 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 880 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 881 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 882 do {\ 883 HWIO_INTLOCK(); \ 884 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 885 HWIO_INTFREE();\ 886 } while (0) 887 888 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 889 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 890 891 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 892 893 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 894 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 895 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 896 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 897 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 898 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 899 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 900 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 901 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 902 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 903 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 904 do {\ 905 HWIO_INTLOCK(); \ 906 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 907 HWIO_INTFREE();\ 908 } while (0) 909 910 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 911 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 912 913 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 914 915 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 916 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 917 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 918 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 919 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 920 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 921 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 922 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 923 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 924 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 925 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 926 do {\ 927 HWIO_INTLOCK(); \ 928 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 929 HWIO_INTFREE();\ 930 } while (0) 931 932 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 933 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 934 935 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 936 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 937 938 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 939 940 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 941 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 942 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 943 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 944 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 945 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 946 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 947 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 948 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 949 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 950 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 951 do {\ 952 HWIO_INTLOCK(); \ 953 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 954 HWIO_INTFREE();\ 955 } while (0) 956 957 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 958 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 959 960 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 961 962 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 963 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 964 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 965 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 966 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 967 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 968 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 969 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 970 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 971 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 972 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 973 do {\ 974 HWIO_INTLOCK(); \ 975 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 976 HWIO_INTFREE();\ 977 } while (0) 978 979 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 980 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 981 982 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 983 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 984 985 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 986 987 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 988 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 989 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 990 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 991 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 992 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 993 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 994 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 995 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 996 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 997 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 998 do {\ 999 HWIO_INTLOCK(); \ 1000 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 1001 HWIO_INTFREE();\ 1002 } while (0) 1003 1004 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1005 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 1006 1007 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 1008 1009 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 1010 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 1011 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1012 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1013 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1014 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1015 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1016 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1017 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1018 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1019 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1020 do {\ 1021 HWIO_INTLOCK(); \ 1022 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1023 HWIO_INTFREE();\ 1024 } while (0) 1025 1026 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1027 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1028 1029 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1030 1031 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1032 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1033 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1034 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1035 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1036 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1037 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1038 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1039 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1040 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1041 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1042 do {\ 1043 HWIO_INTLOCK(); \ 1044 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1045 HWIO_INTFREE();\ 1046 } while (0) 1047 1048 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1049 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1050 1051 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1052 1053 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1054 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1055 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1056 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1057 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1058 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1059 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1060 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1061 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1062 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1063 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1064 do {\ 1065 HWIO_INTLOCK(); \ 1066 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1067 HWIO_INTFREE();\ 1068 } while (0) 1069 1070 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1071 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1072 1073 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1074 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1075 1076 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1077 1078 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000094) 1079 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000094) 1080 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1081 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1082 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1083 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1084 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1085 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1086 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1087 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1088 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1089 do {\ 1090 HWIO_INTLOCK(); \ 1091 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1092 HWIO_INTFREE();\ 1093 } while (0) 1094 1095 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1096 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1097 1098 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1099 1100 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000098) 1101 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000098) 1102 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1103 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1104 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1105 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1106 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1107 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1108 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1109 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1110 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1111 do {\ 1112 HWIO_INTLOCK(); \ 1113 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1114 HWIO_INTFREE();\ 1115 } while (0) 1116 1117 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1118 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1119 1120 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1121 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1122 1123 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1124 1125 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000009c) 1126 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000009c) 1127 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff 1128 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1129 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1130 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1131 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1132 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1133 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1134 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1135 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1136 do {\ 1137 HWIO_INTLOCK(); \ 1138 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 1139 HWIO_INTFREE();\ 1140 } while (0) 1141 1142 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1143 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe 1144 1145 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1146 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1147 1148 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1149 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1150 1151 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1152 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1153 1154 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1155 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 1156 1157 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1158 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1159 1160 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1161 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1162 1163 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1164 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1165 1166 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1167 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 1168 1169 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1170 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1171 1172 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1173 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1174 1175 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 1176 1177 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1178 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1179 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 1180 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 1181 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 1182 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 1183 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 1184 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 1185 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 1186 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 1187 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1188 do {\ 1189 HWIO_INTLOCK(); \ 1190 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 1191 HWIO_INTFREE();\ 1192 } while (0) 1193 1194 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1195 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1196 1197 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 1198 1199 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1200 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1201 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 1202 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 1203 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 1204 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 1205 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 1206 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 1207 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 1208 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 1209 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1210 do {\ 1211 HWIO_INTLOCK(); \ 1212 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 1213 HWIO_INTFREE();\ 1214 } while (0) 1215 1216 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1217 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1218 1219 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 1220 1221 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1222 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1223 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1224 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1225 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1226 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1227 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1228 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1229 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1230 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1231 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1232 do {\ 1233 HWIO_INTLOCK(); \ 1234 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1235 HWIO_INTFREE();\ 1236 } while (0) 1237 1238 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1239 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1240 1241 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1242 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1243 1244 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1245 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1246 1247 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 1248 1249 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1250 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1251 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1252 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1253 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1254 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1255 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1256 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1257 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1258 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1259 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1260 do {\ 1261 HWIO_INTLOCK(); \ 1262 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1263 HWIO_INTFREE();\ 1264 } while (0) 1265 1266 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1267 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1268 1269 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 1270 1271 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1272 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1273 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1274 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 1275 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 1276 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 1277 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1278 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1279 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1280 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1281 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1282 do {\ 1283 HWIO_INTLOCK(); \ 1284 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 1285 HWIO_INTFREE();\ 1286 } while (0) 1287 1288 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1289 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1290 1291 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1292 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1293 1294 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1295 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1296 1297 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 1298 1299 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1300 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1301 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1302 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1303 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1304 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1305 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1306 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1307 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1308 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1309 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1310 do {\ 1311 HWIO_INTLOCK(); \ 1312 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1313 HWIO_INTFREE();\ 1314 } while (0) 1315 1316 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1317 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1318 1319 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 1320 1321 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1322 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1323 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1324 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1325 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1326 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1327 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1328 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1329 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1330 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1331 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1332 do {\ 1333 HWIO_INTLOCK(); \ 1334 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1335 HWIO_INTFREE();\ 1336 } while (0) 1337 1338 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1339 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1340 1341 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 1342 1343 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1344 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1345 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1346 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1347 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1348 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1349 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1350 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1351 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1352 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1353 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1354 do {\ 1355 HWIO_INTLOCK(); \ 1356 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1357 HWIO_INTFREE();\ 1358 } while (0) 1359 1360 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1361 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1362 1363 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1364 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1365 1366 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB //// 1367 1368 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1369 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1370 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1371 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0 1372 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ 1373 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK) 1374 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ 1375 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 1376 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ 1377 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) 1378 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1379 do {\ 1380 HWIO_INTLOCK(); \ 1381 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \ 1382 HWIO_INTFREE();\ 1383 } while (0) 1384 1385 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1386 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1387 1388 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB //// 1389 1390 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1391 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1392 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1393 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0 1394 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ 1395 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK) 1396 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ 1397 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 1398 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ 1399 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) 1400 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1401 do {\ 1402 HWIO_INTLOCK(); \ 1403 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \ 1404 HWIO_INTFREE();\ 1405 } while (0) 1406 1407 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1408 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1409 1410 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1411 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1412 1413 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA //// 1414 1415 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1416 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1417 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff 1418 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0 1419 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ 1420 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK) 1421 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ 1422 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) 1423 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \ 1424 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val) 1425 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ 1426 do {\ 1427 HWIO_INTLOCK(); \ 1428 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \ 1429 HWIO_INTFREE();\ 1430 } while (0) 1431 1432 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1433 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 1434 1435 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 1436 1437 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1438 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1439 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1440 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 1441 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 1442 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 1443 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1444 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1445 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1446 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1447 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1448 do {\ 1449 HWIO_INTLOCK(); \ 1450 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 1451 HWIO_INTFREE();\ 1452 } while (0) 1453 1454 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1455 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1456 1457 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 1458 1459 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1460 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1461 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 1462 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 1463 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 1464 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 1465 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 1466 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 1467 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 1468 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 1469 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 1470 do {\ 1471 HWIO_INTLOCK(); \ 1472 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 1473 HWIO_INTFREE();\ 1474 } while (0) 1475 1476 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1477 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1478 1479 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 1480 1481 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1482 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1483 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 1484 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 1485 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 1486 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 1487 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 1488 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 1489 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 1490 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 1491 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 1492 do {\ 1493 HWIO_INTLOCK(); \ 1494 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 1495 HWIO_INTFREE();\ 1496 } while (0) 1497 1498 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1499 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1500 1501 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1502 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1503 1504 //// Register REO_R0_REO_CMD_RING_ID //// 1505 1506 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x000000ec) 1507 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x000000ec) 1508 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 1509 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 1510 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 1511 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 1512 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 1513 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 1514 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 1515 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 1516 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 1517 do {\ 1518 HWIO_INTLOCK(); \ 1519 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 1520 HWIO_INTFREE();\ 1521 } while (0) 1522 1523 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1524 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 1525 1526 //// Register REO_R0_REO_CMD_RING_STATUS //// 1527 1528 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000000f0) 1529 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000000f0) 1530 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 1531 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 1532 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 1533 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 1534 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 1535 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 1536 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 1537 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 1538 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 1539 do {\ 1540 HWIO_INTLOCK(); \ 1541 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 1542 HWIO_INTFREE();\ 1543 } while (0) 1544 1545 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1546 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1547 1548 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1549 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1550 1551 //// Register REO_R0_REO_CMD_RING_MISC //// 1552 1553 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000000f4) 1554 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000000f4) 1555 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff 1556 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 1557 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 1558 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 1559 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 1560 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 1561 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 1562 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 1563 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 1564 do {\ 1565 HWIO_INTLOCK(); \ 1566 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 1567 HWIO_INTFREE();\ 1568 } while (0) 1569 1570 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1571 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 1572 1573 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1574 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1575 1576 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1577 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1578 1579 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1580 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1581 1582 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1583 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 1584 1585 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1586 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1587 1588 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1589 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1590 1591 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1592 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1593 1594 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1595 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 1596 1597 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1598 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1599 1600 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1601 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1602 1603 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 1604 1605 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1606 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1607 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 1608 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 1609 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 1610 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 1611 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 1612 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 1613 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 1614 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 1615 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1616 do {\ 1617 HWIO_INTLOCK(); \ 1618 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 1619 HWIO_INTFREE();\ 1620 } while (0) 1621 1622 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1623 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1624 1625 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 1626 1627 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1628 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1629 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 1630 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 1631 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 1632 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 1633 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 1634 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 1635 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 1636 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 1637 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1638 do {\ 1639 HWIO_INTLOCK(); \ 1640 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 1641 HWIO_INTFREE();\ 1642 } while (0) 1643 1644 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1645 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1646 1647 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 1648 1649 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1650 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1651 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1652 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1653 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1654 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1655 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1656 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1657 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1658 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1659 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1660 do {\ 1661 HWIO_INTLOCK(); \ 1662 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1663 HWIO_INTFREE();\ 1664 } while (0) 1665 1666 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1667 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1668 1669 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1670 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1671 1672 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1673 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1674 1675 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 1676 1677 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1678 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1679 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1680 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1681 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1682 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1683 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1684 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1685 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1686 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1687 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1688 do {\ 1689 HWIO_INTLOCK(); \ 1690 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1691 HWIO_INTFREE();\ 1692 } while (0) 1693 1694 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1695 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1696 1697 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 1698 1699 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1700 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1701 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1702 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 1703 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 1704 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 1705 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1706 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1707 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1708 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1709 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1710 do {\ 1711 HWIO_INTLOCK(); \ 1712 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 1713 HWIO_INTFREE();\ 1714 } while (0) 1715 1716 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1717 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1718 1719 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1720 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1721 1722 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1723 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1724 1725 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 1726 1727 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1728 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1729 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1730 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1731 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1732 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1733 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1734 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1735 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1736 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1737 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1738 do {\ 1739 HWIO_INTLOCK(); \ 1740 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1741 HWIO_INTFREE();\ 1742 } while (0) 1743 1744 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1745 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1746 1747 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 1748 1749 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1750 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1751 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1752 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1753 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1754 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1755 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1756 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1757 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1758 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1759 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1760 do {\ 1761 HWIO_INTLOCK(); \ 1762 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1763 HWIO_INTFREE();\ 1764 } while (0) 1765 1766 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1767 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1768 1769 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 1770 1771 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1772 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1773 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1774 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1775 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1776 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1777 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1778 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1779 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1780 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1781 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1782 do {\ 1783 HWIO_INTLOCK(); \ 1784 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1785 HWIO_INTFREE();\ 1786 } while (0) 1787 1788 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1789 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1790 1791 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1792 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1793 1794 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 1795 1796 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1797 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1798 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1799 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 1800 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 1801 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 1802 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 1803 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 1804 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 1805 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 1806 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1807 do {\ 1808 HWIO_INTLOCK(); \ 1809 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 1810 HWIO_INTFREE();\ 1811 } while (0) 1812 1813 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1814 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1815 1816 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 1817 1818 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1819 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1820 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1821 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 1822 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 1823 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 1824 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 1825 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 1826 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 1827 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 1828 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1829 do {\ 1830 HWIO_INTLOCK(); \ 1831 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 1832 HWIO_INTFREE();\ 1833 } while (0) 1834 1835 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1836 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1837 1838 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1839 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1840 1841 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 1842 1843 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1844 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1845 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 1846 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 1847 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 1848 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 1849 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 1850 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 1851 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 1852 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 1853 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 1854 do {\ 1855 HWIO_INTLOCK(); \ 1856 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 1857 HWIO_INTFREE();\ 1858 } while (0) 1859 1860 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1861 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 1862 1863 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 1864 1865 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1866 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1867 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1868 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 1869 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 1870 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 1871 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1872 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1873 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1874 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1875 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1876 do {\ 1877 HWIO_INTLOCK(); \ 1878 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 1879 HWIO_INTFREE();\ 1880 } while (0) 1881 1882 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1883 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1884 1885 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 1886 1887 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1888 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1889 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 1890 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 1891 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 1892 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 1893 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 1894 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 1895 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 1896 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 1897 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 1898 do {\ 1899 HWIO_INTLOCK(); \ 1900 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 1901 HWIO_INTFREE();\ 1902 } while (0) 1903 1904 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1905 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1906 1907 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 1908 1909 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1910 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1911 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 1912 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 1913 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 1914 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 1915 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 1916 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 1917 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 1918 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 1919 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 1920 do {\ 1921 HWIO_INTLOCK(); \ 1922 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 1923 HWIO_INTFREE();\ 1924 } while (0) 1925 1926 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1927 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1928 1929 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1930 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1931 1932 //// Register REO_R0_SW2REO_RING_ID //// 1933 1934 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x00000144) 1935 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x00000144) 1936 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 1937 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 1938 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 1939 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 1940 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 1941 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 1942 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 1943 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 1944 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 1945 do {\ 1946 HWIO_INTLOCK(); \ 1947 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 1948 HWIO_INTFREE();\ 1949 } while (0) 1950 1951 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1952 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 1953 1954 //// Register REO_R0_SW2REO_RING_STATUS //// 1955 1956 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x00000148) 1957 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x00000148) 1958 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 1959 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 1960 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 1961 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 1962 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 1963 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 1964 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 1965 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 1966 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 1967 do {\ 1968 HWIO_INTLOCK(); \ 1969 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 1970 HWIO_INTFREE();\ 1971 } while (0) 1972 1973 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1974 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1975 1976 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1977 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1978 1979 //// Register REO_R0_SW2REO_RING_MISC //// 1980 1981 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x0000014c) 1982 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x0000014c) 1983 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff 1984 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 1985 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 1986 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 1987 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 1988 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 1989 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 1990 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 1991 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 1992 do {\ 1993 HWIO_INTLOCK(); \ 1994 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 1995 HWIO_INTFREE();\ 1996 } while (0) 1997 1998 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1999 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe 2000 2001 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2002 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2003 2004 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2005 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2006 2007 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2008 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2009 2010 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2011 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 2012 2013 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2014 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2015 2016 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2017 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2018 2019 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2020 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2021 2022 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2023 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2024 2025 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2026 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2027 2028 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2029 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2030 2031 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2032 2033 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 2034 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 2035 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2036 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2037 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2038 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2039 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2040 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2041 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2042 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2043 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2044 do {\ 2045 HWIO_INTLOCK(); \ 2046 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2047 HWIO_INTFREE();\ 2048 } while (0) 2049 2050 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2051 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2052 2053 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2054 2055 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 2056 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 2057 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2058 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2059 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2060 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2061 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2062 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2063 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2064 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2065 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2066 do {\ 2067 HWIO_INTLOCK(); \ 2068 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2069 HWIO_INTFREE();\ 2070 } while (0) 2071 2072 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2073 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2074 2075 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2076 2077 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2078 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2079 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2080 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2081 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2082 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2083 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2084 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2085 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2086 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2087 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2088 do {\ 2089 HWIO_INTLOCK(); \ 2090 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2091 HWIO_INTFREE();\ 2092 } while (0) 2093 2094 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2095 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2096 2097 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2098 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2099 2100 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2101 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2102 2103 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2104 2105 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2106 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2107 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2108 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2109 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2110 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2111 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2112 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2113 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2114 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2115 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2116 do {\ 2117 HWIO_INTLOCK(); \ 2118 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2119 HWIO_INTFREE();\ 2120 } while (0) 2121 2122 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2123 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2124 2125 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2126 2127 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2128 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2129 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2130 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2131 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2132 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2133 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2134 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2135 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2136 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2137 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2138 do {\ 2139 HWIO_INTLOCK(); \ 2140 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2141 HWIO_INTFREE();\ 2142 } while (0) 2143 2144 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2145 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2146 2147 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2148 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2149 2150 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2151 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2152 2153 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2154 2155 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2156 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2157 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2158 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2159 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2160 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2161 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2162 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2163 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2164 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2165 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2166 do {\ 2167 HWIO_INTLOCK(); \ 2168 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2169 HWIO_INTFREE();\ 2170 } while (0) 2171 2172 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2173 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2174 2175 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2176 2177 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2178 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2179 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2180 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2181 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2182 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2183 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2184 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2185 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2186 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2187 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2188 do {\ 2189 HWIO_INTLOCK(); \ 2190 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2191 HWIO_INTFREE();\ 2192 } while (0) 2193 2194 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2195 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2196 2197 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2198 2199 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2200 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2201 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2202 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2203 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2204 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2205 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2206 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2207 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2208 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2209 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2210 do {\ 2211 HWIO_INTLOCK(); \ 2212 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2213 HWIO_INTFREE();\ 2214 } while (0) 2215 2216 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2217 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2218 2219 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2220 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2221 2222 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 2223 2224 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184) 2225 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184) 2226 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2227 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 2228 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 2229 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 2230 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 2231 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 2232 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 2233 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 2234 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2235 do {\ 2236 HWIO_INTLOCK(); \ 2237 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 2238 HWIO_INTFREE();\ 2239 } while (0) 2240 2241 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2242 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2243 2244 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 2245 2246 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188) 2247 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188) 2248 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2249 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 2250 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 2251 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 2252 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 2253 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 2254 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 2255 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 2256 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2257 do {\ 2258 HWIO_INTLOCK(); \ 2259 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 2260 HWIO_INTFREE();\ 2261 } while (0) 2262 2263 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2264 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2265 2266 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2267 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2268 2269 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 2270 2271 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000018c) 2272 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000018c) 2273 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 2274 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 2275 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 2276 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 2277 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 2278 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 2279 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 2280 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 2281 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 2282 do {\ 2283 HWIO_INTLOCK(); \ 2284 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 2285 HWIO_INTFREE();\ 2286 } while (0) 2287 2288 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2289 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 2290 2291 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 2292 2293 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2294 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2295 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2296 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 2297 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 2298 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 2299 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2300 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2301 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2302 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2303 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2304 do {\ 2305 HWIO_INTLOCK(); \ 2306 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 2307 HWIO_INTFREE();\ 2308 } while (0) 2309 2310 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2311 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2312 2313 //// Register REO_R0_SW2REO1_RING_BASE_LSB //// 2314 2315 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2316 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2317 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff 2318 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0 2319 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ 2320 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK) 2321 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ 2322 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) 2323 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \ 2324 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val) 2325 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 2326 do {\ 2327 HWIO_INTLOCK(); \ 2328 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \ 2329 HWIO_INTFREE();\ 2330 } while (0) 2331 2332 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2333 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2334 2335 //// Register REO_R0_SW2REO1_RING_BASE_MSB //// 2336 2337 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2338 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2339 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff 2340 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0 2341 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ 2342 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK) 2343 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ 2344 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) 2345 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \ 2346 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val) 2347 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 2348 do {\ 2349 HWIO_INTLOCK(); \ 2350 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \ 2351 HWIO_INTFREE();\ 2352 } while (0) 2353 2354 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2355 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2356 2357 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2358 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2359 2360 //// Register REO_R0_SW2REO1_RING_ID //// 2361 2362 #define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000019c) 2363 #define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000019c) 2364 #define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff 2365 #define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0 2366 #define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ 2367 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK) 2368 #define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ 2369 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) 2370 #define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \ 2371 out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val) 2372 #define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ 2373 do {\ 2374 HWIO_INTLOCK(); \ 2375 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \ 2376 HWIO_INTFREE();\ 2377 } while (0) 2378 2379 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2380 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 2381 2382 //// Register REO_R0_SW2REO1_RING_STATUS //// 2383 2384 #define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x000001a0) 2385 #define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x000001a0) 2386 #define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff 2387 #define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0 2388 #define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ 2389 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK) 2390 #define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ 2391 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) 2392 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \ 2393 out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val) 2394 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ 2395 do {\ 2396 HWIO_INTLOCK(); \ 2397 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \ 2398 HWIO_INTFREE();\ 2399 } while (0) 2400 2401 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2402 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2403 2404 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2405 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2406 2407 //// Register REO_R0_SW2REO1_RING_MISC //// 2408 2409 #define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x000001a4) 2410 #define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x000001a4) 2411 #define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff 2412 #define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0 2413 #define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ 2414 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK) 2415 #define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ 2416 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) 2417 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \ 2418 out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val) 2419 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ 2420 do {\ 2421 HWIO_INTLOCK(); \ 2422 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \ 2423 HWIO_INTFREE();\ 2424 } while (0) 2425 2426 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2427 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2428 2429 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2430 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2431 2432 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2433 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2434 2435 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2436 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2437 2438 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2439 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2440 2441 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2442 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2443 2444 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2445 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2446 2447 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2448 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2449 2450 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2451 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 2452 2453 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2454 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2455 2456 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2457 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2458 2459 //// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB //// 2460 2461 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2462 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2463 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2464 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0 2465 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ 2466 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK) 2467 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 2468 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 2469 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 2470 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 2471 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2472 do {\ 2473 HWIO_INTLOCK(); \ 2474 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \ 2475 HWIO_INTFREE();\ 2476 } while (0) 2477 2478 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2479 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2480 2481 //// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB //// 2482 2483 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2484 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2485 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2486 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0 2487 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ 2488 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK) 2489 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 2490 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 2491 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 2492 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 2493 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2494 do {\ 2495 HWIO_INTLOCK(); \ 2496 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \ 2497 HWIO_INTFREE();\ 2498 } while (0) 2499 2500 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2501 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2502 2503 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 2504 2505 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2506 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2507 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2508 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2509 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2510 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2511 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2512 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2513 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2514 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2515 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2516 do {\ 2517 HWIO_INTLOCK(); \ 2518 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2519 HWIO_INTFREE();\ 2520 } while (0) 2521 2522 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2523 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2524 2525 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2526 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2527 2528 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2529 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2530 2531 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 2532 2533 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2534 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2535 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2536 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2537 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2538 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2539 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2540 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2541 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2542 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2543 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2544 do {\ 2545 HWIO_INTLOCK(); \ 2546 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2547 HWIO_INTFREE();\ 2548 } while (0) 2549 2550 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2551 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2552 2553 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS //// 2554 2555 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2556 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2557 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2558 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 2559 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 2560 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK) 2561 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2562 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2563 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2564 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2565 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2566 do {\ 2567 HWIO_INTLOCK(); \ 2568 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 2569 HWIO_INTFREE();\ 2570 } while (0) 2571 2572 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2573 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2574 2575 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2576 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2577 2578 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2579 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2580 2581 //// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER //// 2582 2583 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2584 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2585 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2586 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2587 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2588 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2589 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2590 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2591 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2592 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2593 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2594 do {\ 2595 HWIO_INTLOCK(); \ 2596 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2597 HWIO_INTFREE();\ 2598 } while (0) 2599 2600 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2601 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2602 2603 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER //// 2604 2605 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2606 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2607 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2608 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2609 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2610 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2611 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2612 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2613 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2614 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2615 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2616 do {\ 2617 HWIO_INTLOCK(); \ 2618 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2619 HWIO_INTFREE();\ 2620 } while (0) 2621 2622 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2623 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2624 2625 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS //// 2626 2627 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2628 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2629 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2630 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2631 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2632 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2633 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2634 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2635 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2636 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2637 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2638 do {\ 2639 HWIO_INTLOCK(); \ 2640 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2641 HWIO_INTFREE();\ 2642 } while (0) 2643 2644 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2645 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2646 2647 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2648 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2649 2650 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB //// 2651 2652 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2653 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2654 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2655 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0 2656 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ 2657 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK) 2658 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 2659 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 2660 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 2661 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 2662 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2663 do {\ 2664 HWIO_INTLOCK(); \ 2665 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 2666 HWIO_INTFREE();\ 2667 } while (0) 2668 2669 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2670 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2671 2672 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB //// 2673 2674 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2675 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2676 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2677 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0 2678 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ 2679 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK) 2680 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 2681 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 2682 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 2683 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 2684 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2685 do {\ 2686 HWIO_INTLOCK(); \ 2687 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 2688 HWIO_INTFREE();\ 2689 } while (0) 2690 2691 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2692 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2693 2694 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2695 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2696 2697 //// Register REO_R0_SW2REO1_RING_MSI1_DATA //// 2698 2699 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2700 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2701 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff 2702 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0 2703 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ 2704 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK) 2705 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ 2706 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) 2707 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \ 2708 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val) 2709 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 2710 do {\ 2711 HWIO_INTLOCK(); \ 2712 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \ 2713 HWIO_INTFREE();\ 2714 } while (0) 2715 2716 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2717 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 2718 2719 //// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET //// 2720 2721 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2722 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2723 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2724 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 2725 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 2726 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK) 2727 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2728 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2729 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2730 out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2731 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2732 do {\ 2733 HWIO_INTLOCK(); \ 2734 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 2735 HWIO_INTFREE();\ 2736 } while (0) 2737 2738 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2739 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2740 2741 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 2742 2743 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2744 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2745 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 2746 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 2747 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 2748 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 2749 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 2750 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 2751 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 2752 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 2753 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 2754 do {\ 2755 HWIO_INTLOCK(); \ 2756 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 2757 HWIO_INTFREE();\ 2758 } while (0) 2759 2760 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2761 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2762 2763 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 2764 2765 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2766 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2767 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff 2768 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 2769 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 2770 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 2771 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 2772 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 2773 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 2774 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 2775 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 2776 do {\ 2777 HWIO_INTLOCK(); \ 2778 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 2779 HWIO_INTFREE();\ 2780 } while (0) 2781 2782 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2783 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2784 2785 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2786 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2787 2788 //// Register REO_R0_REO2SW1_RING_ID //// 2789 2790 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000001f4) 2791 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000001f4) 2792 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 2793 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 2794 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 2795 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 2796 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 2797 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 2798 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 2799 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 2800 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 2801 do {\ 2802 HWIO_INTLOCK(); \ 2803 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 2804 HWIO_INTFREE();\ 2805 } while (0) 2806 2807 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 2808 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 2809 2810 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2811 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 2812 2813 //// Register REO_R0_REO2SW1_RING_STATUS //// 2814 2815 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000001f8) 2816 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000001f8) 2817 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 2818 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 2819 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 2820 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 2821 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 2822 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 2823 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 2824 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 2825 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 2826 do {\ 2827 HWIO_INTLOCK(); \ 2828 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 2829 HWIO_INTFREE();\ 2830 } while (0) 2831 2832 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2833 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2834 2835 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2836 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2837 2838 //// Register REO_R0_REO2SW1_RING_MISC //// 2839 2840 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000001fc) 2841 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000001fc) 2842 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff 2843 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 2844 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 2845 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 2846 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 2847 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 2848 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 2849 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 2850 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 2851 do {\ 2852 HWIO_INTLOCK(); \ 2853 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 2854 HWIO_INTFREE();\ 2855 } while (0) 2856 2857 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 2858 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 2859 2860 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2861 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2862 2863 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2864 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2865 2866 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2867 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2868 2869 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2870 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2871 2872 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2873 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2874 2875 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2876 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2877 2878 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2879 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2880 2881 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2882 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2883 2884 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2885 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 2886 2887 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2888 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2889 2890 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2891 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2892 2893 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 2894 2895 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000200) 2896 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000200) 2897 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 2898 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 2899 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 2900 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 2901 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 2902 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 2903 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 2904 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 2905 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 2906 do {\ 2907 HWIO_INTLOCK(); \ 2908 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 2909 HWIO_INTFREE();\ 2910 } while (0) 2911 2912 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 2913 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 2914 2915 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 2916 2917 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000204) 2918 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000204) 2919 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 2920 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 2921 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 2922 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 2923 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 2924 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 2925 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 2926 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 2927 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 2928 do {\ 2929 HWIO_INTLOCK(); \ 2930 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 2931 HWIO_INTFREE();\ 2932 } while (0) 2933 2934 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 2935 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 2936 2937 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 2938 2939 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000210) 2940 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000210) 2941 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 2942 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 2943 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 2944 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 2945 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 2946 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 2947 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 2948 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 2949 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 2950 do {\ 2951 HWIO_INTLOCK(); \ 2952 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 2953 HWIO_INTFREE();\ 2954 } while (0) 2955 2956 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2957 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2958 2959 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 2960 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 2961 2962 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2963 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2964 2965 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 2966 2967 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000214) 2968 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000214) 2969 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 2970 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 2971 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 2972 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 2973 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 2974 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 2975 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 2976 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 2977 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 2978 do {\ 2979 HWIO_INTLOCK(); \ 2980 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 2981 HWIO_INTFREE();\ 2982 } while (0) 2983 2984 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2985 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2986 2987 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 2988 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 2989 2990 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2991 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2992 2993 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 2994 2995 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000218) 2996 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000218) 2997 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 2998 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 2999 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3000 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3001 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3002 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3003 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3004 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3005 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3006 do {\ 3007 HWIO_INTLOCK(); \ 3008 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3009 HWIO_INTFREE();\ 3010 } while (0) 3011 3012 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3013 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3014 3015 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3016 3017 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 3018 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 3019 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3020 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3021 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3022 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3023 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3024 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3025 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3026 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3027 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3028 do {\ 3029 HWIO_INTLOCK(); \ 3030 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3031 HWIO_INTFREE();\ 3032 } while (0) 3033 3034 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3035 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3036 3037 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3038 3039 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 3040 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 3041 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3042 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3043 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3044 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3045 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3046 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3047 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3048 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3049 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3050 do {\ 3051 HWIO_INTLOCK(); \ 3052 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3053 HWIO_INTFREE();\ 3054 } while (0) 3055 3056 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3057 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3058 3059 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3060 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3061 3062 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3063 3064 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 3065 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 3066 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3067 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3068 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3069 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3070 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3071 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3072 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3073 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3074 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3075 do {\ 3076 HWIO_INTLOCK(); \ 3077 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3078 HWIO_INTFREE();\ 3079 } while (0) 3080 3081 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3082 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3083 3084 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3085 3086 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 3087 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 3088 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3089 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3090 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3091 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3092 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3093 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3094 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3095 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3096 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3097 do {\ 3098 HWIO_INTLOCK(); \ 3099 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3100 HWIO_INTFREE();\ 3101 } while (0) 3102 3103 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3104 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3105 3106 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3107 3108 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3109 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3110 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3111 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3112 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3113 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3114 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3115 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3116 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3117 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3118 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3119 do {\ 3120 HWIO_INTLOCK(); \ 3121 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3122 HWIO_INTFREE();\ 3123 } while (0) 3124 3125 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3126 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3127 3128 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3129 3130 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3131 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3132 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff 3133 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3134 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3135 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3136 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3137 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3138 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3139 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3140 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3141 do {\ 3142 HWIO_INTLOCK(); \ 3143 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3144 HWIO_INTFREE();\ 3145 } while (0) 3146 3147 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3148 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3149 3150 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3151 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3152 3153 //// Register REO_R0_REO2SW2_RING_ID //// 3154 3155 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x0000024c) 3156 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x0000024c) 3157 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3158 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3159 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3160 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3161 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3162 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3163 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3164 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3165 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3166 do {\ 3167 HWIO_INTLOCK(); \ 3168 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3169 HWIO_INTFREE();\ 3170 } while (0) 3171 3172 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3173 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3174 3175 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3176 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3177 3178 //// Register REO_R0_REO2SW2_RING_STATUS //// 3179 3180 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000250) 3181 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000250) 3182 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3183 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3184 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3185 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3186 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3187 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3188 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3189 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3190 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3191 do {\ 3192 HWIO_INTLOCK(); \ 3193 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3194 HWIO_INTFREE();\ 3195 } while (0) 3196 3197 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3198 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3199 3200 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3201 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3202 3203 //// Register REO_R0_REO2SW2_RING_MISC //// 3204 3205 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000254) 3206 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000254) 3207 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff 3208 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 3209 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 3210 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 3211 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 3212 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 3213 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 3214 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 3215 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 3216 do {\ 3217 HWIO_INTLOCK(); \ 3218 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 3219 HWIO_INTFREE();\ 3220 } while (0) 3221 3222 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3223 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 3224 3225 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3226 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3227 3228 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3229 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3230 3231 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3232 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3233 3234 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3235 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3236 3237 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3238 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3239 3240 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3241 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3242 3243 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3244 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3245 3246 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3247 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3248 3249 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3250 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 3251 3252 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3253 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3254 3255 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3256 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3257 3258 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 3259 3260 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) 3261 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) 3262 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3263 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 3264 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 3265 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 3266 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 3267 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 3268 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 3269 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 3270 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3271 do {\ 3272 HWIO_INTLOCK(); \ 3273 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 3274 HWIO_INTFREE();\ 3275 } while (0) 3276 3277 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3278 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3279 3280 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 3281 3282 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) 3283 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) 3284 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3285 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 3286 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 3287 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 3288 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 3289 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 3290 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 3291 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 3292 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3293 do {\ 3294 HWIO_INTLOCK(); \ 3295 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 3296 HWIO_INTFREE();\ 3297 } while (0) 3298 3299 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3300 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3301 3302 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 3303 3304 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) 3305 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) 3306 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3307 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 3308 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 3309 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 3310 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3311 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3312 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3313 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3314 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3315 do {\ 3316 HWIO_INTLOCK(); \ 3317 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3318 HWIO_INTFREE();\ 3319 } while (0) 3320 3321 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3322 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3323 3324 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3325 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3326 3327 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3328 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3329 3330 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 3331 3332 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) 3333 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) 3334 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3335 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 3336 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 3337 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 3338 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3339 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3340 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3341 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3342 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3343 do {\ 3344 HWIO_INTLOCK(); \ 3345 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3346 HWIO_INTFREE();\ 3347 } while (0) 3348 3349 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3350 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3351 3352 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3353 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3354 3355 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3356 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3357 3358 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 3359 3360 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) 3361 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) 3362 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3363 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 3364 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3365 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 3366 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3367 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3368 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3369 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3370 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3371 do {\ 3372 HWIO_INTLOCK(); \ 3373 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3374 HWIO_INTFREE();\ 3375 } while (0) 3376 3377 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3378 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3379 3380 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 3381 3382 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3383 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3384 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3385 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 3386 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 3387 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 3388 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 3389 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 3390 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 3391 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 3392 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3393 do {\ 3394 HWIO_INTLOCK(); \ 3395 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 3396 HWIO_INTFREE();\ 3397 } while (0) 3398 3399 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3400 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3401 3402 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 3403 3404 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3405 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3406 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3407 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 3408 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 3409 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 3410 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 3411 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 3412 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 3413 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 3414 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3415 do {\ 3416 HWIO_INTLOCK(); \ 3417 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 3418 HWIO_INTFREE();\ 3419 } while (0) 3420 3421 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3422 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3423 3424 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3425 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3426 3427 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 3428 3429 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3430 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3431 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 3432 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 3433 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 3434 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 3435 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 3436 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 3437 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 3438 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 3439 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 3440 do {\ 3441 HWIO_INTLOCK(); \ 3442 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 3443 HWIO_INTFREE();\ 3444 } while (0) 3445 3446 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3447 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 3448 3449 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 3450 3451 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3452 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3453 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3454 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 3455 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 3456 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 3457 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3458 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3459 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3460 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3461 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3462 do {\ 3463 HWIO_INTLOCK(); \ 3464 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 3465 HWIO_INTFREE();\ 3466 } while (0) 3467 3468 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3469 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3470 3471 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 3472 3473 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3474 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3475 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 3476 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 3477 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 3478 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 3479 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 3480 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 3481 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 3482 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 3483 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 3484 do {\ 3485 HWIO_INTLOCK(); \ 3486 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 3487 HWIO_INTFREE();\ 3488 } while (0) 3489 3490 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3491 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3492 3493 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 3494 3495 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3496 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3497 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff 3498 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 3499 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 3500 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 3501 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 3502 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 3503 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 3504 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 3505 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 3506 do {\ 3507 HWIO_INTLOCK(); \ 3508 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 3509 HWIO_INTFREE();\ 3510 } while (0) 3511 3512 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3513 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3514 3515 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3516 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3517 3518 //// Register REO_R0_REO2SW3_RING_ID //// 3519 3520 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002a4) 3521 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002a4) 3522 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 3523 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 3524 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 3525 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 3526 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 3527 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 3528 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 3529 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 3530 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 3531 do {\ 3532 HWIO_INTLOCK(); \ 3533 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 3534 HWIO_INTFREE();\ 3535 } while (0) 3536 3537 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 3538 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 3539 3540 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3541 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 3542 3543 //// Register REO_R0_REO2SW3_RING_STATUS //// 3544 3545 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x000002a8) 3546 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x000002a8) 3547 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 3548 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 3549 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 3550 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 3551 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 3552 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 3553 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 3554 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 3555 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 3556 do {\ 3557 HWIO_INTLOCK(); \ 3558 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 3559 HWIO_INTFREE();\ 3560 } while (0) 3561 3562 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3563 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3564 3565 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3566 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3567 3568 //// Register REO_R0_REO2SW3_RING_MISC //// 3569 3570 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x000002ac) 3571 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x000002ac) 3572 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff 3573 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 3574 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 3575 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 3576 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 3577 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 3578 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 3579 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 3580 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 3581 do {\ 3582 HWIO_INTLOCK(); \ 3583 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 3584 HWIO_INTFREE();\ 3585 } while (0) 3586 3587 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3588 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 3589 3590 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3591 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe 3592 3593 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3594 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3595 3596 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3597 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3598 3599 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3600 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3601 3602 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3603 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 3604 3605 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3606 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3607 3608 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3609 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3610 3611 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3612 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3613 3614 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3615 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 3616 3617 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3618 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3619 3620 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3621 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3622 3623 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 3624 3625 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3626 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3627 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 3628 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 3629 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 3630 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 3631 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 3632 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 3633 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 3634 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 3635 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3636 do {\ 3637 HWIO_INTLOCK(); \ 3638 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 3639 HWIO_INTFREE();\ 3640 } while (0) 3641 3642 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3643 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3644 3645 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 3646 3647 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3648 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3649 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 3650 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 3651 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 3652 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 3653 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 3654 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 3655 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 3656 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 3657 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3658 do {\ 3659 HWIO_INTLOCK(); \ 3660 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 3661 HWIO_INTFREE();\ 3662 } while (0) 3663 3664 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3665 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3666 3667 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 3668 3669 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3670 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3671 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3672 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 3673 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 3674 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 3675 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3676 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3677 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3678 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3679 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3680 do {\ 3681 HWIO_INTLOCK(); \ 3682 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 3683 HWIO_INTFREE();\ 3684 } while (0) 3685 3686 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3687 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3688 3689 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3690 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3691 3692 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3693 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3694 3695 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 3696 3697 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3698 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3699 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3700 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 3701 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 3702 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 3703 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3704 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3705 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3706 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3707 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3708 do {\ 3709 HWIO_INTLOCK(); \ 3710 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 3711 HWIO_INTFREE();\ 3712 } while (0) 3713 3714 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3715 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3716 3717 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3718 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3719 3720 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3721 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3722 3723 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 3724 3725 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3726 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3727 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3728 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 3729 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3730 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 3731 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3732 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3733 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3734 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3735 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3736 do {\ 3737 HWIO_INTLOCK(); \ 3738 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3739 HWIO_INTFREE();\ 3740 } while (0) 3741 3742 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3743 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3744 3745 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 3746 3747 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3748 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3749 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3750 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 3751 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 3752 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 3753 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 3754 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 3755 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 3756 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 3757 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3758 do {\ 3759 HWIO_INTLOCK(); \ 3760 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 3761 HWIO_INTFREE();\ 3762 } while (0) 3763 3764 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3765 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3766 3767 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 3768 3769 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3770 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3771 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3772 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 3773 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 3774 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 3775 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 3776 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 3777 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 3778 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 3779 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3780 do {\ 3781 HWIO_INTLOCK(); \ 3782 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 3783 HWIO_INTFREE();\ 3784 } while (0) 3785 3786 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3787 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3788 3789 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3790 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3791 3792 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 3793 3794 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3795 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3796 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 3797 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 3798 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 3799 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 3800 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 3801 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 3802 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 3803 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 3804 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 3805 do {\ 3806 HWIO_INTLOCK(); \ 3807 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 3808 HWIO_INTFREE();\ 3809 } while (0) 3810 3811 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3812 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 3813 3814 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 3815 3816 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3817 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3818 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3819 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 3820 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 3821 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 3822 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3823 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3824 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3825 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3826 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3827 do {\ 3828 HWIO_INTLOCK(); \ 3829 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 3830 HWIO_INTFREE();\ 3831 } while (0) 3832 3833 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3834 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3835 3836 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 3837 3838 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3839 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3840 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 3841 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 3842 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 3843 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 3844 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 3845 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 3846 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 3847 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 3848 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 3849 do {\ 3850 HWIO_INTLOCK(); \ 3851 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 3852 HWIO_INTFREE();\ 3853 } while (0) 3854 3855 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3856 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3857 3858 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 3859 3860 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3861 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3862 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff 3863 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 3864 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 3865 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 3866 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 3867 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 3868 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 3869 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 3870 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 3871 do {\ 3872 HWIO_INTLOCK(); \ 3873 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 3874 HWIO_INTFREE();\ 3875 } while (0) 3876 3877 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3878 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3879 3880 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3881 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3882 3883 //// Register REO_R0_REO2SW4_RING_ID //// 3884 3885 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000002fc) 3886 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000002fc) 3887 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 3888 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 3889 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 3890 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 3891 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 3892 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 3893 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 3894 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 3895 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 3896 do {\ 3897 HWIO_INTLOCK(); \ 3898 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 3899 HWIO_INTFREE();\ 3900 } while (0) 3901 3902 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 3903 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 3904 3905 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3906 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 3907 3908 //// Register REO_R0_REO2SW4_RING_STATUS //// 3909 3910 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000300) 3911 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000300) 3912 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 3913 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 3914 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 3915 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 3916 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 3917 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 3918 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 3919 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 3920 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 3921 do {\ 3922 HWIO_INTLOCK(); \ 3923 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 3924 HWIO_INTFREE();\ 3925 } while (0) 3926 3927 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3928 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3929 3930 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3931 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3932 3933 //// Register REO_R0_REO2SW4_RING_MISC //// 3934 3935 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x00000304) 3936 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x00000304) 3937 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff 3938 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 3939 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 3940 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 3941 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 3942 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 3943 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 3944 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 3945 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 3946 do {\ 3947 HWIO_INTLOCK(); \ 3948 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 3949 HWIO_INTFREE();\ 3950 } while (0) 3951 3952 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3953 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 3954 3955 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3956 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe 3957 3958 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3959 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3960 3961 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3962 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3963 3964 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3965 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3966 3967 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3968 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 3969 3970 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3971 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3972 3973 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3974 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3975 3976 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3977 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3978 3979 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3980 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 3981 3982 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3983 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3984 3985 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3986 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3987 3988 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 3989 3990 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 3991 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 3992 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 3993 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 3994 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 3995 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 3996 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 3997 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 3998 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 3999 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4000 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4001 do {\ 4002 HWIO_INTLOCK(); \ 4003 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4004 HWIO_INTFREE();\ 4005 } while (0) 4006 4007 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4008 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4009 4010 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4011 4012 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 4013 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 4014 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4015 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4016 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4017 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4018 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4019 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4020 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4021 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4022 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4023 do {\ 4024 HWIO_INTLOCK(); \ 4025 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4026 HWIO_INTFREE();\ 4027 } while (0) 4028 4029 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4030 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4031 4032 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4033 4034 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 4035 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 4036 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4037 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4038 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4039 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4040 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4041 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4042 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4043 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4044 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4045 do {\ 4046 HWIO_INTLOCK(); \ 4047 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4048 HWIO_INTFREE();\ 4049 } while (0) 4050 4051 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4052 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4053 4054 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4055 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4056 4057 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4058 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4059 4060 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4061 4062 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 4063 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 4064 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4065 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4066 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4067 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4068 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4069 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4070 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4071 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4072 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4073 do {\ 4074 HWIO_INTLOCK(); \ 4075 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4076 HWIO_INTFREE();\ 4077 } while (0) 4078 4079 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4080 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4081 4082 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4083 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4084 4085 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4086 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4087 4088 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4089 4090 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 4091 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 4092 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4093 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4094 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4095 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4096 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4097 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4098 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4099 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4100 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4101 do {\ 4102 HWIO_INTLOCK(); \ 4103 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4104 HWIO_INTFREE();\ 4105 } while (0) 4106 4107 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4108 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4109 4110 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4111 4112 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 4113 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 4114 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4115 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4116 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4117 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4118 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4119 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4120 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4121 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4122 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4123 do {\ 4124 HWIO_INTLOCK(); \ 4125 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4126 HWIO_INTFREE();\ 4127 } while (0) 4128 4129 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4130 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4131 4132 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4133 4134 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 4135 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 4136 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4137 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4138 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4139 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4140 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4141 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4142 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4143 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4144 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4145 do {\ 4146 HWIO_INTLOCK(); \ 4147 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4148 HWIO_INTFREE();\ 4149 } while (0) 4150 4151 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4152 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4153 4154 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4155 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4156 4157 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4158 4159 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4160 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4161 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4162 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4163 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4164 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4165 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4166 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4167 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4168 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4169 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4170 do {\ 4171 HWIO_INTLOCK(); \ 4172 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4173 HWIO_INTFREE();\ 4174 } while (0) 4175 4176 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4177 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4178 4179 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4180 4181 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4182 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4183 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4184 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4185 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4186 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4187 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4188 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4189 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4190 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4191 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4192 do {\ 4193 HWIO_INTLOCK(); \ 4194 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4195 HWIO_INTFREE();\ 4196 } while (0) 4197 4198 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4199 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4200 4201 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4202 4203 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4204 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4205 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4206 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4207 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 4208 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 4209 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 4210 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 4211 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 4212 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 4213 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 4214 do {\ 4215 HWIO_INTLOCK(); \ 4216 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 4217 HWIO_INTFREE();\ 4218 } while (0) 4219 4220 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4221 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4222 4223 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 4224 4225 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400) 4226 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400) 4227 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff 4228 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 4229 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 4230 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 4231 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 4232 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 4233 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 4234 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 4235 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 4236 do {\ 4237 HWIO_INTLOCK(); \ 4238 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 4239 HWIO_INTFREE();\ 4240 } while (0) 4241 4242 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4243 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4244 4245 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4246 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4247 4248 //// Register REO_R0_REO2TCL_RING_ID //// 4249 4250 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404) 4251 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404) 4252 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 4253 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 4254 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 4255 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 4256 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 4257 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 4258 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 4259 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 4260 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 4261 do {\ 4262 HWIO_INTLOCK(); \ 4263 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 4264 HWIO_INTFREE();\ 4265 } while (0) 4266 4267 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 4268 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 4269 4270 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4271 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 4272 4273 //// Register REO_R0_REO2TCL_RING_STATUS //// 4274 4275 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408) 4276 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408) 4277 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 4278 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 4279 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 4280 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 4281 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 4282 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 4283 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 4284 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 4285 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 4286 do {\ 4287 HWIO_INTLOCK(); \ 4288 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 4289 HWIO_INTFREE();\ 4290 } while (0) 4291 4292 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4293 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4294 4295 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4296 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4297 4298 //// Register REO_R0_REO2TCL_RING_MISC //// 4299 4300 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c) 4301 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c) 4302 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff 4303 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 4304 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 4305 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 4306 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 4307 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 4308 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 4309 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 4310 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 4311 do {\ 4312 HWIO_INTLOCK(); \ 4313 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 4314 HWIO_INTFREE();\ 4315 } while (0) 4316 4317 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4318 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 4319 4320 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4321 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe 4322 4323 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4324 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4325 4326 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4327 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4328 4329 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4330 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4331 4332 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4333 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 4334 4335 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4336 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4337 4338 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4339 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4340 4341 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4342 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4343 4344 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4345 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 4346 4347 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4348 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4349 4350 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4351 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4352 4353 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 4354 4355 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 4356 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 4357 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 4358 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 4359 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 4360 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 4361 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 4362 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 4363 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 4364 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 4365 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4366 do {\ 4367 HWIO_INTLOCK(); \ 4368 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 4369 HWIO_INTFREE();\ 4370 } while (0) 4371 4372 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4373 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4374 4375 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 4376 4377 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 4378 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 4379 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 4380 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 4381 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 4382 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 4383 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 4384 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 4385 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 4386 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 4387 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4388 do {\ 4389 HWIO_INTLOCK(); \ 4390 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 4391 HWIO_INTFREE();\ 4392 } while (0) 4393 4394 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4395 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4396 4397 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 4398 4399 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 4400 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 4401 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4402 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 4403 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 4404 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 4405 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4406 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4407 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4408 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4409 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4410 do {\ 4411 HWIO_INTLOCK(); \ 4412 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 4413 HWIO_INTFREE();\ 4414 } while (0) 4415 4416 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4417 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4418 4419 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4420 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4421 4422 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4423 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4424 4425 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 4426 4427 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 4428 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 4429 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4430 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 4431 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 4432 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 4433 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4434 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4435 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4436 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4437 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4438 do {\ 4439 HWIO_INTLOCK(); \ 4440 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 4441 HWIO_INTFREE();\ 4442 } while (0) 4443 4444 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4445 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4446 4447 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4448 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4449 4450 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4451 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4452 4453 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 4454 4455 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 4456 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 4457 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4458 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 4459 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4460 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 4461 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4462 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4463 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4464 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4465 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4466 do {\ 4467 HWIO_INTLOCK(); \ 4468 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4469 HWIO_INTFREE();\ 4470 } while (0) 4471 4472 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4473 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4474 4475 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 4476 4477 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 4478 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 4479 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4480 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 4481 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 4482 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 4483 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 4484 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 4485 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 4486 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 4487 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4488 do {\ 4489 HWIO_INTLOCK(); \ 4490 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 4491 HWIO_INTFREE();\ 4492 } while (0) 4493 4494 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4495 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4496 4497 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 4498 4499 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 4500 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 4501 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4502 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 4503 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 4504 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 4505 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 4506 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 4507 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 4508 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 4509 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4510 do {\ 4511 HWIO_INTLOCK(); \ 4512 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 4513 HWIO_INTFREE();\ 4514 } while (0) 4515 4516 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4517 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4518 4519 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4520 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4521 4522 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 4523 4524 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 4525 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 4526 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 4527 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 4528 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 4529 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 4530 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 4531 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 4532 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 4533 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 4534 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 4535 do {\ 4536 HWIO_INTLOCK(); \ 4537 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 4538 HWIO_INTFREE();\ 4539 } while (0) 4540 4541 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4542 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 4543 4544 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 4545 4546 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 4547 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 4548 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4549 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 4550 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 4551 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 4552 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4553 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4554 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4555 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4556 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4557 do {\ 4558 HWIO_INTLOCK(); \ 4559 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 4560 HWIO_INTFREE();\ 4561 } while (0) 4562 4563 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4564 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4565 4566 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 4567 4568 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454) 4569 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454) 4570 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 4571 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 4572 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 4573 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 4574 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 4575 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 4576 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 4577 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 4578 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4579 do {\ 4580 HWIO_INTLOCK(); \ 4581 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 4582 HWIO_INTFREE();\ 4583 } while (0) 4584 4585 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4586 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4587 4588 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 4589 4590 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458) 4591 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458) 4592 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff 4593 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 4594 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 4595 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 4596 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 4597 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 4598 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 4599 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 4600 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4601 do {\ 4602 HWIO_INTLOCK(); \ 4603 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 4604 HWIO_INTFREE();\ 4605 } while (0) 4606 4607 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4608 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4609 4610 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4611 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4612 4613 //// Register REO_R0_REO2FW_RING_ID //// 4614 4615 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c) 4616 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c) 4617 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 4618 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 4619 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 4620 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 4621 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 4622 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 4623 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 4624 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 4625 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 4626 do {\ 4627 HWIO_INTLOCK(); \ 4628 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 4629 HWIO_INTFREE();\ 4630 } while (0) 4631 4632 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4633 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 4634 4635 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4636 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4637 4638 //// Register REO_R0_REO2FW_RING_STATUS //// 4639 4640 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460) 4641 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460) 4642 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 4643 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 4644 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 4645 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 4646 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 4647 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 4648 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 4649 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 4650 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 4651 do {\ 4652 HWIO_INTLOCK(); \ 4653 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 4654 HWIO_INTFREE();\ 4655 } while (0) 4656 4657 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4658 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4659 4660 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4661 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4662 4663 //// Register REO_R0_REO2FW_RING_MISC //// 4664 4665 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464) 4666 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464) 4667 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff 4668 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 4669 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 4670 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 4671 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 4672 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 4673 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 4674 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 4675 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 4676 do {\ 4677 HWIO_INTLOCK(); \ 4678 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 4679 HWIO_INTFREE();\ 4680 } while (0) 4681 4682 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4683 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4684 4685 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4686 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4687 4688 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4689 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4690 4691 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4692 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4693 4694 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4695 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4696 4697 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4698 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4699 4700 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4701 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4702 4703 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4704 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4705 4706 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4707 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4708 4709 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4710 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4711 4712 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4713 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4714 4715 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4716 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4717 4718 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 4719 4720 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 4721 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 4722 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4723 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 4724 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 4725 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 4726 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4727 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4728 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4729 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4730 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4731 do {\ 4732 HWIO_INTLOCK(); \ 4733 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 4734 HWIO_INTFREE();\ 4735 } while (0) 4736 4737 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4738 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4739 4740 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 4741 4742 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 4743 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 4744 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4745 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 4746 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 4747 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 4748 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4749 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4750 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4751 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4752 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4753 do {\ 4754 HWIO_INTLOCK(); \ 4755 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 4756 HWIO_INTFREE();\ 4757 } while (0) 4758 4759 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4760 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4761 4762 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 4763 4764 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 4765 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 4766 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4767 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4768 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4769 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 4770 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4771 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4772 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4773 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4774 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4775 do {\ 4776 HWIO_INTLOCK(); \ 4777 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4778 HWIO_INTFREE();\ 4779 } while (0) 4780 4781 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4782 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4783 4784 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4785 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4786 4787 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4788 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4789 4790 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 4791 4792 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 4793 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 4794 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4795 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4796 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4797 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 4798 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4799 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4800 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4801 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4802 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4803 do {\ 4804 HWIO_INTLOCK(); \ 4805 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4806 HWIO_INTFREE();\ 4807 } while (0) 4808 4809 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4810 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4811 4812 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4813 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4814 4815 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4816 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4817 4818 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 4819 4820 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 4821 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 4822 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4823 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4824 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4825 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4826 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4827 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4828 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4829 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4830 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4831 do {\ 4832 HWIO_INTLOCK(); \ 4833 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4834 HWIO_INTFREE();\ 4835 } while (0) 4836 4837 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4838 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4839 4840 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 4841 4842 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) 4843 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) 4844 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4845 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 4846 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 4847 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 4848 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 4849 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 4850 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 4851 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 4852 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4853 do {\ 4854 HWIO_INTLOCK(); \ 4855 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 4856 HWIO_INTFREE();\ 4857 } while (0) 4858 4859 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4860 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4861 4862 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 4863 4864 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) 4865 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) 4866 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4867 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 4868 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 4869 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 4870 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 4871 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 4872 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 4873 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 4874 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4875 do {\ 4876 HWIO_INTLOCK(); \ 4877 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 4878 HWIO_INTFREE();\ 4879 } while (0) 4880 4881 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4882 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4883 4884 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4885 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4886 4887 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 4888 4889 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) 4890 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) 4891 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 4892 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 4893 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 4894 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 4895 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 4896 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 4897 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 4898 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 4899 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 4900 do {\ 4901 HWIO_INTLOCK(); \ 4902 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 4903 HWIO_INTFREE();\ 4904 } while (0) 4905 4906 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4907 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 4908 4909 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 4910 4911 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 4912 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 4913 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4914 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4915 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4916 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 4917 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4918 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4919 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4920 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4921 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4922 do {\ 4923 HWIO_INTLOCK(); \ 4924 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4925 HWIO_INTFREE();\ 4926 } while (0) 4927 4928 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4929 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4930 4931 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 4932 4933 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 4934 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 4935 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 4936 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 4937 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 4938 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 4939 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 4940 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 4941 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 4942 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 4943 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 4944 do {\ 4945 HWIO_INTLOCK(); \ 4946 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 4947 HWIO_INTFREE();\ 4948 } while (0) 4949 4950 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4951 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4952 4953 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 4954 4955 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 4956 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 4957 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 4958 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 4959 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 4960 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 4961 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 4962 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 4963 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 4964 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 4965 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 4966 do {\ 4967 HWIO_INTLOCK(); \ 4968 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 4969 HWIO_INTFREE();\ 4970 } while (0) 4971 4972 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4973 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4974 4975 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4976 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4977 4978 //// Register REO_R0_REO_RELEASE_RING_ID //// 4979 4980 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4) 4981 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4) 4982 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 4983 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 4984 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 4985 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 4986 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 4987 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 4988 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 4989 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 4990 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 4991 do {\ 4992 HWIO_INTLOCK(); \ 4993 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 4994 HWIO_INTFREE();\ 4995 } while (0) 4996 4997 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 4998 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 4999 5000 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5001 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5002 5003 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5004 5005 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8) 5006 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8) 5007 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5008 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5009 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5010 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5011 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5012 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5013 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5014 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5015 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5016 do {\ 5017 HWIO_INTLOCK(); \ 5018 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5019 HWIO_INTFREE();\ 5020 } while (0) 5021 5022 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5023 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5024 5025 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5026 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5027 5028 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5029 5030 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc) 5031 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc) 5032 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff 5033 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5034 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5035 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5036 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5037 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5038 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5039 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5040 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5041 do {\ 5042 HWIO_INTLOCK(); \ 5043 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5044 HWIO_INTFREE();\ 5045 } while (0) 5046 5047 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5048 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 5049 5050 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5051 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe 5052 5053 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5054 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5055 5056 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5057 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5058 5059 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5060 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5061 5062 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5063 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 5064 5065 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5066 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5067 5068 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5069 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5070 5071 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5072 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5073 5074 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5075 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5076 5077 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5078 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5079 5080 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5081 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5082 5083 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5084 5085 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5086 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5087 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5088 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5089 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5090 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5091 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5092 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5093 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5094 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5095 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5096 do {\ 5097 HWIO_INTLOCK(); \ 5098 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5099 HWIO_INTFREE();\ 5100 } while (0) 5101 5102 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5103 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5104 5105 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5106 5107 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5108 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5109 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5110 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5111 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5112 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5113 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5114 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5115 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5116 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5117 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5118 do {\ 5119 HWIO_INTLOCK(); \ 5120 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5121 HWIO_INTFREE();\ 5122 } while (0) 5123 5124 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5125 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5126 5127 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5128 5129 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5130 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5131 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5132 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5133 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5134 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5135 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5136 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5137 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5138 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5139 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5140 do {\ 5141 HWIO_INTLOCK(); \ 5142 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5143 HWIO_INTFREE();\ 5144 } while (0) 5145 5146 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5147 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5148 5149 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5150 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5151 5152 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5153 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5154 5155 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5156 5157 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5158 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5159 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5160 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5161 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5162 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5163 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5164 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5165 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5166 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5167 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5168 do {\ 5169 HWIO_INTLOCK(); \ 5170 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5171 HWIO_INTFREE();\ 5172 } while (0) 5173 5174 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5175 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5176 5177 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5178 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5179 5180 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5181 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5182 5183 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5184 5185 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5186 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5187 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5188 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5189 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5190 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5191 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5192 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5193 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5194 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5195 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5196 do {\ 5197 HWIO_INTLOCK(); \ 5198 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5199 HWIO_INTFREE();\ 5200 } while (0) 5201 5202 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5203 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5204 5205 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB //// 5206 5207 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) 5208 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) 5209 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5210 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 5211 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ 5212 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK) 5213 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ 5214 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 5215 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ 5216 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) 5217 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5218 do {\ 5219 HWIO_INTLOCK(); \ 5220 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ 5221 HWIO_INTFREE();\ 5222 } while (0) 5223 5224 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5225 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5226 5227 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB //// 5228 5229 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) 5230 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) 5231 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5232 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 5233 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ 5234 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK) 5235 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ 5236 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 5237 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ 5238 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) 5239 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5240 do {\ 5241 HWIO_INTLOCK(); \ 5242 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ 5243 HWIO_INTFREE();\ 5244 } while (0) 5245 5246 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5247 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5248 5249 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5250 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5251 5252 //// Register REO_R0_REO_RELEASE_RING_MSI1_DATA //// 5253 5254 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) 5255 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) 5256 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff 5257 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0 5258 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ 5259 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK) 5260 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ 5261 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 5262 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \ 5263 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val) 5264 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ 5265 do {\ 5266 HWIO_INTLOCK(); \ 5267 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \ 5268 HWIO_INTFREE();\ 5269 } while (0) 5270 5271 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5272 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 5273 5274 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 5275 5276 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 5277 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 5278 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5279 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 5280 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 5281 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 5282 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5283 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5284 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5285 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5286 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5287 do {\ 5288 HWIO_INTLOCK(); \ 5289 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 5290 HWIO_INTFREE();\ 5291 } while (0) 5292 5293 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5294 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5295 5296 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 5297 5298 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504) 5299 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504) 5300 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 5301 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 5302 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 5303 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 5304 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 5305 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 5306 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 5307 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 5308 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 5309 do {\ 5310 HWIO_INTLOCK(); \ 5311 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 5312 HWIO_INTFREE();\ 5313 } while (0) 5314 5315 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5316 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5317 5318 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 5319 5320 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508) 5321 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508) 5322 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 5323 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 5324 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 5325 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 5326 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 5327 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 5328 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 5329 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 5330 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 5331 do {\ 5332 HWIO_INTLOCK(); \ 5333 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 5334 HWIO_INTFREE();\ 5335 } while (0) 5336 5337 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5338 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5339 5340 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5341 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5342 5343 //// Register REO_R0_REO_STATUS_RING_ID //// 5344 5345 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c) 5346 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c) 5347 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 5348 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 5349 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 5350 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 5351 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 5352 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 5353 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 5354 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 5355 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 5356 do {\ 5357 HWIO_INTLOCK(); \ 5358 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 5359 HWIO_INTFREE();\ 5360 } while (0) 5361 5362 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 5363 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 5364 5365 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5366 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 5367 5368 //// Register REO_R0_REO_STATUS_RING_STATUS //// 5369 5370 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510) 5371 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510) 5372 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 5373 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 5374 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 5375 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 5376 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 5377 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 5378 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 5379 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 5380 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 5381 do {\ 5382 HWIO_INTLOCK(); \ 5383 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 5384 HWIO_INTFREE();\ 5385 } while (0) 5386 5387 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5388 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5389 5390 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5391 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5392 5393 //// Register REO_R0_REO_STATUS_RING_MISC //// 5394 5395 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514) 5396 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514) 5397 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff 5398 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 5399 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 5400 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 5401 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 5402 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 5403 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 5404 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 5405 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 5406 do {\ 5407 HWIO_INTLOCK(); \ 5408 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 5409 HWIO_INTFREE();\ 5410 } while (0) 5411 5412 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5413 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 5414 5415 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5416 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 5417 5418 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5419 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5420 5421 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5422 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5423 5424 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5425 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5426 5427 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5428 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 5429 5430 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5431 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5432 5433 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5434 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5435 5436 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5437 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5438 5439 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5440 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 5441 5442 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5443 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5444 5445 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5446 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5447 5448 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 5449 5450 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518) 5451 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518) 5452 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 5453 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 5454 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 5455 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 5456 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 5457 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 5458 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 5459 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 5460 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5461 do {\ 5462 HWIO_INTLOCK(); \ 5463 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 5464 HWIO_INTFREE();\ 5465 } while (0) 5466 5467 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5468 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5469 5470 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 5471 5472 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c) 5473 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c) 5474 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 5475 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 5476 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 5477 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 5478 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 5479 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 5480 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 5481 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 5482 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5483 do {\ 5484 HWIO_INTLOCK(); \ 5485 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 5486 HWIO_INTFREE();\ 5487 } while (0) 5488 5489 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5490 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5491 5492 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 5493 5494 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528) 5495 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528) 5496 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5497 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 5498 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 5499 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 5500 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5501 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5502 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5503 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5504 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5505 do {\ 5506 HWIO_INTLOCK(); \ 5507 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 5508 HWIO_INTFREE();\ 5509 } while (0) 5510 5511 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5512 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5513 5514 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5515 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5516 5517 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5518 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5519 5520 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 5521 5522 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c) 5523 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c) 5524 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5525 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 5526 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 5527 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 5528 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5529 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5530 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5531 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5532 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5533 do {\ 5534 HWIO_INTLOCK(); \ 5535 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 5536 HWIO_INTFREE();\ 5537 } while (0) 5538 5539 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5540 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5541 5542 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5543 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5544 5545 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5546 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5547 5548 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 5549 5550 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530) 5551 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530) 5552 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5553 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 5554 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5555 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 5556 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5557 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5558 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5559 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5560 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5561 do {\ 5562 HWIO_INTLOCK(); \ 5563 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5564 HWIO_INTFREE();\ 5565 } while (0) 5566 5567 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5568 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5569 5570 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 5571 5572 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c) 5573 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c) 5574 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5575 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 5576 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 5577 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 5578 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 5579 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 5580 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 5581 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 5582 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5583 do {\ 5584 HWIO_INTLOCK(); \ 5585 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 5586 HWIO_INTFREE();\ 5587 } while (0) 5588 5589 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5590 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5591 5592 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 5593 5594 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550) 5595 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550) 5596 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5597 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 5598 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 5599 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 5600 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 5601 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 5602 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 5603 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 5604 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5605 do {\ 5606 HWIO_INTLOCK(); \ 5607 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 5608 HWIO_INTFREE();\ 5609 } while (0) 5610 5611 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5612 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5613 5614 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5615 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5616 5617 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 5618 5619 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554) 5620 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554) 5621 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 5622 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 5623 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 5624 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 5625 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 5626 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 5627 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 5628 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 5629 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 5630 do {\ 5631 HWIO_INTLOCK(); \ 5632 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 5633 HWIO_INTFREE();\ 5634 } while (0) 5635 5636 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5637 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 5638 5639 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 5640 5641 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558) 5642 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558) 5643 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5644 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 5645 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 5646 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 5647 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5648 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5649 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5650 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5651 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5652 do {\ 5653 HWIO_INTLOCK(); \ 5654 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 5655 HWIO_INTFREE();\ 5656 } while (0) 5657 5658 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5659 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5660 5661 //// Register REO_R0_WATCHDOG_TIMEOUT //// 5662 5663 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c) 5664 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c) 5665 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff 5666 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 5667 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 5668 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 5669 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 5670 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 5671 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 5672 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 5673 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 5674 do {\ 5675 HWIO_INTLOCK(); \ 5676 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 5677 HWIO_INTFREE();\ 5678 } while (0) 5679 5680 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000 5681 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc 5682 5683 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 5684 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 5685 5686 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 5687 5688 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560) 5689 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560) 5690 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 5691 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 5692 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 5693 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 5694 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 5695 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 5696 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 5697 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 5698 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 5699 do {\ 5700 HWIO_INTLOCK(); \ 5701 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 5702 HWIO_INTFREE();\ 5703 } while (0) 5704 5705 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 5706 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 5707 5708 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 5709 5710 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564) 5711 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564) 5712 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 5713 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 5714 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 5715 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 5716 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 5717 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 5718 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 5719 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 5720 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 5721 do {\ 5722 HWIO_INTLOCK(); \ 5723 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 5724 HWIO_INTFREE();\ 5725 } while (0) 5726 5727 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 5728 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 5729 5730 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 5731 5732 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568) 5733 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568) 5734 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 5735 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 5736 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 5737 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 5738 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 5739 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 5740 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 5741 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 5742 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 5743 do {\ 5744 HWIO_INTLOCK(); \ 5745 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 5746 HWIO_INTFREE();\ 5747 } while (0) 5748 5749 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 5750 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 5751 5752 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 5753 5754 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c) 5755 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c) 5756 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 5757 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 5758 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 5759 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 5760 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 5761 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 5762 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 5763 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 5764 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 5765 do {\ 5766 HWIO_INTLOCK(); \ 5767 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 5768 HWIO_INTFREE();\ 5769 } while (0) 5770 5771 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 5772 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 5773 5774 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 5775 5776 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570) 5777 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570) 5778 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 5779 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 5780 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 5781 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 5782 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 5783 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 5784 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 5785 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 5786 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 5787 do {\ 5788 HWIO_INTLOCK(); \ 5789 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 5790 HWIO_INTFREE();\ 5791 } while (0) 5792 5793 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 5794 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 5795 5796 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 5797 5798 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574) 5799 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574) 5800 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 5801 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 5802 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 5803 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 5804 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 5805 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 5806 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 5807 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 5808 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 5809 do {\ 5810 HWIO_INTLOCK(); \ 5811 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 5812 HWIO_INTFREE();\ 5813 } while (0) 5814 5815 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5816 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 5817 5818 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 5819 5820 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578) 5821 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578) 5822 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 5823 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 5824 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 5825 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 5826 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 5827 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 5828 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 5829 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 5830 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 5831 do {\ 5832 HWIO_INTLOCK(); \ 5833 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 5834 HWIO_INTFREE();\ 5835 } while (0) 5836 5837 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5838 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 5839 5840 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 5841 5842 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c) 5843 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c) 5844 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 5845 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 5846 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 5847 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 5848 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 5849 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 5850 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 5851 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 5852 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 5853 do {\ 5854 HWIO_INTLOCK(); \ 5855 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 5856 HWIO_INTFREE();\ 5857 } while (0) 5858 5859 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 5860 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 5861 5862 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 5863 5864 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580) 5865 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580) 5866 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 5867 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 5868 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 5869 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 5870 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 5871 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 5872 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 5873 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 5874 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 5875 do {\ 5876 HWIO_INTLOCK(); \ 5877 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 5878 HWIO_INTFREE();\ 5879 } while (0) 5880 5881 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 5882 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 5883 5884 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 5885 5886 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584) 5887 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584) 5888 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 5889 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 5890 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 5891 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 5892 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 5893 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 5894 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 5895 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 5896 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 5897 do {\ 5898 HWIO_INTLOCK(); \ 5899 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 5900 HWIO_INTFREE();\ 5901 } while (0) 5902 5903 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5904 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 5905 5906 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 5907 5908 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588) 5909 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588) 5910 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 5911 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 5912 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 5913 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 5914 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 5915 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 5916 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 5917 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 5918 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 5919 do {\ 5920 HWIO_INTLOCK(); \ 5921 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 5922 HWIO_INTFREE();\ 5923 } while (0) 5924 5925 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5926 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 5927 5928 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 5929 5930 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c) 5931 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c) 5932 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 5933 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 5934 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 5935 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 5936 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 5937 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 5938 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 5939 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 5940 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 5941 do {\ 5942 HWIO_INTLOCK(); \ 5943 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 5944 HWIO_INTFREE();\ 5945 } while (0) 5946 5947 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 5948 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 5949 5950 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 5951 5952 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590) 5953 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590) 5954 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 5955 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 5956 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 5957 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 5958 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 5959 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 5960 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 5961 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 5962 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 5963 do {\ 5964 HWIO_INTLOCK(); \ 5965 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 5966 HWIO_INTFREE();\ 5967 } while (0) 5968 5969 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 5970 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 5971 5972 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 5973 5974 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594) 5975 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594) 5976 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 5977 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 5978 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 5979 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 5980 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 5981 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 5982 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 5983 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 5984 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 5985 do {\ 5986 HWIO_INTLOCK(); \ 5987 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 5988 HWIO_INTFREE();\ 5989 } while (0) 5990 5991 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5992 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 5993 5994 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 5995 5996 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598) 5997 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598) 5998 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 5999 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6000 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6001 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6002 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6003 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6004 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6005 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6006 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6007 do {\ 6008 HWIO_INTLOCK(); \ 6009 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6010 HWIO_INTFREE();\ 6011 } while (0) 6012 6013 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6014 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6015 6016 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6017 6018 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c) 6019 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c) 6020 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6021 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6022 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6023 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6024 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6025 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6026 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6027 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6028 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6029 do {\ 6030 HWIO_INTLOCK(); \ 6031 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6032 HWIO_INTFREE();\ 6033 } while (0) 6034 6035 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6036 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6037 6038 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6039 6040 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0) 6041 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0) 6042 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6043 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6044 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6045 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6046 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6047 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6048 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6049 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6050 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6051 do {\ 6052 HWIO_INTLOCK(); \ 6053 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6054 HWIO_INTFREE();\ 6055 } while (0) 6056 6057 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6058 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6059 6060 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6061 6062 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4) 6063 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4) 6064 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6065 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6066 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6067 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6068 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6069 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6070 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6071 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6072 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6073 do {\ 6074 HWIO_INTLOCK(); \ 6075 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6076 HWIO_INTFREE();\ 6077 } while (0) 6078 6079 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6080 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6081 6082 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6083 6084 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8) 6085 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8) 6086 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6087 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6088 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6089 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6090 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6091 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6092 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6093 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6094 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6095 do {\ 6096 HWIO_INTLOCK(); \ 6097 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6098 HWIO_INTFREE();\ 6099 } while (0) 6100 6101 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6102 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6103 6104 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6105 6106 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac) 6107 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac) 6108 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6109 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6110 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6111 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6112 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6113 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6114 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6115 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6116 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6117 do {\ 6118 HWIO_INTLOCK(); \ 6119 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6120 HWIO_INTFREE();\ 6121 } while (0) 6122 6123 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6124 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6125 6126 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6127 6128 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0) 6129 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0) 6130 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6131 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6132 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6133 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6134 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6135 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6136 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6137 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6138 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6139 do {\ 6140 HWIO_INTLOCK(); \ 6141 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6142 HWIO_INTFREE();\ 6143 } while (0) 6144 6145 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6146 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6147 6148 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6149 6150 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4) 6151 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4) 6152 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6153 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6154 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6155 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6156 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6157 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6158 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6159 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6160 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6161 do {\ 6162 HWIO_INTLOCK(); \ 6163 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6164 HWIO_INTFREE();\ 6165 } while (0) 6166 6167 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6168 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6169 6170 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6171 6172 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8) 6173 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8) 6174 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6175 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6176 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6177 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6178 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6179 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6180 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6181 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6182 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6183 do {\ 6184 HWIO_INTLOCK(); \ 6185 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6186 HWIO_INTFREE();\ 6187 } while (0) 6188 6189 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6190 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6191 6192 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6193 6194 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc) 6195 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc) 6196 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6197 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6198 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6199 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6200 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6201 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6202 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6203 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6204 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6205 do {\ 6206 HWIO_INTLOCK(); \ 6207 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6208 HWIO_INTFREE();\ 6209 } while (0) 6210 6211 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6212 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6213 6214 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6215 6216 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0) 6217 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0) 6218 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6219 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6220 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6221 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6222 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6223 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6224 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6225 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6226 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6227 do {\ 6228 HWIO_INTLOCK(); \ 6229 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6230 HWIO_INTFREE();\ 6231 } while (0) 6232 6233 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6234 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6235 6236 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6237 6238 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4) 6239 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4) 6240 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6241 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6242 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6243 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6244 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6245 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6246 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6247 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6248 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6249 do {\ 6250 HWIO_INTLOCK(); \ 6251 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6252 HWIO_INTFREE();\ 6253 } while (0) 6254 6255 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6256 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6257 6258 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 6259 6260 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8) 6261 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8) 6262 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 6263 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 6264 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 6265 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 6266 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 6267 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 6268 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 6269 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 6270 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 6271 do {\ 6272 HWIO_INTLOCK(); \ 6273 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 6274 HWIO_INTFREE();\ 6275 } while (0) 6276 6277 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 6278 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 6279 6280 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 6281 6282 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc) 6283 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc) 6284 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 6285 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 6286 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 6287 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 6288 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 6289 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 6290 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 6291 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 6292 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 6293 do {\ 6294 HWIO_INTLOCK(); \ 6295 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 6296 HWIO_INTFREE();\ 6297 } while (0) 6298 6299 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 6300 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 6301 6302 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 6303 6304 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0) 6305 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0) 6306 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 6307 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 6308 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 6309 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 6310 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 6311 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 6312 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 6313 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 6314 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 6315 do {\ 6316 HWIO_INTLOCK(); \ 6317 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 6318 HWIO_INTFREE();\ 6319 } while (0) 6320 6321 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 6322 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 6323 6324 //// Register REO_R0_AGING_CONTROL //// 6325 6326 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4) 6327 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4) 6328 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 6329 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 6330 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 6331 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 6332 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 6333 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 6334 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 6335 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 6336 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 6337 do {\ 6338 HWIO_INTLOCK(); \ 6339 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 6340 HWIO_INTFREE();\ 6341 } while (0) 6342 6343 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 6344 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 6345 6346 //// Register REO_R0_MISC_CTL //// 6347 6348 #define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8) 6349 #define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8) 6350 #define HWIO_REO_R0_MISC_CTL_RMSK 0x000fffff 6351 #define HWIO_REO_R0_MISC_CTL_SHFT 0 6352 #define HWIO_REO_R0_MISC_CTL_IN(x) \ 6353 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK) 6354 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ 6355 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) 6356 #define HWIO_REO_R0_MISC_CTL_OUT(x, val) \ 6357 out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val) 6358 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ 6359 do {\ 6360 HWIO_INTLOCK(); \ 6361 out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \ 6362 HWIO_INTFREE();\ 6363 } while (0) 6364 6365 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x000e0000 6366 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 0x11 6367 6368 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000 6369 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10 6370 6371 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x00008000 6372 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 0xf 6373 6374 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x00007fff 6375 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0 6376 6377 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 6378 6379 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc) 6380 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc) 6381 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 6382 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 6383 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 6384 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 6385 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 6386 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 6387 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 6388 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 6389 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 6390 do {\ 6391 HWIO_INTLOCK(); \ 6392 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 6393 HWIO_INTFREE();\ 6394 } while (0) 6395 6396 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 6397 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 6398 6399 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 6400 6401 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0) 6402 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0) 6403 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 6404 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 6405 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 6406 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 6407 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 6408 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 6409 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 6410 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 6411 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 6412 do {\ 6413 HWIO_INTLOCK(); \ 6414 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 6415 HWIO_INTFREE();\ 6416 } while (0) 6417 6418 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 6419 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 6420 6421 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 6422 6423 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4) 6424 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4) 6425 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 6426 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 6427 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 6428 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 6429 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 6430 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 6431 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 6432 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 6433 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 6434 do {\ 6435 HWIO_INTLOCK(); \ 6436 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 6437 HWIO_INTFREE();\ 6438 } while (0) 6439 6440 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 6441 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 6442 6443 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 6444 6445 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8) 6446 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8) 6447 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 6448 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 6449 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 6450 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 6451 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 6452 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 6453 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 6454 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 6455 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 6456 do {\ 6457 HWIO_INTLOCK(); \ 6458 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 6459 HWIO_INTFREE();\ 6460 } while (0) 6461 6462 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 6463 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 6464 6465 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 6466 6467 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec) 6468 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec) 6469 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 6470 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 6471 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 6472 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 6473 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 6474 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 6475 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 6476 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 6477 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 6478 do {\ 6479 HWIO_INTLOCK(); \ 6480 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 6481 HWIO_INTFREE();\ 6482 } while (0) 6483 6484 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 6485 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 6486 6487 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 6488 6489 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0) 6490 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0) 6491 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 6492 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 6493 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 6494 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 6495 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 6496 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 6497 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 6498 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 6499 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 6500 do {\ 6501 HWIO_INTLOCK(); \ 6502 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 6503 HWIO_INTFREE();\ 6504 } while (0) 6505 6506 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 6507 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 6508 6509 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 6510 6511 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4) 6512 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4) 6513 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 6514 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 6515 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 6516 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 6517 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 6518 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 6519 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 6520 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 6521 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 6522 do {\ 6523 HWIO_INTLOCK(); \ 6524 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 6525 HWIO_INTFREE();\ 6526 } while (0) 6527 6528 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 6529 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 6530 6531 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 6532 6533 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8) 6534 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8) 6535 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 6536 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 6537 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 6538 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 6539 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 6540 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 6541 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 6542 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 6543 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 6544 do {\ 6545 HWIO_INTLOCK(); \ 6546 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 6547 HWIO_INTFREE();\ 6548 } while (0) 6549 6550 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 6551 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 6552 6553 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 6554 6555 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc) 6556 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc) 6557 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 6558 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 6559 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 6560 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 6561 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 6562 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 6563 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 6564 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 6565 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 6566 do {\ 6567 HWIO_INTLOCK(); \ 6568 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 6569 HWIO_INTFREE();\ 6570 } while (0) 6571 6572 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 6573 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 6574 6575 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 6576 6577 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600) 6578 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600) 6579 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 6580 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 6581 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 6582 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 6583 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 6584 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 6585 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 6586 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 6587 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 6588 do {\ 6589 HWIO_INTLOCK(); \ 6590 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 6591 HWIO_INTFREE();\ 6592 } while (0) 6593 6594 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 6595 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 6596 6597 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 6598 6599 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604) 6600 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604) 6601 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 6602 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 6603 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 6604 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 6605 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 6606 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 6607 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 6608 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 6609 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 6610 do {\ 6611 HWIO_INTLOCK(); \ 6612 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 6613 HWIO_INTFREE();\ 6614 } while (0) 6615 6616 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 6617 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 6618 6619 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 6620 6621 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608) 6622 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608) 6623 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 6624 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 6625 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 6626 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 6627 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 6628 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 6629 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 6630 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 6631 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 6632 do {\ 6633 HWIO_INTLOCK(); \ 6634 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 6635 HWIO_INTFREE();\ 6636 } while (0) 6637 6638 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 6639 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 6640 6641 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 6642 6643 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c) 6644 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c) 6645 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 6646 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 6647 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 6648 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 6649 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 6650 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 6651 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 6652 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 6653 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 6654 do {\ 6655 HWIO_INTLOCK(); \ 6656 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 6657 HWIO_INTFREE();\ 6658 } while (0) 6659 6660 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 6661 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 6662 6663 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 6664 6665 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610) 6666 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610) 6667 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 6668 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 6669 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 6670 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 6671 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 6672 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 6673 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 6674 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 6675 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 6676 do {\ 6677 HWIO_INTLOCK(); \ 6678 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 6679 HWIO_INTFREE();\ 6680 } while (0) 6681 6682 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 6683 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 6684 6685 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 6686 6687 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614) 6688 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614) 6689 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 6690 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 6691 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 6692 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 6693 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 6694 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 6695 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 6696 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 6697 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 6698 do {\ 6699 HWIO_INTLOCK(); \ 6700 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 6701 HWIO_INTFREE();\ 6702 } while (0) 6703 6704 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 6705 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 6706 6707 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 6708 6709 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618) 6710 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618) 6711 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 6712 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 6713 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 6714 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 6715 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 6716 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 6717 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 6718 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 6719 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 6720 do {\ 6721 HWIO_INTLOCK(); \ 6722 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 6723 HWIO_INTFREE();\ 6724 } while (0) 6725 6726 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 6727 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 6728 6729 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 6730 6731 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c) 6732 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c) 6733 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 6734 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 6735 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 6736 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 6737 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 6738 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 6739 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 6740 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 6741 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 6742 do {\ 6743 HWIO_INTLOCK(); \ 6744 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 6745 HWIO_INTFREE();\ 6746 } while (0) 6747 6748 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 6749 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 6750 6751 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 6752 6753 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620) 6754 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620) 6755 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 6756 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 6757 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 6758 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 6759 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 6760 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 6761 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 6762 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 6763 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 6764 do {\ 6765 HWIO_INTLOCK(); \ 6766 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 6767 HWIO_INTFREE();\ 6768 } while (0) 6769 6770 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 6771 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 6772 6773 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 6774 6775 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624) 6776 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624) 6777 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 6778 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 6779 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 6780 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 6781 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 6782 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 6783 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 6784 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 6785 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 6786 do {\ 6787 HWIO_INTLOCK(); \ 6788 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 6789 HWIO_INTFREE();\ 6790 } while (0) 6791 6792 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 6793 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 6794 6795 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 6796 6797 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628) 6798 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628) 6799 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 6800 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 6801 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 6802 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 6803 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 6804 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 6805 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 6806 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 6807 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 6808 do {\ 6809 HWIO_INTLOCK(); \ 6810 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 6811 HWIO_INTFREE();\ 6812 } while (0) 6813 6814 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 6815 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 6816 6817 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 6818 6819 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c) 6820 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c) 6821 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 6822 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 6823 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 6824 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 6825 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 6826 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 6827 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 6828 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 6829 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 6830 do {\ 6831 HWIO_INTLOCK(); \ 6832 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 6833 HWIO_INTFREE();\ 6834 } while (0) 6835 6836 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 6837 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 6838 6839 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 6840 6841 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630) 6842 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630) 6843 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 6844 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 6845 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 6846 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 6847 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 6848 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 6849 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 6850 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 6851 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 6852 do {\ 6853 HWIO_INTLOCK(); \ 6854 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 6855 HWIO_INTFREE();\ 6856 } while (0) 6857 6858 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 6859 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 6860 6861 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 6862 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 6863 6864 //// Register REO_R0_GXI_TESTBUS_LOWER //// 6865 6866 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000654) 6867 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000654) 6868 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 6869 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 6870 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 6871 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 6872 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 6873 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 6874 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 6875 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 6876 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 6877 do {\ 6878 HWIO_INTLOCK(); \ 6879 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 6880 HWIO_INTFREE();\ 6881 } while (0) 6882 6883 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 6884 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 6885 6886 //// Register REO_R0_GXI_TESTBUS_UPPER //// 6887 6888 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000658) 6889 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000658) 6890 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 6891 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 6892 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 6893 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 6894 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 6895 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 6896 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 6897 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 6898 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 6899 do {\ 6900 HWIO_INTLOCK(); \ 6901 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 6902 HWIO_INTFREE();\ 6903 } while (0) 6904 6905 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 6906 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 6907 6908 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 6909 6910 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000065c) 6911 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000065c) 6912 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 6913 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 6914 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 6915 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 6916 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 6917 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 6918 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 6919 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 6920 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 6921 do {\ 6922 HWIO_INTLOCK(); \ 6923 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 6924 HWIO_INTFREE();\ 6925 } while (0) 6926 6927 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 6928 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 6929 6930 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 6931 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 6932 6933 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 6934 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 6935 6936 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 6937 6938 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000660) 6939 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000660) 6940 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 6941 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 6942 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 6943 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 6944 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 6945 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 6946 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 6947 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 6948 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6949 do {\ 6950 HWIO_INTLOCK(); \ 6951 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 6952 HWIO_INTFREE();\ 6953 } while (0) 6954 6955 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6956 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6957 6958 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 6959 6960 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000664) 6961 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000664) 6962 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 6963 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 6964 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 6965 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 6966 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 6967 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 6968 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 6969 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 6970 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 6971 do {\ 6972 HWIO_INTLOCK(); \ 6973 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 6974 HWIO_INTFREE();\ 6975 } while (0) 6976 6977 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 6978 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 6979 6980 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 6981 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 6982 6983 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 6984 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 6985 6986 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 6987 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 6988 6989 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 6990 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 6991 6992 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 6993 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 6994 6995 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 6996 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 6997 6998 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 6999 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 7000 7001 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 7002 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 7003 7004 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 7005 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 7006 7007 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 7008 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 7009 7010 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 7011 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 7012 7013 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 7014 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 7015 7016 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7017 7018 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000668) 7019 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000668) 7020 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7021 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7022 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7023 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7024 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7025 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7026 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7027 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7028 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7029 do {\ 7030 HWIO_INTLOCK(); \ 7031 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7032 HWIO_INTFREE();\ 7033 } while (0) 7034 7035 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7036 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7037 7038 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7039 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7040 7041 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7042 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7043 7044 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7045 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7046 7047 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7048 7049 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000066c) 7050 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000066c) 7051 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7052 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7053 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7054 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7055 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7056 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7057 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7058 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 7059 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 7060 do {\ 7061 HWIO_INTLOCK(); \ 7062 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 7063 HWIO_INTFREE();\ 7064 } while (0) 7065 7066 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 7067 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 7068 7069 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 7070 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 7071 7072 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 7073 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 7074 7075 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 7076 7077 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000670) 7078 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000670) 7079 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 7080 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 7081 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 7082 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 7083 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 7084 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 7085 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 7086 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 7087 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 7088 do {\ 7089 HWIO_INTLOCK(); \ 7090 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 7091 HWIO_INTFREE();\ 7092 } while (0) 7093 7094 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 7095 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 7096 7097 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7098 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 7099 7100 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 7101 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 7102 7103 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 7104 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 7105 7106 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 7107 7108 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000674) 7109 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000674) 7110 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 7111 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 7112 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 7113 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 7114 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 7115 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 7116 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 7117 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 7118 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 7119 do {\ 7120 HWIO_INTLOCK(); \ 7121 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 7122 HWIO_INTFREE();\ 7123 } while (0) 7124 7125 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 7126 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 7127 7128 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7129 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 7130 7131 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 7132 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 7133 7134 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 7135 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 7136 7137 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 7138 7139 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000678) 7140 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000678) 7141 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 7142 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 7143 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 7144 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 7145 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 7146 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 7147 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 7148 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 7149 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 7150 do {\ 7151 HWIO_INTLOCK(); \ 7152 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 7153 HWIO_INTFREE();\ 7154 } while (0) 7155 7156 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 7157 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 7158 7159 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 7160 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 7161 7162 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 7163 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 7164 7165 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 7166 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 7167 7168 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 7169 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 7170 7171 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 7172 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 7173 7174 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 7175 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 7176 7177 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 7178 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 7179 7180 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 7181 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 7182 7183 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 7184 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 7185 7186 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 7187 7188 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000067c) 7189 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000067c) 7190 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 7191 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 7192 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 7193 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 7194 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 7195 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 7196 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 7197 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 7198 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 7199 do {\ 7200 HWIO_INTLOCK(); \ 7201 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 7202 HWIO_INTFREE();\ 7203 } while (0) 7204 7205 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 7206 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 7207 7208 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 7209 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 7210 7211 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 7212 7213 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000680) 7214 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000680) 7215 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 7216 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 7217 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 7218 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 7219 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 7220 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 7221 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 7222 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 7223 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 7224 do {\ 7225 HWIO_INTLOCK(); \ 7226 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 7227 HWIO_INTFREE();\ 7228 } while (0) 7229 7230 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 7231 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 7232 7233 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 7234 7235 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000684) 7236 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000684) 7237 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 7238 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 7239 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 7240 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 7241 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 7242 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 7243 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 7244 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 7245 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 7246 do {\ 7247 HWIO_INTLOCK(); \ 7248 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 7249 HWIO_INTFREE();\ 7250 } while (0) 7251 7252 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 7253 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 7254 7255 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 7256 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 7257 7258 //// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL //// 7259 7260 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000688) 7261 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000688) 7262 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 7263 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 7264 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 7265 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 7266 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 7267 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 7268 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 7269 out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 7270 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 7271 do {\ 7272 HWIO_INTLOCK(); \ 7273 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 7274 HWIO_INTFREE();\ 7275 } while (0) 7276 7277 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 7278 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 7279 7280 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 7281 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 7282 7283 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 7284 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 7285 7286 //// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL //// 7287 7288 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000068c) 7289 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000068c) 7290 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 7291 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 7292 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 7293 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 7294 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 7295 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 7296 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 7297 out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 7298 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 7299 do {\ 7300 HWIO_INTLOCK(); \ 7301 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 7302 HWIO_INTFREE();\ 7303 } while (0) 7304 7305 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 7306 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 7307 7308 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 7309 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 7310 7311 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 7312 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 7313 7314 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 7315 7316 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000690) 7317 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000690) 7318 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 7319 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 7320 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 7321 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 7322 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 7323 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 7324 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 7325 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 7326 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 7327 do {\ 7328 HWIO_INTLOCK(); \ 7329 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 7330 HWIO_INTFREE();\ 7331 } while (0) 7332 7333 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 7334 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 7335 7336 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 7337 7338 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000694) 7339 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000694) 7340 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 7341 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 7342 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 7343 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 7344 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 7345 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 7346 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 7347 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 7348 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 7349 do {\ 7350 HWIO_INTLOCK(); \ 7351 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 7352 HWIO_INTFREE();\ 7353 } while (0) 7354 7355 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 7356 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 7357 7358 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 7359 7360 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000698) 7361 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000698) 7362 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 7363 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 7364 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 7365 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 7366 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 7367 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 7368 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 7369 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 7370 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 7371 do {\ 7372 HWIO_INTLOCK(); \ 7373 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 7374 HWIO_INTFREE();\ 7375 } while (0) 7376 7377 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 7378 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 7379 7380 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 7381 7382 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000069c) 7383 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000069c) 7384 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 7385 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 7386 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 7387 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 7388 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 7389 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 7390 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 7391 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 7392 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 7393 do {\ 7394 HWIO_INTLOCK(); \ 7395 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 7396 HWIO_INTFREE();\ 7397 } while (0) 7398 7399 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 7400 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 7401 7402 //// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 7403 7404 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000006a0) 7405 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000006a0) 7406 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 7407 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 7408 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 7409 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 7410 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 7411 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 7412 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 7413 out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 7414 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 7415 do {\ 7416 HWIO_INTLOCK(); \ 7417 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 7418 HWIO_INTFREE();\ 7419 } while (0) 7420 7421 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 7422 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 7423 7424 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 7425 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 7426 7427 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 7428 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 7429 7430 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 7431 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 7432 7433 //// Register REO_R0_CACHE_CTL_CONFIG //// 7434 7435 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x000006a4) 7436 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x000006a4) 7437 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff 7438 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 7439 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 7440 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 7441 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 7442 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 7443 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 7444 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 7445 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 7446 do {\ 7447 HWIO_INTLOCK(); \ 7448 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 7449 HWIO_INTFREE();\ 7450 } while (0) 7451 7452 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 7453 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18 7454 7455 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000 7456 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17 7457 7458 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000 7459 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16 7460 7461 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000 7462 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15 7463 7464 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000 7465 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14 7466 7467 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000 7468 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13 7469 7470 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000 7471 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12 7472 7473 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000 7474 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11 7475 7476 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00 7477 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9 7478 7479 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff 7480 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 7481 7482 //// Register REO_R0_CACHE_CTL_CONTROL //// 7483 7484 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x000006a8) 7485 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x000006a8) 7486 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003 7487 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 7488 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 7489 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 7490 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 7491 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 7492 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 7493 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 7494 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 7495 do {\ 7496 HWIO_INTLOCK(); \ 7497 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 7498 HWIO_INTFREE();\ 7499 } while (0) 7500 7501 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002 7502 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1 7503 7504 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 7505 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 7506 7507 //// Register REO_R0_CACHE_CTL_CONFIG_SET //// 7508 7509 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x000006ac) 7510 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x000006ac) 7511 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff 7512 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0 7513 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ 7514 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK) 7515 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ 7516 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) 7517 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \ 7518 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val) 7519 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ 7520 do {\ 7521 HWIO_INTLOCK(); \ 7522 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \ 7523 HWIO_INTFREE();\ 7524 } while (0) 7525 7526 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x01ffffff 7527 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0x0 7528 7529 //// Register REO_R0_CACHE_CTL_SET_SIZE //// 7530 7531 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x000006b0) 7532 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x000006b0) 7533 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff 7534 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0 7535 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ 7536 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK) 7537 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ 7538 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) 7539 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \ 7540 out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val) 7541 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ 7542 do {\ 7543 HWIO_INTLOCK(); \ 7544 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \ 7545 HWIO_INTFREE();\ 7546 } while (0) 7547 7548 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff 7549 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0 7550 7551 //// Register REO_R0_CLK_GATE_CTRL //// 7552 7553 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x000006b4) 7554 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x000006b4) 7555 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 7556 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 7557 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 7558 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 7559 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 7560 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 7561 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 7562 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 7563 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 7564 do {\ 7565 HWIO_INTLOCK(); \ 7566 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 7567 HWIO_INTFREE();\ 7568 } while (0) 7569 7570 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 7571 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 7572 7573 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 7574 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 7575 7576 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 7577 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 7578 7579 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 7580 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 7581 7582 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 7583 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 7584 7585 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 7586 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 7587 7588 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x00001000 7589 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 0xc 7590 7591 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x00000800 7592 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 0xb 7593 7594 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 7595 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 7596 7597 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 7598 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 7599 7600 //// Register REO_R0_EVENTMASK_IX_0 //// 7601 7602 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x000006b8) 7603 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x000006b8) 7604 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 7605 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 7606 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 7607 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 7608 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 7609 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 7610 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 7611 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 7612 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 7613 do {\ 7614 HWIO_INTLOCK(); \ 7615 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 7616 HWIO_INTFREE();\ 7617 } while (0) 7618 7619 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 7620 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 7621 7622 //// Register REO_R0_EVENTMASK_IX_1 //// 7623 7624 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x000006bc) 7625 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x000006bc) 7626 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 7627 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 7628 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 7629 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 7630 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 7631 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 7632 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 7633 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 7634 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 7635 do {\ 7636 HWIO_INTLOCK(); \ 7637 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 7638 HWIO_INTFREE();\ 7639 } while (0) 7640 7641 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 7642 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 7643 7644 //// Register REO_R0_EVENTMASK_IX_2 //// 7645 7646 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006c0) 7647 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006c0) 7648 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 7649 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 7650 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 7651 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 7652 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 7653 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 7654 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 7655 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 7656 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 7657 do {\ 7658 HWIO_INTLOCK(); \ 7659 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 7660 HWIO_INTFREE();\ 7661 } while (0) 7662 7663 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 7664 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 7665 7666 //// Register REO_R0_EVENTMASK_IX_3 //// 7667 7668 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006c4) 7669 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006c4) 7670 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 7671 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 7672 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 7673 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 7674 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 7675 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 7676 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 7677 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 7678 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 7679 do {\ 7680 HWIO_INTLOCK(); \ 7681 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 7682 HWIO_INTFREE();\ 7683 } while (0) 7684 7685 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 7686 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 7687 7688 //// Register REO_R1_MISC_DEBUG_CTRL //// 7689 7690 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 7691 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 7692 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff 7693 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 7694 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 7695 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 7696 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 7697 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 7698 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 7699 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 7700 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 7701 do {\ 7702 HWIO_INTLOCK(); \ 7703 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 7704 HWIO_INTFREE();\ 7705 } while (0) 7706 7707 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 7708 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 0x1f 7709 7710 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 7711 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e 7712 7713 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 7714 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 7715 7716 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 7717 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 7718 7719 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 7720 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 7721 7722 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 7723 7724 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 7725 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 7726 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 7727 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 7728 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 7729 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 7730 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 7731 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 7732 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 7733 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 7734 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 7735 do {\ 7736 HWIO_INTLOCK(); \ 7737 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 7738 HWIO_INTFREE();\ 7739 } while (0) 7740 7741 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 7742 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 7743 7744 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 7745 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 7746 7747 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 7748 7749 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 7750 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 7751 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff 7752 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 7753 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 7754 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 7755 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 7756 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 7757 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 7758 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 7759 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 7760 do {\ 7761 HWIO_INTLOCK(); \ 7762 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 7763 HWIO_INTFREE();\ 7764 } while (0) 7765 7766 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800 7767 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb 7768 7769 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400 7770 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa 7771 7772 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200 7773 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9 7774 7775 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff 7776 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 7777 7778 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 7779 7780 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 7781 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 7782 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 7783 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 7784 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 7785 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 7786 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 7787 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 7788 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 7789 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 7790 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 7791 do {\ 7792 HWIO_INTLOCK(); \ 7793 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 7794 HWIO_INTFREE();\ 7795 } while (0) 7796 7797 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 7798 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 7799 7800 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 7801 7802 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 7803 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 7804 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 7805 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 7806 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 7807 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 7808 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 7809 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 7810 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 7811 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 7812 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 7813 do {\ 7814 HWIO_INTLOCK(); \ 7815 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 7816 HWIO_INTFREE();\ 7817 } while (0) 7818 7819 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 7820 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 7821 7822 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 7823 7824 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 7825 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 7826 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 7827 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 7828 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 7829 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 7830 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 7831 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 7832 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 7833 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 7834 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 7835 do {\ 7836 HWIO_INTLOCK(); \ 7837 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 7838 HWIO_INTFREE();\ 7839 } while (0) 7840 7841 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 7842 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 7843 7844 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 7845 7846 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 7847 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 7848 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff 7849 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 7850 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 7851 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 7852 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 7853 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 7854 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 7855 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 7856 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 7857 do {\ 7858 HWIO_INTLOCK(); \ 7859 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 7860 HWIO_INTFREE();\ 7861 } while (0) 7862 7863 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff 7864 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 7865 7866 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 7867 7868 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 7869 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 7870 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 7871 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 7872 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 7873 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 7874 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 7875 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 7876 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 7877 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 7878 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 7879 do {\ 7880 HWIO_INTLOCK(); \ 7881 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 7882 HWIO_INTFREE();\ 7883 } while (0) 7884 7885 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 7886 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 7887 7888 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 7889 7890 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 7891 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 7892 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff 7893 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 7894 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 7895 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 7896 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 7897 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 7898 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 7899 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 7900 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 7901 do {\ 7902 HWIO_INTLOCK(); \ 7903 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 7904 HWIO_INTFREE();\ 7905 } while (0) 7906 7907 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00 7908 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa 7909 7910 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff 7911 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 7912 7913 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 //// 7914 7915 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024) 7916 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024) 7917 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff 7918 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0 7919 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ 7920 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK) 7921 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ 7922 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) 7923 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \ 7924 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val) 7925 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ 7926 do {\ 7927 HWIO_INTLOCK(); \ 7928 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \ 7929 HWIO_INTFREE();\ 7930 } while (0) 7931 7932 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00 7933 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa 7934 7935 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff 7936 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0 7937 7938 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 //// 7939 7940 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028) 7941 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028) 7942 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff 7943 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0 7944 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ 7945 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK) 7946 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ 7947 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) 7948 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \ 7949 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val) 7950 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ 7951 do {\ 7952 HWIO_INTLOCK(); \ 7953 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \ 7954 HWIO_INTFREE();\ 7955 } while (0) 7956 7957 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00 7958 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa 7959 7960 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff 7961 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0 7962 7963 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 //// 7964 7965 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c) 7966 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c) 7967 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff 7968 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0 7969 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ 7970 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK) 7971 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ 7972 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) 7973 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \ 7974 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val) 7975 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ 7976 do {\ 7977 HWIO_INTLOCK(); \ 7978 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \ 7979 HWIO_INTFREE();\ 7980 } while (0) 7981 7982 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00 7983 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa 7984 7985 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff 7986 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0 7987 7988 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW //// 7989 7990 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030) 7991 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030) 7992 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff 7993 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0 7994 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ 7995 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK) 7996 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ 7997 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) 7998 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \ 7999 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val) 8000 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ 8001 do {\ 8002 HWIO_INTLOCK(); \ 8003 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \ 8004 HWIO_INTFREE();\ 8005 } while (0) 8006 8007 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff 8008 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0 8009 8010 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH //// 8011 8012 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034) 8013 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034) 8014 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff 8015 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0 8016 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ 8017 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK) 8018 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ 8019 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) 8020 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \ 8021 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val) 8022 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ 8023 do {\ 8024 HWIO_INTLOCK(); \ 8025 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \ 8026 HWIO_INTFREE();\ 8027 } while (0) 8028 8029 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff 8030 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0 8031 8032 //// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER //// 8033 8034 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038) 8035 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038) 8036 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff 8037 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0 8038 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ 8039 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK) 8040 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ 8041 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 8042 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \ 8043 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val) 8044 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ 8045 do {\ 8046 HWIO_INTLOCK(); \ 8047 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \ 8048 HWIO_INTFREE();\ 8049 } while (0) 8050 8051 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00 8052 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa 8053 8054 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff 8055 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0 8056 8057 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 8058 8059 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c) 8060 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c) 8061 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 8062 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 8063 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 8064 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 8065 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 8066 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 8067 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 8068 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 8069 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8070 do {\ 8071 HWIO_INTLOCK(); \ 8072 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 8073 HWIO_INTFREE();\ 8074 } while (0) 8075 8076 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8077 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8078 8079 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 //// 8080 8081 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) (x+0x00002040) 8082 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) (x+0x00002040) 8083 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x000007ff 8084 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT 0 8085 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ 8086 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK) 8087 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \ 8088 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask) 8089 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val) \ 8090 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val) 8091 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \ 8092 do {\ 8093 HWIO_INTLOCK(); \ 8094 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \ 8095 HWIO_INTFREE();\ 8096 } while (0) 8097 8098 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x000007f8 8099 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 0x3 8100 8101 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004 8102 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 0x2 8103 8104 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002 8105 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 0x1 8106 8107 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x00000001 8108 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0x0 8109 8110 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 //// 8111 8112 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) (x+0x00002044) 8113 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) (x+0x00002044) 8114 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff 8115 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT 0 8116 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ 8117 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK) 8118 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \ 8119 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask) 8120 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val) \ 8121 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val) 8122 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \ 8123 do {\ 8124 HWIO_INTLOCK(); \ 8125 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \ 8126 HWIO_INTFREE();\ 8127 } while (0) 8128 8129 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff 8130 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0x0 8131 8132 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 //// 8133 8134 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) (x+0x00002048) 8135 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) (x+0x00002048) 8136 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0x000000ff 8137 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT 0 8138 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ 8139 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK) 8140 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \ 8141 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask) 8142 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val) \ 8143 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val) 8144 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \ 8145 do {\ 8146 HWIO_INTLOCK(); \ 8147 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \ 8148 HWIO_INTFREE();\ 8149 } while (0) 8150 8151 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff 8152 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0x0 8153 8154 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS //// 8155 8156 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) (x+0x0000204c) 8157 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) (x+0x0000204c) 8158 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff 8159 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT 0 8160 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ 8161 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK) 8162 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \ 8163 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask) 8164 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val) \ 8165 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val) 8166 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \ 8167 do {\ 8168 HWIO_INTLOCK(); \ 8169 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \ 8170 HWIO_INTFREE();\ 8171 } while (0) 8172 8173 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 8174 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 0x16 8175 8176 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x003ff000 8177 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 0xc 8178 8179 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800 8180 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 0xb 8181 8182 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600 8183 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 0x9 8184 8185 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0 8186 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 0x5 8187 8188 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c 8189 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 0x2 8190 8191 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002 8192 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 0x1 8193 8194 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x00000001 8195 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0x0 8196 8197 //// Register REO_R1_END_OF_TEST_CHECK //// 8198 8199 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002050) 8200 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002050) 8201 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 8202 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 8203 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 8204 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 8205 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 8206 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 8207 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 8208 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 8209 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 8210 do {\ 8211 HWIO_INTLOCK(); \ 8212 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 8213 HWIO_INTFREE();\ 8214 } while (0) 8215 8216 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 8217 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 8218 8219 //// Register REO_R1_SM_ALL_IDLE //// 8220 8221 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002054) 8222 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002054) 8223 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 8224 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 8225 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 8226 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 8227 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 8228 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 8229 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 8230 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 8231 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 8232 do {\ 8233 HWIO_INTLOCK(); \ 8234 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 8235 HWIO_INTFREE();\ 8236 } while (0) 8237 8238 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 8239 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 8240 8241 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 8242 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 8243 8244 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 8245 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 8246 8247 //// Register REO_R1_TESTBUS_CTRL //// 8248 8249 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002058) 8250 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002058) 8251 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 8252 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 8253 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 8254 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 8255 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 8256 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 8257 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 8258 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 8259 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 8260 do {\ 8261 HWIO_INTLOCK(); \ 8262 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 8263 HWIO_INTFREE();\ 8264 } while (0) 8265 8266 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 8267 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 8268 8269 //// Register REO_R1_TESTBUS_LOWER //// 8270 8271 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000205c) 8272 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000205c) 8273 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 8274 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 8275 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 8276 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 8277 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 8278 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 8279 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 8280 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 8281 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 8282 do {\ 8283 HWIO_INTLOCK(); \ 8284 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 8285 HWIO_INTFREE();\ 8286 } while (0) 8287 8288 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 8289 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 8290 8291 //// Register REO_R1_TESTBUS_HIGHER //// 8292 8293 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002060) 8294 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002060) 8295 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 8296 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 8297 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 8298 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 8299 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 8300 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 8301 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 8302 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 8303 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 8304 do {\ 8305 HWIO_INTLOCK(); \ 8306 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 8307 HWIO_INTFREE();\ 8308 } while (0) 8309 8310 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 8311 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 8312 8313 //// Register REO_R1_SM_STATES_IX_0 //// 8314 8315 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002064) 8316 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002064) 8317 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 8318 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 8319 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 8320 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 8321 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 8322 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 8323 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 8324 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 8325 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 8326 do {\ 8327 HWIO_INTLOCK(); \ 8328 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 8329 HWIO_INTFREE();\ 8330 } while (0) 8331 8332 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 8333 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 8334 8335 //// Register REO_R1_SM_STATES_IX_1 //// 8336 8337 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002068) 8338 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002068) 8339 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 8340 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 8341 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 8342 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 8343 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 8344 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 8345 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 8346 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 8347 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 8348 do {\ 8349 HWIO_INTLOCK(); \ 8350 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 8351 HWIO_INTFREE();\ 8352 } while (0) 8353 8354 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 8355 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 8356 8357 //// Register REO_R1_SM_STATES_IX_2 //// 8358 8359 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000206c) 8360 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000206c) 8361 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 8362 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 8363 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 8364 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 8365 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 8366 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 8367 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 8368 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 8369 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 8370 do {\ 8371 HWIO_INTLOCK(); \ 8372 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 8373 HWIO_INTFREE();\ 8374 } while (0) 8375 8376 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 8377 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 8378 8379 //// Register REO_R1_SM_STATES_IX_3 //// 8380 8381 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002070) 8382 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002070) 8383 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 8384 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 8385 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 8386 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 8387 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 8388 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 8389 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 8390 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 8391 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 8392 do {\ 8393 HWIO_INTLOCK(); \ 8394 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 8395 HWIO_INTFREE();\ 8396 } while (0) 8397 8398 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 8399 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 8400 8401 //// Register REO_R1_SM_STATES_IX_4 //// 8402 8403 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002074) 8404 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002074) 8405 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 8406 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 8407 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 8408 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 8409 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 8410 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 8411 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 8412 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 8413 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 8414 do {\ 8415 HWIO_INTLOCK(); \ 8416 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 8417 HWIO_INTFREE();\ 8418 } while (0) 8419 8420 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 8421 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 8422 8423 //// Register REO_R1_SM_STATES_IX_5 //// 8424 8425 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002078) 8426 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002078) 8427 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 8428 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 8429 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 8430 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 8431 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 8432 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 8433 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 8434 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 8435 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 8436 do {\ 8437 HWIO_INTLOCK(); \ 8438 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 8439 HWIO_INTFREE();\ 8440 } while (0) 8441 8442 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 8443 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 8444 8445 //// Register REO_R1_SM_STATES_IX_6 //// 8446 8447 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000207c) 8448 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000207c) 8449 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 8450 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 8451 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 8452 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 8453 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 8454 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 8455 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 8456 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 8457 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 8458 do {\ 8459 HWIO_INTLOCK(); \ 8460 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 8461 HWIO_INTFREE();\ 8462 } while (0) 8463 8464 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 8465 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 8466 8467 //// Register REO_R1_IDLE_STATES_IX_0 //// 8468 8469 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002080) 8470 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002080) 8471 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 8472 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 8473 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 8474 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 8475 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 8476 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 8477 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 8478 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 8479 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 8480 do {\ 8481 HWIO_INTLOCK(); \ 8482 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 8483 HWIO_INTFREE();\ 8484 } while (0) 8485 8486 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 8487 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 8488 8489 //// Register REO_R1_INVALID_APB_ACCESS //// 8490 8491 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002084) 8492 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002084) 8493 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 8494 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 8495 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 8496 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 8497 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 8498 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 8499 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 8500 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 8501 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 8502 do {\ 8503 HWIO_INTLOCK(); \ 8504 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 8505 HWIO_INTFREE();\ 8506 } while (0) 8507 8508 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 8509 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 8510 8511 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 8512 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 8513 8514 //// Register REO_R2_RXDMA2REO0_RING_HP //// 8515 8516 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 8517 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 8518 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 8519 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 8520 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 8521 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 8522 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 8523 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 8524 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 8525 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 8526 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 8527 do {\ 8528 HWIO_INTLOCK(); \ 8529 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 8530 HWIO_INTFREE();\ 8531 } while (0) 8532 8533 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8534 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 8535 8536 //// Register REO_R2_RXDMA2REO0_RING_TP //// 8537 8538 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 8539 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 8540 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 8541 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 8542 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 8543 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 8544 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 8545 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 8546 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 8547 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 8548 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 8549 do {\ 8550 HWIO_INTLOCK(); \ 8551 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 8552 HWIO_INTFREE();\ 8553 } while (0) 8554 8555 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8556 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 8557 8558 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 8559 8560 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003008) 8561 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003008) 8562 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 8563 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 8564 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 8565 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 8566 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 8567 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 8568 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 8569 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 8570 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 8571 do {\ 8572 HWIO_INTLOCK(); \ 8573 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 8574 HWIO_INTFREE();\ 8575 } while (0) 8576 8577 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8578 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 8579 8580 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 8581 8582 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000300c) 8583 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000300c) 8584 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 8585 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 8586 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 8587 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 8588 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 8589 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 8590 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 8591 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 8592 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 8593 do {\ 8594 HWIO_INTLOCK(); \ 8595 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 8596 HWIO_INTFREE();\ 8597 } while (0) 8598 8599 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8600 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 8601 8602 //// Register REO_R2_REO_CMD_RING_HP //// 8603 8604 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003010) 8605 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003010) 8606 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 8607 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 8608 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 8609 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 8610 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 8611 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 8612 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 8613 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 8614 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 8615 do {\ 8616 HWIO_INTLOCK(); \ 8617 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 8618 HWIO_INTFREE();\ 8619 } while (0) 8620 8621 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8622 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 8623 8624 //// Register REO_R2_REO_CMD_RING_TP //// 8625 8626 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003014) 8627 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003014) 8628 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 8629 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 8630 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 8631 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 8632 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 8633 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 8634 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 8635 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 8636 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 8637 do {\ 8638 HWIO_INTLOCK(); \ 8639 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 8640 HWIO_INTFREE();\ 8641 } while (0) 8642 8643 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8644 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 8645 8646 //// Register REO_R2_SW2REO_RING_HP //// 8647 8648 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003018) 8649 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003018) 8650 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 8651 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 8652 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 8653 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 8654 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 8655 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 8656 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 8657 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 8658 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 8659 do {\ 8660 HWIO_INTLOCK(); \ 8661 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 8662 HWIO_INTFREE();\ 8663 } while (0) 8664 8665 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8666 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 8667 8668 //// Register REO_R2_SW2REO_RING_TP //// 8669 8670 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000301c) 8671 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000301c) 8672 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 8673 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 8674 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 8675 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 8676 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 8677 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 8678 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 8679 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 8680 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 8681 do {\ 8682 HWIO_INTLOCK(); \ 8683 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 8684 HWIO_INTFREE();\ 8685 } while (0) 8686 8687 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8688 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 8689 8690 //// Register REO_R2_SW2REO1_RING_HP //// 8691 8692 #define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003020) 8693 #define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003020) 8694 #define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff 8695 #define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0 8696 #define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ 8697 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK) 8698 #define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ 8699 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) 8700 #define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \ 8701 out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val) 8702 #define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ 8703 do {\ 8704 HWIO_INTLOCK(); \ 8705 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \ 8706 HWIO_INTFREE();\ 8707 } while (0) 8708 8709 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8710 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0 8711 8712 //// Register REO_R2_SW2REO1_RING_TP //// 8713 8714 #define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003024) 8715 #define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003024) 8716 #define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff 8717 #define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0 8718 #define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ 8719 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK) 8720 #define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ 8721 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) 8722 #define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \ 8723 out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val) 8724 #define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ 8725 do {\ 8726 HWIO_INTLOCK(); \ 8727 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \ 8728 HWIO_INTFREE();\ 8729 } while (0) 8730 8731 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8732 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0 8733 8734 //// Register REO_R2_REO2SW1_RING_HP //// 8735 8736 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003028) 8737 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003028) 8738 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff 8739 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 8740 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 8741 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 8742 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 8743 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 8744 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 8745 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 8746 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 8747 do {\ 8748 HWIO_INTLOCK(); \ 8749 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 8750 HWIO_INTFREE();\ 8751 } while (0) 8752 8753 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff 8754 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 8755 8756 //// Register REO_R2_REO2SW1_RING_TP //// 8757 8758 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000302c) 8759 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000302c) 8760 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff 8761 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 8762 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 8763 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 8764 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 8765 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 8766 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 8767 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 8768 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 8769 do {\ 8770 HWIO_INTLOCK(); \ 8771 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 8772 HWIO_INTFREE();\ 8773 } while (0) 8774 8775 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff 8776 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 8777 8778 //// Register REO_R2_REO2SW2_RING_HP //// 8779 8780 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003030) 8781 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003030) 8782 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff 8783 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 8784 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 8785 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 8786 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 8787 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 8788 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 8789 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 8790 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 8791 do {\ 8792 HWIO_INTLOCK(); \ 8793 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 8794 HWIO_INTFREE();\ 8795 } while (0) 8796 8797 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff 8798 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 8799 8800 //// Register REO_R2_REO2SW2_RING_TP //// 8801 8802 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003034) 8803 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003034) 8804 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff 8805 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 8806 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 8807 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 8808 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 8809 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 8810 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 8811 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 8812 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 8813 do {\ 8814 HWIO_INTLOCK(); \ 8815 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 8816 HWIO_INTFREE();\ 8817 } while (0) 8818 8819 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff 8820 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 8821 8822 //// Register REO_R2_REO2SW3_RING_HP //// 8823 8824 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003038) 8825 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003038) 8826 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff 8827 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 8828 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 8829 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 8830 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 8831 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 8832 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 8833 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 8834 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 8835 do {\ 8836 HWIO_INTLOCK(); \ 8837 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 8838 HWIO_INTFREE();\ 8839 } while (0) 8840 8841 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff 8842 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 8843 8844 //// Register REO_R2_REO2SW3_RING_TP //// 8845 8846 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000303c) 8847 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000303c) 8848 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff 8849 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 8850 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 8851 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 8852 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 8853 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 8854 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 8855 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 8856 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 8857 do {\ 8858 HWIO_INTLOCK(); \ 8859 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 8860 HWIO_INTFREE();\ 8861 } while (0) 8862 8863 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff 8864 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 8865 8866 //// Register REO_R2_REO2SW4_RING_HP //// 8867 8868 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003040) 8869 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003040) 8870 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff 8871 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 8872 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 8873 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 8874 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 8875 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 8876 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 8877 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 8878 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 8879 do {\ 8880 HWIO_INTLOCK(); \ 8881 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 8882 HWIO_INTFREE();\ 8883 } while (0) 8884 8885 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff 8886 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 8887 8888 //// Register REO_R2_REO2SW4_RING_TP //// 8889 8890 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003044) 8891 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003044) 8892 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff 8893 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 8894 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 8895 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 8896 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 8897 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 8898 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 8899 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 8900 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 8901 do {\ 8902 HWIO_INTLOCK(); \ 8903 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 8904 HWIO_INTFREE();\ 8905 } while (0) 8906 8907 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff 8908 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 8909 8910 //// Register REO_R2_REO2TCL_RING_HP //// 8911 8912 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058) 8913 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058) 8914 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff 8915 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 8916 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 8917 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 8918 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 8919 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 8920 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 8921 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 8922 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 8923 do {\ 8924 HWIO_INTLOCK(); \ 8925 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 8926 HWIO_INTFREE();\ 8927 } while (0) 8928 8929 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff 8930 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 8931 8932 //// Register REO_R2_REO2TCL_RING_TP //// 8933 8934 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c) 8935 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c) 8936 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff 8937 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 8938 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 8939 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 8940 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 8941 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 8942 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 8943 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 8944 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 8945 do {\ 8946 HWIO_INTLOCK(); \ 8947 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 8948 HWIO_INTFREE();\ 8949 } while (0) 8950 8951 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff 8952 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 8953 8954 //// Register REO_R2_REO2FW_RING_HP //// 8955 8956 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060) 8957 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060) 8958 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff 8959 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 8960 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 8961 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 8962 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 8963 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 8964 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 8965 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 8966 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 8967 do {\ 8968 HWIO_INTLOCK(); \ 8969 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 8970 HWIO_INTFREE();\ 8971 } while (0) 8972 8973 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff 8974 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 8975 8976 //// Register REO_R2_REO2FW_RING_TP //// 8977 8978 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064) 8979 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064) 8980 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff 8981 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 8982 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 8983 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 8984 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 8985 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 8986 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 8987 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 8988 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 8989 do {\ 8990 HWIO_INTLOCK(); \ 8991 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 8992 HWIO_INTFREE();\ 8993 } while (0) 8994 8995 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff 8996 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 8997 8998 //// Register REO_R2_REO_RELEASE_RING_HP //// 8999 9000 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068) 9001 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068) 9002 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 9003 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 9004 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 9005 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 9006 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 9007 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 9008 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 9009 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 9010 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 9011 do {\ 9012 HWIO_INTLOCK(); \ 9013 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 9014 HWIO_INTFREE();\ 9015 } while (0) 9016 9017 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9018 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 9019 9020 //// Register REO_R2_REO_RELEASE_RING_TP //// 9021 9022 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c) 9023 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c) 9024 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 9025 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 9026 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 9027 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 9028 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 9029 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 9030 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 9031 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 9032 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 9033 do {\ 9034 HWIO_INTLOCK(); \ 9035 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 9036 HWIO_INTFREE();\ 9037 } while (0) 9038 9039 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9040 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 9041 9042 //// Register REO_R2_REO_STATUS_RING_HP //// 9043 9044 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070) 9045 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070) 9046 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 9047 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 9048 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 9049 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 9050 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 9051 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 9052 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 9053 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 9054 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 9055 do {\ 9056 HWIO_INTLOCK(); \ 9057 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 9058 HWIO_INTFREE();\ 9059 } while (0) 9060 9061 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9062 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 9063 9064 //// Register REO_R2_REO_STATUS_RING_TP //// 9065 9066 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074) 9067 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074) 9068 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 9069 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 9070 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 9071 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 9072 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 9073 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 9074 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 9075 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 9076 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 9077 do {\ 9078 HWIO_INTLOCK(); \ 9079 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 9080 HWIO_INTFREE();\ 9081 } while (0) 9082 9083 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9084 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 9085 9086 9087 #endif 9088 9089