1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_MPDU_INFO_H_ 19 #define _RX_MPDU_INFO_H_ 20 21 #include "rxpt_classify_info.h" 22 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 23 24 struct rx_mpdu_info { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct rxpt_classify_info rxpt_classify_info_details; 27 uint32_t epd_en : 1, 28 all_frames_shall_be_encrypted : 1, 29 encrypt_type : 4, 30 wep_key_width_for_variable_key : 2, 31 __reserved_g_0003 : 2, 32 bssid_hit : 1, 33 bssid_number : 4, 34 tid : 4, 35 reserved_7a : 13; 36 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 37 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 38 receive_queue_number : 16, 39 pre_delim_err_warning : 1, 40 first_delim_err : 1, 41 reserved_2a : 6; 42 uint32_t pn_31_0 : 32; 43 uint32_t pn_63_32 : 32; 44 uint32_t pn_95_64 : 32; 45 uint32_t pn_127_96 : 32; 46 uint32_t mpdu_frame_control_valid : 1, 47 mpdu_duration_valid : 1, 48 mac_addr_ad1_valid : 1, 49 mac_addr_ad2_valid : 1, 50 mac_addr_ad3_valid : 1, 51 mac_addr_ad4_valid : 1, 52 mpdu_sequence_control_valid : 1, 53 mpdu_qos_control_valid : 1, 54 mpdu_ht_control_valid : 1, 55 frame_encryption_info_valid : 1, 56 mpdu_fragment_number : 4, 57 more_fragment_flag : 1, 58 reserved_11a : 1, 59 fr_ds : 1, 60 to_ds : 1, 61 encrypted : 1, 62 mpdu_retry : 1, 63 mpdu_sequence_number : 12; 64 uint32_t peer_meta_data : 32; 65 uint32_t ast_index : 16, 66 sw_peer_id : 16; 67 uint32_t rxpcu_mpdu_filter_in_category : 2, 68 sw_frame_group_id : 7, 69 ndp_frame : 1, 70 phy_err : 1, 71 phy_err_during_mpdu_header : 1, 72 protocol_version_err : 1, 73 ast_based_lookup_valid : 1, 74 __reserved_g_0005 : 1, 75 reserved_9a : 1, 76 phy_ppdu_id : 16; 77 uint32_t key_id_octet : 8, 78 new_peer_entry : 1, 79 decrypt_needed : 1, 80 decap_type : 2, 81 rx_insert_vlan_c_tag_padding : 1, 82 rx_insert_vlan_s_tag_padding : 1, 83 strip_vlan_c_tag_decap : 1, 84 strip_vlan_s_tag_decap : 1, 85 pre_delim_count : 12, 86 ampdu_flag : 1, 87 bar_frame : 1, 88 raw_mpdu : 1, 89 reserved_12 : 1; 90 uint32_t mpdu_length : 14, 91 first_mpdu : 1, 92 mcast_bcast : 1, 93 ast_index_not_found : 1, 94 ast_index_timeout : 1, 95 power_mgmt : 1, 96 non_qos : 1, 97 null_data : 1, 98 mgmt_type : 1, 99 ctrl_type : 1, 100 more_data : 1, 101 eosp : 1, 102 fragment_flag : 1, 103 order : 1, 104 u_apsd_trigger : 1, 105 encrypt_required : 1, 106 directed : 1, 107 amsdu_present : 1, 108 reserved_13 : 1; 109 uint32_t mpdu_frame_control_field : 16, 110 mpdu_duration_field : 16; 111 uint32_t mac_addr_ad1_31_0 : 32; 112 uint32_t mac_addr_ad1_47_32 : 16, 113 mac_addr_ad2_15_0 : 16; 114 uint32_t mac_addr_ad2_47_16 : 32; 115 uint32_t mac_addr_ad3_31_0 : 32; 116 uint32_t mac_addr_ad3_47_32 : 16, 117 mpdu_sequence_control_field : 16; 118 uint32_t mac_addr_ad4_31_0 : 32; 119 uint32_t mac_addr_ad4_47_32 : 16, 120 mpdu_qos_control_field : 16; 121 uint32_t mpdu_ht_control_field : 32; 122 uint32_t vdev_id : 8, 123 service_code : 9, 124 priority_valid : 1, 125 src_info : 12, 126 reserved_23a : 1, 127 __reserved_g_0006 : 1; 128 uint32_t __reserved_g_0007 : 32; 129 uint32_t __reserved_g_0008 : 16, 130 __reserved_g_0009 : 16; 131 uint32_t __reserved_g_0010 : 32; 132 uint32_t authorized_to_send_wds : 1, 133 reserved_27a : 31; 134 uint32_t reserved_28a : 32; 135 uint32_t reserved_29a : 32; 136 #else 137 struct rxpt_classify_info rxpt_classify_info_details; 138 uint32_t reserved_7a : 13, 139 tid : 4, 140 bssid_number : 4, 141 bssid_hit : 1, 142 __reserved_g_0003 : 2, 143 wep_key_width_for_variable_key : 2, 144 encrypt_type : 4, 145 all_frames_shall_be_encrypted : 1, 146 epd_en : 1; 147 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 148 uint32_t reserved_2a : 6, 149 first_delim_err : 1, 150 pre_delim_err_warning : 1, 151 receive_queue_number : 16, 152 rx_reo_queue_desc_addr_39_32 : 8; 153 uint32_t pn_31_0 : 32; 154 uint32_t pn_63_32 : 32; 155 uint32_t pn_95_64 : 32; 156 uint32_t pn_127_96 : 32; 157 uint32_t mpdu_sequence_number : 12, 158 mpdu_retry : 1, 159 encrypted : 1, 160 to_ds : 1, 161 fr_ds : 1, 162 reserved_11a : 1, 163 more_fragment_flag : 1, 164 mpdu_fragment_number : 4, 165 frame_encryption_info_valid : 1, 166 mpdu_ht_control_valid : 1, 167 mpdu_qos_control_valid : 1, 168 mpdu_sequence_control_valid : 1, 169 mac_addr_ad4_valid : 1, 170 mac_addr_ad3_valid : 1, 171 mac_addr_ad2_valid : 1, 172 mac_addr_ad1_valid : 1, 173 mpdu_duration_valid : 1, 174 mpdu_frame_control_valid : 1; 175 uint32_t peer_meta_data : 32; 176 uint32_t sw_peer_id : 16, 177 ast_index : 16; 178 uint32_t phy_ppdu_id : 16, 179 reserved_9a : 1, 180 __reserved_g_0005 : 1, 181 ast_based_lookup_valid : 1, 182 protocol_version_err : 1, 183 phy_err_during_mpdu_header : 1, 184 phy_err : 1, 185 ndp_frame : 1, 186 sw_frame_group_id : 7, 187 rxpcu_mpdu_filter_in_category : 2; 188 uint32_t reserved_12 : 1, 189 raw_mpdu : 1, 190 bar_frame : 1, 191 ampdu_flag : 1, 192 pre_delim_count : 12, 193 strip_vlan_s_tag_decap : 1, 194 strip_vlan_c_tag_decap : 1, 195 rx_insert_vlan_s_tag_padding : 1, 196 rx_insert_vlan_c_tag_padding : 1, 197 decap_type : 2, 198 decrypt_needed : 1, 199 new_peer_entry : 1, 200 key_id_octet : 8; 201 uint32_t reserved_13 : 1, 202 amsdu_present : 1, 203 directed : 1, 204 encrypt_required : 1, 205 u_apsd_trigger : 1, 206 order : 1, 207 fragment_flag : 1, 208 eosp : 1, 209 more_data : 1, 210 ctrl_type : 1, 211 mgmt_type : 1, 212 null_data : 1, 213 non_qos : 1, 214 power_mgmt : 1, 215 ast_index_timeout : 1, 216 ast_index_not_found : 1, 217 mcast_bcast : 1, 218 first_mpdu : 1, 219 mpdu_length : 14; 220 uint32_t mpdu_duration_field : 16, 221 mpdu_frame_control_field : 16; 222 uint32_t mac_addr_ad1_31_0 : 32; 223 uint32_t mac_addr_ad2_15_0 : 16, 224 mac_addr_ad1_47_32 : 16; 225 uint32_t mac_addr_ad2_47_16 : 32; 226 uint32_t mac_addr_ad3_31_0 : 32; 227 uint32_t mpdu_sequence_control_field : 16, 228 mac_addr_ad3_47_32 : 16; 229 uint32_t mac_addr_ad4_31_0 : 32; 230 uint32_t mpdu_qos_control_field : 16, 231 mac_addr_ad4_47_32 : 16; 232 uint32_t mpdu_ht_control_field : 32; 233 uint32_t __reserved_g_0006 : 1, 234 reserved_23a : 1, 235 src_info : 12, 236 priority_valid : 1, 237 service_code : 9, 238 vdev_id : 8; 239 uint32_t __reserved_g_0007 : 32; 240 uint32_t __reserved_g_0009 : 16, 241 __reserved_g_0008 : 16; 242 uint32_t __reserved_g_0010 : 32; 243 uint32_t reserved_27a : 31, 244 authorized_to_send_wds : 1; 245 uint32_t reserved_28a : 32; 246 uint32_t reserved_29a : 32; 247 #endif 248 }; 249 250 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 251 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 252 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 253 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 254 255 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 256 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 257 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 258 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 259 260 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 261 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 262 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 263 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 264 265 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 266 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 267 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 268 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 269 270 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 271 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 272 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 273 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 274 275 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 276 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 277 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 278 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 279 280 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 281 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 282 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 283 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 284 285 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 286 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 287 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 288 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 289 290 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 291 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 292 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 293 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 294 295 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 296 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 297 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 298 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 299 300 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 301 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 302 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 303 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 304 305 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 306 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 307 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 308 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 309 310 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 311 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 312 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 313 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 314 315 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 316 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 317 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 318 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 319 320 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 321 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 322 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 323 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 324 325 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 326 #define RX_MPDU_INFO_EPD_EN_LSB 0 327 #define RX_MPDU_INFO_EPD_EN_MSB 0 328 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 329 330 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 331 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 332 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 333 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 334 335 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 336 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 337 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 338 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 339 340 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 341 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 342 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 343 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 344 345 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 346 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 347 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 348 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 349 350 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 351 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 352 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 353 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 354 355 #define RX_MPDU_INFO_TID_OFFSET 0x00000004 356 #define RX_MPDU_INFO_TID_LSB 15 357 #define RX_MPDU_INFO_TID_MSB 18 358 #define RX_MPDU_INFO_TID_MASK 0x00078000 359 360 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 361 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 362 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 363 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 364 365 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 366 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 367 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 368 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 369 370 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c 371 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 372 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 373 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 374 375 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 376 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 377 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 378 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 379 380 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c 381 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 382 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 383 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 384 385 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c 386 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 387 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 388 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 389 390 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c 391 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 392 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 393 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 394 395 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 396 #define RX_MPDU_INFO_PN_31_0_LSB 0 397 #define RX_MPDU_INFO_PN_31_0_MSB 31 398 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 399 400 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 401 #define RX_MPDU_INFO_PN_63_32_LSB 0 402 #define RX_MPDU_INFO_PN_63_32_MSB 31 403 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 404 405 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 406 #define RX_MPDU_INFO_PN_95_64_LSB 0 407 #define RX_MPDU_INFO_PN_95_64_MSB 31 408 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 409 410 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c 411 #define RX_MPDU_INFO_PN_127_96_LSB 0 412 #define RX_MPDU_INFO_PN_127_96_MSB 31 413 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 414 415 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 416 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 417 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 418 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 419 420 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 421 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 422 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 423 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 424 425 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 426 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 427 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 428 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 429 430 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 431 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 432 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 433 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 434 435 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 436 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 437 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 438 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 439 440 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 441 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 442 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 443 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 444 445 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 446 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 447 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 448 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 449 450 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 451 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 452 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 453 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 454 455 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 456 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 457 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 458 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 459 460 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 461 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 462 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 463 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 464 465 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 466 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 467 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 468 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 469 470 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 471 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 472 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 473 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 474 475 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 476 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 477 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 478 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 479 480 #define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 481 #define RX_MPDU_INFO_FR_DS_LSB 16 482 #define RX_MPDU_INFO_FR_DS_MSB 16 483 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 484 485 #define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 486 #define RX_MPDU_INFO_TO_DS_LSB 17 487 #define RX_MPDU_INFO_TO_DS_MSB 17 488 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 489 490 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 491 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 492 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 493 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 494 495 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 496 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 497 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 498 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 499 500 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 501 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 502 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 503 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 504 505 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 506 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 507 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 508 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 509 510 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 511 #define RX_MPDU_INFO_AST_INDEX_LSB 0 512 #define RX_MPDU_INFO_AST_INDEX_MSB 15 513 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 514 515 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 516 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 517 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 518 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 519 520 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c 521 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 522 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 523 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 524 525 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c 526 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 527 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 528 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 529 530 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c 531 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 532 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 533 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 534 535 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c 536 #define RX_MPDU_INFO_PHY_ERR_LSB 10 537 #define RX_MPDU_INFO_PHY_ERR_MSB 10 538 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 539 540 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c 541 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 542 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 543 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 544 545 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c 546 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 547 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 548 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 549 550 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c 551 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 552 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 553 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 554 555 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x0000002c 556 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 557 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 558 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 559 560 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c 561 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 562 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 563 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 564 565 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 566 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 567 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 568 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 569 570 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 571 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 572 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 573 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 574 575 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 576 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 577 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 578 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 579 580 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 581 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 582 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 583 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 584 585 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 586 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 587 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 588 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 589 590 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 591 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 592 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 593 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 594 595 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 596 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 597 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 598 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 599 600 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 601 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 602 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 603 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 604 605 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 606 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 607 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 608 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 609 610 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 611 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 612 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 613 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 614 615 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 616 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 617 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 618 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 619 620 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 621 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 622 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 623 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 624 625 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 626 #define RX_MPDU_INFO_RESERVED_12_LSB 31 627 #define RX_MPDU_INFO_RESERVED_12_MSB 31 628 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 629 630 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 631 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 632 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 633 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 634 635 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 636 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 637 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 638 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 639 640 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 641 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 642 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 643 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 644 645 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 646 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 647 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 648 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 649 650 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 651 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 652 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 653 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 654 655 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 656 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 657 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 658 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 659 660 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 661 #define RX_MPDU_INFO_NON_QOS_LSB 19 662 #define RX_MPDU_INFO_NON_QOS_MSB 19 663 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 664 665 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 666 #define RX_MPDU_INFO_NULL_DATA_LSB 20 667 #define RX_MPDU_INFO_NULL_DATA_MSB 20 668 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 669 670 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 671 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 672 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 673 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 674 675 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 676 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 677 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 678 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 679 680 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 681 #define RX_MPDU_INFO_MORE_DATA_LSB 23 682 #define RX_MPDU_INFO_MORE_DATA_MSB 23 683 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 684 685 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 686 #define RX_MPDU_INFO_EOSP_LSB 24 687 #define RX_MPDU_INFO_EOSP_MSB 24 688 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 689 690 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 691 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 692 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 693 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 694 695 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 696 #define RX_MPDU_INFO_ORDER_LSB 26 697 #define RX_MPDU_INFO_ORDER_MSB 26 698 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 699 700 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 701 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 702 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 703 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 704 705 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 706 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 707 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 708 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 709 710 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 711 #define RX_MPDU_INFO_DIRECTED_LSB 29 712 #define RX_MPDU_INFO_DIRECTED_MSB 29 713 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 714 715 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 716 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 717 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 718 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 719 720 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 721 #define RX_MPDU_INFO_RESERVED_13_LSB 31 722 #define RX_MPDU_INFO_RESERVED_13_MSB 31 723 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 724 725 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 726 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 727 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 728 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 729 730 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 731 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 732 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 733 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 734 735 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 736 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 737 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 738 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 739 740 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 741 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 742 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 743 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 744 745 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 746 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 747 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 748 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 749 750 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 751 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 752 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 753 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 754 755 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 756 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 757 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 758 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 759 760 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 761 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 762 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 763 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 764 765 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 766 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 767 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 768 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 769 770 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 771 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 772 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 773 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 774 775 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 776 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 777 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 778 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 779 780 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 781 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 782 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 783 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 784 785 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 786 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 787 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 788 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 789 790 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 791 #define RX_MPDU_INFO_VDEV_ID_LSB 0 792 #define RX_MPDU_INFO_VDEV_ID_MSB 7 793 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 794 795 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 796 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 797 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 798 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 799 800 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 801 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 802 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 803 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 804 805 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 806 #define RX_MPDU_INFO_SRC_INFO_LSB 18 807 #define RX_MPDU_INFO_SRC_INFO_MSB 29 808 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 809 810 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 811 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 812 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 813 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 814 815 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 816 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 817 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 818 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 819 820 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 821 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 822 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 823 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 824 825 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 826 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 827 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 828 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 829 830 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 831 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 832 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 833 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 834 835 #endif 836