1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
24 #define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 
29 // ################ START SUMMARY #################
30 //
31 //	Dword	Fields
32 //	0	filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], phyrx_abort_received[6], reserved_0[15:7], phy_ppdu_id[31:16]
33 //
34 // ################ END SUMMARY #################
35 
36 #define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
37 
38 struct rx_rxpcu_classification_overview {
39              uint32_t filter_pass_mpdus               :  1, //[0]
40                       filter_pass_mpdus_fcs_ok        :  1, //[1]
41                       monitor_direct_mpdus            :  1, //[2]
42                       monitor_direct_mpdus_fcs_ok     :  1, //[3]
43                       monitor_other_mpdus             :  1, //[4]
44                       monitor_other_mpdus_fcs_ok      :  1, //[5]
45                       phyrx_abort_received            :  1, //[6]
46                       reserved_0                      :  9, //[15:7]
47                       phy_ppdu_id                     : 16; //[31:16]
48 };
49 
50 /*
51 
52 filter_pass_mpdus
53 
54 			When set, at least one Filter Pass MPDU has been
55 			received. FCS might or might not have been passing.
56 
57 
58 
59 			For MU UL, in  TLVs RX_PPDU_END and
60 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
61 			users.
62 
63 			<legal all>
64 
65 filter_pass_mpdus_fcs_ok
66 
67 			When set, at least one Filter Pass MPDU has been
68 			received that has a correct FCS.
69 
70 
71 
72 			For MU UL, in  TLVs RX_PPDU_END and
73 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
74 			users.
75 
76 
77 
78 			<legal all>
79 
80 monitor_direct_mpdus
81 
82 			When set, at least one Monitor Direct MPDU has been
83 			received. FCS might or might not have been passing
84 
85 
86 
87 			For MU UL, in  TLVs RX_PPDU_END and
88 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
89 			users.
90 
91 			<legal all>
92 
93 monitor_direct_mpdus_fcs_ok
94 
95 			When set, at least one Monitor Direct MPDU has been
96 			received that has a correct FCS.
97 
98 
99 
100 			For MU UL, in  TLVs RX_PPDU_END and
101 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
102 			users.
103 
104 
105 
106 			<legal all>
107 
108 monitor_other_mpdus
109 
110 			When set, at least one Monitor Direct MPDU has been
111 			received. FCS might or might not have been passing.
112 
113 
114 
115 			For MU UL, in  TLVs RX_PPDU_END and
116 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
117 			users.
118 
119 			<legal all>
120 
121 monitor_other_mpdus_fcs_ok
122 
123 			When set, at least one Monitor Direct MPDU has been
124 			received that has a correct FCS.
125 
126 
127 
128 			For MU UL, in  TLVs RX_PPDU_END and
129 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
130 			users.
131 
132 			<legal all>
133 
134 phyrx_abort_received
135 
136 			When set, PPDU reception was aborted by the PHY
137 
138 			<legal all>
139 
140 reserved_0
141 
142 			<legal 0>
143 
144 phy_ppdu_id
145 
146 			A ppdu counter value that PHY increments for every PPDU
147 			received. The counter value wraps around
148 
149 			<legal all>
150 */
151 
152 
153 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS
154 
155 			When set, at least one Filter Pass MPDU has been
156 			received. FCS might or might not have been passing.
157 
158 
159 
160 			For MU UL, in  TLVs RX_PPDU_END and
161 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
162 			users.
163 
164 			<legal all>
165 */
166 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET  0x00000000
167 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB     0
168 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK    0x00000001
169 
170 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK
171 
172 			When set, at least one Filter Pass MPDU has been
173 			received that has a correct FCS.
174 
175 
176 
177 			For MU UL, in  TLVs RX_PPDU_END and
178 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
179 			users.
180 
181 
182 
183 			<legal all>
184 */
185 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
186 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
187 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
188 
189 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS
190 
191 			When set, at least one Monitor Direct MPDU has been
192 			received. FCS might or might not have been passing
193 
194 
195 
196 			For MU UL, in  TLVs RX_PPDU_END and
197 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
198 			users.
199 
200 			<legal all>
201 */
202 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
203 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB  2
204 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
205 
206 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK
207 
208 			When set, at least one Monitor Direct MPDU has been
209 			received that has a correct FCS.
210 
211 
212 
213 			For MU UL, in  TLVs RX_PPDU_END and
214 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
215 			users.
216 
217 
218 
219 			<legal all>
220 */
221 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
222 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
223 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
224 
225 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS
226 
227 			When set, at least one Monitor Direct MPDU has been
228 			received. FCS might or might not have been passing.
229 
230 
231 
232 			For MU UL, in  TLVs RX_PPDU_END and
233 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
234 			users.
235 
236 			<legal all>
237 */
238 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
239 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB   4
240 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK  0x00000010
241 
242 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK
243 
244 			When set, at least one Monitor Direct MPDU has been
245 			received that has a correct FCS.
246 
247 
248 
249 			For MU UL, in  TLVs RX_PPDU_END and
250 			RX_PPDU_END_STATUS_DONE, this field is the OR of all the
251 			users.
252 
253 			<legal all>
254 */
255 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
256 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
257 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
258 
259 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED
260 
261 			When set, PPDU reception was aborted by the PHY
262 
263 			<legal all>
264 */
265 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
266 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB  6
267 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040
268 
269 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0
270 
271 			<legal 0>
272 */
273 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET         0x00000000
274 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB            7
275 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK           0x0000ff80
276 
277 /* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID
278 
279 			A ppdu counter value that PHY increments for every PPDU
280 			received. The counter value wraps around
281 
282 			<legal all>
283 */
284 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET        0x00000000
285 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB           16
286 #define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK          0xffff0000
287 
288 
289 #endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
290