1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _RX_MSDU_LINK_H_
24 #define _RX_MSDU_LINK_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 #include "uniform_descriptor_header.h"
29 #include "buffer_addr_info.h"
30 #include "rx_msdu_details.h"
31 
32 // ################ START SUMMARY #################
33 //
34 //	Dword	Fields
35 //	0	struct uniform_descriptor_header descriptor_header;
36 //	1-2	struct buffer_addr_info next_msdu_link_desc_addr_info;
37 //	3	receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17]
38 //	4	pn_31_0[31:0]
39 //	5	pn_63_32[31:0]
40 //	6	pn_95_64[31:0]
41 //	7	pn_127_96[31:0]
42 //	8-11	struct rx_msdu_details msdu_0;
43 //	12-15	struct rx_msdu_details msdu_1;
44 //	16-19	struct rx_msdu_details msdu_2;
45 //	20-23	struct rx_msdu_details msdu_3;
46 //	24-27	struct rx_msdu_details msdu_4;
47 //	28-31	struct rx_msdu_details msdu_5;
48 //
49 // ################ END SUMMARY #################
50 
51 #define NUM_OF_DWORDS_RX_MSDU_LINK 32
52 
53 struct rx_msdu_link {
54     struct            uniform_descriptor_header                       descriptor_header;
55     struct            buffer_addr_info                       next_msdu_link_desc_addr_info;
56              uint32_t receive_queue_number            : 16, //[15:0]
57                       first_rx_msdu_link_struct       :  1, //[16]
58                       reserved_3a                     : 15; //[31:17]
59              uint32_t pn_31_0                         : 32; //[31:0]
60              uint32_t pn_63_32                        : 32; //[31:0]
61              uint32_t pn_95_64                        : 32; //[31:0]
62              uint32_t pn_127_96                       : 32; //[31:0]
63     struct            rx_msdu_details                       msdu_0;
64     struct            rx_msdu_details                       msdu_1;
65     struct            rx_msdu_details                       msdu_2;
66     struct            rx_msdu_details                       msdu_3;
67     struct            rx_msdu_details                       msdu_4;
68     struct            rx_msdu_details                       msdu_5;
69 };
70 
71 /*
72 
73 struct uniform_descriptor_header descriptor_header
74 
75 			Details about which module owns this struct.
76 
77 			Note that sub field Buffer_type shall be set to
78 			Receive_MSDU_Link_descriptor
79 
80 struct buffer_addr_info next_msdu_link_desc_addr_info
81 
82 			Details of the physical address of the next MSDU link
83 			descriptor that contains info about additional MSDUs that
84 			are part of this MPDU.
85 
86 receive_queue_number
87 
88 			Indicates the Receive queue to which this MPDU
89 			descriptor belongs
90 
91 			Used for tracking, finding bugs and debugging.
92 
93 			<legal all>
94 
95 first_rx_msdu_link_struct
96 
97 			When set, this RX_MSDU_link descriptor is the first one
98 			in the MSDU link list. Field MSDU_0 points to the very first
99 			MSDU buffer descriptor in the MPDU
100 
101 			<legal all>
102 
103 reserved_3a
104 
105 			<legal 0>
106 
107 pn_31_0
108 
109 
110 
111 
112 			31-0 bits of the 256-bit packet number bitmap.
113 
114 			<legal all>
115 
116 pn_63_32
117 
118 
119 
120 
121 			63-32 bits of the 256-bit packet number bitmap.
122 
123 			<legal all>
124 
125 pn_95_64
126 
127 
128 
129 
130 			95-64 bits of the 256-bit packet number bitmap.
131 
132 			<legal all>
133 
134 pn_127_96
135 
136 
137 
138 
139 			127-96 bits of the 256-bit packet number bitmap.
140 
141 			<legal all>
142 
143 struct rx_msdu_details msdu_0
144 
145 			When First_RX_MSDU_link_struct  is set, this MSDU is the
146 			first in the MPDU
147 
148 
149 
150 			When First_RX_MSDU_link_struct  is NOT set, this MSDU
151 			follows the last MSDU in the previous RX_MSDU_link data
152 			structure
153 
154 struct rx_msdu_details msdu_1
155 
156 			Details of next MSDU in this (MSDU flow) linked list
157 
158 struct rx_msdu_details msdu_2
159 
160 			Details of next MSDU in this (MSDU flow) linked list
161 
162 struct rx_msdu_details msdu_3
163 
164 			Details of next MSDU in this (MSDU flow) linked list
165 
166 struct rx_msdu_details msdu_4
167 
168 			Details of next MSDU in this (MSDU flow) linked list
169 
170 struct rx_msdu_details msdu_5
171 
172 			Details of next MSDU in this (MSDU flow) linked list
173 */
174 
175 
176  /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */
177 
178 
179 /* Description		RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER
180 
181 			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
182 
183 			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
184 
185 
186 
187 			The owner of this data structure:
188 
189 			<enum 0 WBM_owned> Buffer Manager currently owns this
190 			data structure.
191 
192 			<enum 1 SW_OR_FW_owned> Software of FW currently owns
193 			this data structure.
194 
195 			<enum 2 TQM_owned> Transmit Queue Manager currently owns
196 			this data structure.
197 
198 			<enum 3 RXDMA_owned> Receive DMA currently owns this
199 			data structure.
200 
201 			<enum 4 REO_owned> Reorder currently owns this data
202 			structure.
203 
204 			<enum 5 SWITCH_owned> SWITCH currently owns this data
205 			structure.
206 
207 
208 
209 			<legal 0-5>
210 */
211 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET                0x00000000
212 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB                   0
213 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK                  0x0000000f
214 
215 /* Description		RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE
216 
217 			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
218 
219 			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
220 
221 
222 
223 			Field describing what contents format is of this
224 			descriptor
225 
226 
227 
228 			<enum 0 Transmit_MSDU_Link_descriptor >
229 
230 			<enum 1 Transmit_MPDU_Link_descriptor >
231 
232 			<enum 2 Transmit_MPDU_Queue_head_descriptor>
233 
234 			<enum 3 Transmit_MPDU_Queue_ext_descriptor>
235 
236 			<enum 4 Transmit_flow_descriptor>
237 
238 			<enum 5 Transmit_buffer > NOT TO BE USED:
239 
240 
241 
242 			<enum 6 Receive_MSDU_Link_descriptor >
243 
244 			<enum 7 Receive_MPDU_Link_descriptor >
245 
246 			<enum 8 Receive_REO_queue_descriptor >
247 
248 			<enum 9 Receive_REO_queue_ext_descriptor >
249 
250 
251 
252 			<enum 10 Receive_buffer >
253 
254 
255 
256 			<enum 11 Idle_link_list_entry>
257 
258 
259 
260 			<legal 0-11>
261 */
262 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET          0x00000000
263 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB             4
264 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK            0x000000f0
265 
266 /* Description		RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A
267 
268 			<legal 0>
269 */
270 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET          0x00000000
271 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB             8
272 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK            0xffffff00
273 
274  /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */
275 
276 
277 /* Description		RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
278 
279 			Address (lower 32 bits) of the MSDU buffer OR
280 			MSDU_EXTENSION descriptor OR Link Descriptor
281 
282 
283 
284 			In case of 'NULL' pointer, this field is set to 0
285 
286 			<legal all>
287 */
288 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004
289 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
290 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
291 
292 /* Description		RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
293 
294 			Address (upper 8 bits) of the MSDU buffer OR
295 			MSDU_EXTENSION descriptor OR Link Descriptor
296 
297 
298 
299 			In case of 'NULL' pointer, this field is set to 0
300 
301 			<legal all>
302 */
303 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008
304 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
305 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
306 
307 /* Description		RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
308 
309 			Consumer: WBM
310 
311 			Producer: SW/FW
312 
313 
314 
315 			In case of 'NULL' pointer, this field is set to 0
316 
317 
318 
319 			Indicates to which buffer manager the buffer OR
320 			MSDU_EXTENSION descriptor OR link descriptor that is being
321 			pointed to shall be returned after the frame has been
322 			processed. It is used by WBM for routing purposes.
323 
324 
325 
326 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
327 			to the WMB buffer idle list
328 
329 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
330 			returned to the WMB idle link descriptor idle list
331 
332 			<enum 2 FW_BM> This buffer shall be returned to the FW
333 
334 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
335 			ring 0
336 
337 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
338 			ring 1
339 
340 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
341 			ring 2
342 
343 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
344 			ring 3
345 
346 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
347 			ring 3
348 
349 
350 
351 			<legal all>
352 */
353 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
354 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
355 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
356 
357 /* Description		RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
358 
359 			Cookie field exclusively used by SW.
360 
361 
362 
363 			In case of 'NULL' pointer, this field is set to 0
364 
365 
366 
367 			HW ignores the contents, accept that it passes the
368 			programmed value on to other descriptors together with the
369 			physical address
370 
371 
372 
373 			Field can be used by SW to for example associate the
374 			buffers physical address with the virtual address
375 
376 			The bit definitions as used by SW are within SW HLD
377 			specification
378 
379 
380 
381 			NOTE:
382 
383 			The three most significant bits can have a special
384 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
385 			STRUCT, and field transmit_bw_restriction is set
386 
387 
388 
389 			In case of NON punctured transmission:
390 
391 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
392 
393 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
394 
395 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
396 
397 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
398 
399 
400 
401 			In case of punctured transmission:
402 
403 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
404 
405 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
406 
407 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
408 
409 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
410 
411 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
412 
413 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
414 
415 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
416 
417 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
418 
419 
420 
421 			Note: a punctured transmission is indicated by the
422 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
423 			TLV
424 
425 
426 
427 			<legal all>
428 */
429 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008
430 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
431 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
432 
433 /* Description		RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER
434 
435 			Indicates the Receive queue to which this MPDU
436 			descriptor belongs
437 
438 			Used for tracking, finding bugs and debugging.
439 
440 			<legal all>
441 */
442 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET                   0x0000000c
443 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB                      0
444 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
445 
446 /* Description		RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT
447 
448 			When set, this RX_MSDU_link descriptor is the first one
449 			in the MSDU link list. Field MSDU_0 points to the very first
450 			MSDU buffer descriptor in the MPDU
451 
452 			<legal all>
453 */
454 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET              0x0000000c
455 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB                 16
456 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK                0x00010000
457 
458 /* Description		RX_MSDU_LINK_3_RESERVED_3A
459 
460 			<legal 0>
461 */
462 #define RX_MSDU_LINK_3_RESERVED_3A_OFFSET                            0x0000000c
463 #define RX_MSDU_LINK_3_RESERVED_3A_LSB                               17
464 #define RX_MSDU_LINK_3_RESERVED_3A_MASK                              0xfffe0000
465 
466 /* Description		RX_MSDU_LINK_4_PN_31_0
467 
468 
469 
470 
471 			31-0 bits of the 256-bit packet number bitmap.
472 
473 			<legal all>
474 */
475 #define RX_MSDU_LINK_4_PN_31_0_OFFSET                                0x00000010
476 #define RX_MSDU_LINK_4_PN_31_0_LSB                                   0
477 #define RX_MSDU_LINK_4_PN_31_0_MASK                                  0xffffffff
478 
479 /* Description		RX_MSDU_LINK_5_PN_63_32
480 
481 
482 
483 
484 			63-32 bits of the 256-bit packet number bitmap.
485 
486 			<legal all>
487 */
488 #define RX_MSDU_LINK_5_PN_63_32_OFFSET                               0x00000014
489 #define RX_MSDU_LINK_5_PN_63_32_LSB                                  0
490 #define RX_MSDU_LINK_5_PN_63_32_MASK                                 0xffffffff
491 
492 /* Description		RX_MSDU_LINK_6_PN_95_64
493 
494 
495 
496 
497 			95-64 bits of the 256-bit packet number bitmap.
498 
499 			<legal all>
500 */
501 #define RX_MSDU_LINK_6_PN_95_64_OFFSET                               0x00000018
502 #define RX_MSDU_LINK_6_PN_95_64_LSB                                  0
503 #define RX_MSDU_LINK_6_PN_95_64_MASK                                 0xffffffff
504 
505 /* Description		RX_MSDU_LINK_7_PN_127_96
506 
507 
508 
509 
510 			127-96 bits of the 256-bit packet number bitmap.
511 
512 			<legal all>
513 */
514 #define RX_MSDU_LINK_7_PN_127_96_OFFSET                              0x0000001c
515 #define RX_MSDU_LINK_7_PN_127_96_LSB                                 0
516 #define RX_MSDU_LINK_7_PN_127_96_MASK                                0xffffffff
517 
518  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */
519 
520 
521  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
522 
523 
524 /* Description		RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
525 
526 			Address (lower 32 bits) of the MSDU buffer OR
527 			MSDU_EXTENSION descriptor OR Link Descriptor
528 
529 
530 
531 			In case of 'NULL' pointer, this field is set to 0
532 
533 			<legal all>
534 */
535 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020
536 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
537 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
538 
539 /* Description		RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
540 
541 			Address (upper 8 bits) of the MSDU buffer OR
542 			MSDU_EXTENSION descriptor OR Link Descriptor
543 
544 
545 
546 			In case of 'NULL' pointer, this field is set to 0
547 
548 			<legal all>
549 */
550 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024
551 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
552 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
553 
554 /* Description		RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
555 
556 			Consumer: WBM
557 
558 			Producer: SW/FW
559 
560 
561 
562 			In case of 'NULL' pointer, this field is set to 0
563 
564 
565 
566 			Indicates to which buffer manager the buffer OR
567 			MSDU_EXTENSION descriptor OR link descriptor that is being
568 			pointed to shall be returned after the frame has been
569 			processed. It is used by WBM for routing purposes.
570 
571 
572 
573 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
574 			to the WMB buffer idle list
575 
576 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
577 			returned to the WMB idle link descriptor idle list
578 
579 			<enum 2 FW_BM> This buffer shall be returned to the FW
580 
581 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
582 			ring 0
583 
584 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
585 			ring 1
586 
587 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
588 			ring 2
589 
590 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
591 			ring 3
592 
593 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
594 			ring 3
595 
596 
597 
598 			<legal all>
599 */
600 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
601 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
602 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
603 
604 /* Description		RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
605 
606 			Cookie field exclusively used by SW.
607 
608 
609 
610 			In case of 'NULL' pointer, this field is set to 0
611 
612 
613 
614 			HW ignores the contents, accept that it passes the
615 			programmed value on to other descriptors together with the
616 			physical address
617 
618 
619 
620 			Field can be used by SW to for example associate the
621 			buffers physical address with the virtual address
622 
623 			The bit definitions as used by SW are within SW HLD
624 			specification
625 
626 
627 
628 			NOTE:
629 
630 			The three most significant bits can have a special
631 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
632 			STRUCT, and field transmit_bw_restriction is set
633 
634 
635 
636 			In case of NON punctured transmission:
637 
638 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
639 
640 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
641 
642 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
643 
644 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
645 
646 
647 
648 			In case of punctured transmission:
649 
650 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
651 
652 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
653 
654 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
655 
656 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
657 
658 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
659 
660 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
661 
662 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
663 
664 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
665 
666 
667 
668 			Note: a punctured transmission is indicated by the
669 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
670 			TLV
671 
672 
673 
674 			<legal all>
675 */
676 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024
677 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
678 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
679 
680  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
681 
682 
683 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
684 
685 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
686 			over multiple buffers, this field will be valid in the Last
687 			buffer used by the MSDU
688 
689 
690 
691 			<enum 0 Not_first_msdu> This is not the first MSDU in
692 			the MPDU.
693 
694 			<enum 1 first_msdu> This MSDU is the first one in the
695 			MPDU.
696 
697 
698 
699 			<legal all>
700 */
701 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
702 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
703 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
704 
705 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
706 
707 			Consumer: WBM/REO/SW/FW
708 
709 			Producer: RXDMA
710 
711 
712 
713 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
714 			over multiple buffers, this field will be valid in the Last
715 			buffer used by the MSDU
716 
717 
718 
719 			<enum 0 Not_last_msdu> There are more MSDUs linked to
720 			this MSDU that belongs to this MPDU
721 
722 			<enum 1 Last_msdu> this MSDU is the last one in the
723 			MPDU. This setting is only allowed in combination with
724 			'Msdu_continuation' set to 0. This implies that when an msdu
725 			is spread out over multiple buffers and thus
726 			msdu_continuation is set, only for the very last buffer of
727 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
728 
729 
730 
731 			When both first_msdu_in_mpdu_flag and
732 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
733 			belongs to only contains a single MSDU.
734 
735 
736 
737 
738 
739 			<legal all>
740 */
741 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
742 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
743 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
744 
745 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
746 
747 			When set, this MSDU buffer was not able to hold the
748 			entire MSDU. The next buffer will therefor contain
749 			additional information related to this MSDU.
750 
751 
752 
753 			<legal all>
754 */
755 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028
756 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
757 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
758 
759 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
760 
761 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
762 			over multiple buffers, this field will be valid in the First
763 			buffer used by MSDU.
764 
765 
766 
767 			Full MSDU length in bytes after decapsulation.
768 
769 
770 
771 			This field is still valid for MPDU frames without
772 			A-MSDU.  It still represents MSDU length after decapsulation
773 
774 
775 
776 			Or in case of RAW MPDUs, it indicates the length of the
777 			entire MPDU (without FCS field)
778 
779 			<legal all>
780 */
781 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028
782 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
783 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
784 
785 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
786 
787 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
788 			over multiple buffers, this field will be valid in the Last
789 			buffer used by the MSDU
790 
791 
792 
793 			The ID of the REO exit ring where the MSDU frame shall
794 			push after (MPDU level) reordering has finished.
795 
796 
797 
798 			<enum 0 reo_destination_tcl> Reo will push the frame
799 			into the REO2TCL ring
800 
801 			<enum 1 reo_destination_sw1> Reo will push the frame
802 			into the REO2SW1 ring
803 
804 			<enum 2 reo_destination_sw2> Reo will push the frame
805 			into the REO2SW1 ring
806 
807 			<enum 3 reo_destination_sw3> Reo will push the frame
808 			into the REO2SW1 ring
809 
810 			<enum 4 reo_destination_sw4> Reo will push the frame
811 			into the REO2SW1 ring
812 
813 			<enum 5 reo_destination_release> Reo will push the frame
814 			into the REO_release ring
815 
816 			<enum 6 reo_destination_fw> Reo will push the frame into
817 			the REO2FW ring
818 
819 			<enum 7 reo_destination_7> REO remaps this
820 
821 			<enum 8 reo_destination_8> REO remaps this <enum 9
822 			reo_destination_9> REO remaps this <enum 10
823 			reo_destination_10> REO remaps this
824 
825 			<enum 11 reo_destination_11> REO remaps this
826 
827 			<enum 12 reo_destination_12> REO remaps this <enum 13
828 			reo_destination_13> REO remaps this
829 
830 			<enum 14 reo_destination_14> REO remaps this
831 
832 			<enum 15 reo_destination_15> REO remaps this
833 
834 			<enum 16 reo_destination_16> REO remaps this
835 
836 			<enum 17 reo_destination_17> REO remaps this
837 
838 			<enum 18 reo_destination_18> REO remaps this
839 
840 			<enum 19 reo_destination_19> REO remaps this
841 
842 			<enum 20 reo_destination_20> REO remaps this
843 
844 			<enum 21 reo_destination_21> REO remaps this
845 
846 			<enum 22 reo_destination_22> REO remaps this
847 
848 			<enum 23 reo_destination_23> REO remaps this
849 
850 			<enum 24 reo_destination_24> REO remaps this
851 
852 			<enum 25 reo_destination_25> REO remaps this
853 
854 			<enum 26 reo_destination_26> REO remaps this
855 
856 			<enum 27 reo_destination_27> REO remaps this
857 
858 			<enum 28 reo_destination_28> REO remaps this
859 
860 			<enum 29 reo_destination_29> REO remaps this
861 
862 			<enum 30 reo_destination_30> REO remaps this
863 
864 			<enum 31 reo_destination_31> REO remaps this
865 
866 
867 
868 			<legal all>
869 */
870 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028
871 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
872 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
873 
874 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
875 
876 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
877 			over multiple buffers, this field will be valid in the Last
878 			buffer used by the MSDU
879 
880 
881 
882 			When set, REO shall drop this MSDU and not forward it to
883 			any other ring...
884 
885 			<legal all>
886 */
887 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028
888 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
889 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
890 
891 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
892 
893 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
894 			over multiple buffers, this field will be valid in the Last
895 			buffer used by the MSDU
896 
897 
898 
899 			Indicates that OLE found a valid SA entry for this MSDU
900 
901 			<legal all>
902 */
903 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028
904 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
905 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
906 
907 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
908 
909 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
910 			over multiple buffers, this field will be valid in the Last
911 			buffer used by the MSDU
912 
913 
914 
915 			Indicates an unsuccessful MAC source address search due
916 			to the expiring of the search timer for this MSDU
917 
918 			<legal all>
919 */
920 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028
921 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
922 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
923 
924 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
925 
926 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
927 			over multiple buffers, this field will be valid in the Last
928 			buffer used by the MSDU
929 
930 
931 
932 			Indicates that OLE found a valid DA entry for this MSDU
933 
934 			<legal all>
935 */
936 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028
937 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
938 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
939 
940 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
941 
942 			Field Only valid if da_is_valid is set
943 
944 
945 
946 			Indicates the DA address was a Multicast of Broadcast
947 			address for this MSDU
948 
949 			<legal all>
950 */
951 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028
952 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
953 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
954 
955 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
956 
957 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
958 			over multiple buffers, this field will be valid in the Last
959 			buffer used by the MSDU
960 
961 
962 
963 			Indicates an unsuccessful MAC destination address search
964 			due to the expiring of the search timer for this MSDU
965 
966 			<legal all>
967 */
968 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028
969 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
970 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
971 
972 /* Description		RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
973 
974 			<legal 0>
975 */
976 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028
977 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
978 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
979 
980 /* Description		RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
981 
982 			<legal 0>
983 */
984 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000002c
985 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
986 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
987 
988  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */
989 
990 
991  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
992 
993 
994 /* Description		RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
995 
996 			Address (lower 32 bits) of the MSDU buffer OR
997 			MSDU_EXTENSION descriptor OR Link Descriptor
998 
999 
1000 
1001 			In case of 'NULL' pointer, this field is set to 0
1002 
1003 			<legal all>
1004 */
1005 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030
1006 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
1007 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
1008 
1009 /* Description		RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
1010 
1011 			Address (upper 8 bits) of the MSDU buffer OR
1012 			MSDU_EXTENSION descriptor OR Link Descriptor
1013 
1014 
1015 
1016 			In case of 'NULL' pointer, this field is set to 0
1017 
1018 			<legal all>
1019 */
1020 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034
1021 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
1022 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
1023 
1024 /* Description		RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
1025 
1026 			Consumer: WBM
1027 
1028 			Producer: SW/FW
1029 
1030 
1031 
1032 			In case of 'NULL' pointer, this field is set to 0
1033 
1034 
1035 
1036 			Indicates to which buffer manager the buffer OR
1037 			MSDU_EXTENSION descriptor OR link descriptor that is being
1038 			pointed to shall be returned after the frame has been
1039 			processed. It is used by WBM for routing purposes.
1040 
1041 
1042 
1043 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
1044 			to the WMB buffer idle list
1045 
1046 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
1047 			returned to the WMB idle link descriptor idle list
1048 
1049 			<enum 2 FW_BM> This buffer shall be returned to the FW
1050 
1051 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
1052 			ring 0
1053 
1054 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
1055 			ring 1
1056 
1057 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
1058 			ring 2
1059 
1060 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
1061 			ring 3
1062 
1063 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
1064 			ring 3
1065 
1066 
1067 
1068 			<legal all>
1069 */
1070 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
1071 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
1072 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
1073 
1074 /* Description		RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
1075 
1076 			Cookie field exclusively used by SW.
1077 
1078 
1079 
1080 			In case of 'NULL' pointer, this field is set to 0
1081 
1082 
1083 
1084 			HW ignores the contents, accept that it passes the
1085 			programmed value on to other descriptors together with the
1086 			physical address
1087 
1088 
1089 
1090 			Field can be used by SW to for example associate the
1091 			buffers physical address with the virtual address
1092 
1093 			The bit definitions as used by SW are within SW HLD
1094 			specification
1095 
1096 
1097 
1098 			NOTE:
1099 
1100 			The three most significant bits can have a special
1101 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
1102 			STRUCT, and field transmit_bw_restriction is set
1103 
1104 
1105 
1106 			In case of NON punctured transmission:
1107 
1108 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
1109 
1110 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
1111 
1112 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
1113 
1114 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
1115 
1116 
1117 
1118 			In case of punctured transmission:
1119 
1120 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
1121 
1122 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
1123 
1124 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
1125 
1126 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
1127 
1128 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
1129 
1130 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
1131 
1132 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
1133 
1134 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
1135 
1136 
1137 
1138 			Note: a punctured transmission is indicated by the
1139 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
1140 			TLV
1141 
1142 
1143 
1144 			<legal all>
1145 */
1146 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034
1147 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
1148 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
1149 
1150  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
1151 
1152 
1153 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
1154 
1155 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1156 			over multiple buffers, this field will be valid in the Last
1157 			buffer used by the MSDU
1158 
1159 
1160 
1161 			<enum 0 Not_first_msdu> This is not the first MSDU in
1162 			the MPDU.
1163 
1164 			<enum 1 first_msdu> This MSDU is the first one in the
1165 			MPDU.
1166 
1167 
1168 
1169 			<legal all>
1170 */
1171 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
1172 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
1173 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
1174 
1175 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
1176 
1177 			Consumer: WBM/REO/SW/FW
1178 
1179 			Producer: RXDMA
1180 
1181 
1182 
1183 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1184 			over multiple buffers, this field will be valid in the Last
1185 			buffer used by the MSDU
1186 
1187 
1188 
1189 			<enum 0 Not_last_msdu> There are more MSDUs linked to
1190 			this MSDU that belongs to this MPDU
1191 
1192 			<enum 1 Last_msdu> this MSDU is the last one in the
1193 			MPDU. This setting is only allowed in combination with
1194 			'Msdu_continuation' set to 0. This implies that when an msdu
1195 			is spread out over multiple buffers and thus
1196 			msdu_continuation is set, only for the very last buffer of
1197 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
1198 
1199 
1200 
1201 			When both first_msdu_in_mpdu_flag and
1202 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
1203 			belongs to only contains a single MSDU.
1204 
1205 
1206 
1207 
1208 
1209 			<legal all>
1210 */
1211 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
1212 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
1213 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
1214 
1215 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
1216 
1217 			When set, this MSDU buffer was not able to hold the
1218 			entire MSDU. The next buffer will therefor contain
1219 			additional information related to this MSDU.
1220 
1221 
1222 
1223 			<legal all>
1224 */
1225 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038
1226 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
1227 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
1228 
1229 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
1230 
1231 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
1232 			over multiple buffers, this field will be valid in the First
1233 			buffer used by MSDU.
1234 
1235 
1236 
1237 			Full MSDU length in bytes after decapsulation.
1238 
1239 
1240 
1241 			This field is still valid for MPDU frames without
1242 			A-MSDU.  It still represents MSDU length after decapsulation
1243 
1244 
1245 
1246 			Or in case of RAW MPDUs, it indicates the length of the
1247 			entire MPDU (without FCS field)
1248 
1249 			<legal all>
1250 */
1251 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038
1252 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
1253 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
1254 
1255 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
1256 
1257 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1258 			over multiple buffers, this field will be valid in the Last
1259 			buffer used by the MSDU
1260 
1261 
1262 
1263 			The ID of the REO exit ring where the MSDU frame shall
1264 			push after (MPDU level) reordering has finished.
1265 
1266 
1267 
1268 			<enum 0 reo_destination_tcl> Reo will push the frame
1269 			into the REO2TCL ring
1270 
1271 			<enum 1 reo_destination_sw1> Reo will push the frame
1272 			into the REO2SW1 ring
1273 
1274 			<enum 2 reo_destination_sw2> Reo will push the frame
1275 			into the REO2SW1 ring
1276 
1277 			<enum 3 reo_destination_sw3> Reo will push the frame
1278 			into the REO2SW1 ring
1279 
1280 			<enum 4 reo_destination_sw4> Reo will push the frame
1281 			into the REO2SW1 ring
1282 
1283 			<enum 5 reo_destination_release> Reo will push the frame
1284 			into the REO_release ring
1285 
1286 			<enum 6 reo_destination_fw> Reo will push the frame into
1287 			the REO2FW ring
1288 
1289 			<enum 7 reo_destination_7> REO remaps this
1290 
1291 			<enum 8 reo_destination_8> REO remaps this <enum 9
1292 			reo_destination_9> REO remaps this <enum 10
1293 			reo_destination_10> REO remaps this
1294 
1295 			<enum 11 reo_destination_11> REO remaps this
1296 
1297 			<enum 12 reo_destination_12> REO remaps this <enum 13
1298 			reo_destination_13> REO remaps this
1299 
1300 			<enum 14 reo_destination_14> REO remaps this
1301 
1302 			<enum 15 reo_destination_15> REO remaps this
1303 
1304 			<enum 16 reo_destination_16> REO remaps this
1305 
1306 			<enum 17 reo_destination_17> REO remaps this
1307 
1308 			<enum 18 reo_destination_18> REO remaps this
1309 
1310 			<enum 19 reo_destination_19> REO remaps this
1311 
1312 			<enum 20 reo_destination_20> REO remaps this
1313 
1314 			<enum 21 reo_destination_21> REO remaps this
1315 
1316 			<enum 22 reo_destination_22> REO remaps this
1317 
1318 			<enum 23 reo_destination_23> REO remaps this
1319 
1320 			<enum 24 reo_destination_24> REO remaps this
1321 
1322 			<enum 25 reo_destination_25> REO remaps this
1323 
1324 			<enum 26 reo_destination_26> REO remaps this
1325 
1326 			<enum 27 reo_destination_27> REO remaps this
1327 
1328 			<enum 28 reo_destination_28> REO remaps this
1329 
1330 			<enum 29 reo_destination_29> REO remaps this
1331 
1332 			<enum 30 reo_destination_30> REO remaps this
1333 
1334 			<enum 31 reo_destination_31> REO remaps this
1335 
1336 
1337 
1338 			<legal all>
1339 */
1340 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038
1341 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
1342 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
1343 
1344 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
1345 
1346 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1347 			over multiple buffers, this field will be valid in the Last
1348 			buffer used by the MSDU
1349 
1350 
1351 
1352 			When set, REO shall drop this MSDU and not forward it to
1353 			any other ring...
1354 
1355 			<legal all>
1356 */
1357 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038
1358 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
1359 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
1360 
1361 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
1362 
1363 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1364 			over multiple buffers, this field will be valid in the Last
1365 			buffer used by the MSDU
1366 
1367 
1368 
1369 			Indicates that OLE found a valid SA entry for this MSDU
1370 
1371 			<legal all>
1372 */
1373 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038
1374 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
1375 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
1376 
1377 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
1378 
1379 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1380 			over multiple buffers, this field will be valid in the Last
1381 			buffer used by the MSDU
1382 
1383 
1384 
1385 			Indicates an unsuccessful MAC source address search due
1386 			to the expiring of the search timer for this MSDU
1387 
1388 			<legal all>
1389 */
1390 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038
1391 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
1392 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
1393 
1394 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
1395 
1396 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1397 			over multiple buffers, this field will be valid in the Last
1398 			buffer used by the MSDU
1399 
1400 
1401 
1402 			Indicates that OLE found a valid DA entry for this MSDU
1403 
1404 			<legal all>
1405 */
1406 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038
1407 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
1408 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
1409 
1410 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
1411 
1412 			Field Only valid if da_is_valid is set
1413 
1414 
1415 
1416 			Indicates the DA address was a Multicast of Broadcast
1417 			address for this MSDU
1418 
1419 			<legal all>
1420 */
1421 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038
1422 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
1423 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
1424 
1425 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
1426 
1427 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1428 			over multiple buffers, this field will be valid in the Last
1429 			buffer used by the MSDU
1430 
1431 
1432 
1433 			Indicates an unsuccessful MAC destination address search
1434 			due to the expiring of the search timer for this MSDU
1435 
1436 			<legal all>
1437 */
1438 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038
1439 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
1440 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
1441 
1442 /* Description		RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
1443 
1444 			<legal 0>
1445 */
1446 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038
1447 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
1448 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
1449 
1450 /* Description		RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
1451 
1452 			<legal 0>
1453 */
1454 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000003c
1455 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
1456 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
1457 
1458  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */
1459 
1460 
1461  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
1462 
1463 
1464 /* Description		RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
1465 
1466 			Address (lower 32 bits) of the MSDU buffer OR
1467 			MSDU_EXTENSION descriptor OR Link Descriptor
1468 
1469 
1470 
1471 			In case of 'NULL' pointer, this field is set to 0
1472 
1473 			<legal all>
1474 */
1475 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040
1476 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
1477 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
1478 
1479 /* Description		RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
1480 
1481 			Address (upper 8 bits) of the MSDU buffer OR
1482 			MSDU_EXTENSION descriptor OR Link Descriptor
1483 
1484 
1485 
1486 			In case of 'NULL' pointer, this field is set to 0
1487 
1488 			<legal all>
1489 */
1490 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044
1491 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
1492 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
1493 
1494 /* Description		RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
1495 
1496 			Consumer: WBM
1497 
1498 			Producer: SW/FW
1499 
1500 
1501 
1502 			In case of 'NULL' pointer, this field is set to 0
1503 
1504 
1505 
1506 			Indicates to which buffer manager the buffer OR
1507 			MSDU_EXTENSION descriptor OR link descriptor that is being
1508 			pointed to shall be returned after the frame has been
1509 			processed. It is used by WBM for routing purposes.
1510 
1511 
1512 
1513 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
1514 			to the WMB buffer idle list
1515 
1516 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
1517 			returned to the WMB idle link descriptor idle list
1518 
1519 			<enum 2 FW_BM> This buffer shall be returned to the FW
1520 
1521 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
1522 			ring 0
1523 
1524 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
1525 			ring 1
1526 
1527 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
1528 			ring 2
1529 
1530 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
1531 			ring 3
1532 
1533 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
1534 			ring 3
1535 
1536 
1537 
1538 			<legal all>
1539 */
1540 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
1541 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
1542 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
1543 
1544 /* Description		RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
1545 
1546 			Cookie field exclusively used by SW.
1547 
1548 
1549 
1550 			In case of 'NULL' pointer, this field is set to 0
1551 
1552 
1553 
1554 			HW ignores the contents, accept that it passes the
1555 			programmed value on to other descriptors together with the
1556 			physical address
1557 
1558 
1559 
1560 			Field can be used by SW to for example associate the
1561 			buffers physical address with the virtual address
1562 
1563 			The bit definitions as used by SW are within SW HLD
1564 			specification
1565 
1566 
1567 
1568 			NOTE:
1569 
1570 			The three most significant bits can have a special
1571 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
1572 			STRUCT, and field transmit_bw_restriction is set
1573 
1574 
1575 
1576 			In case of NON punctured transmission:
1577 
1578 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
1579 
1580 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
1581 
1582 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
1583 
1584 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
1585 
1586 
1587 
1588 			In case of punctured transmission:
1589 
1590 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
1591 
1592 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
1593 
1594 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
1595 
1596 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
1597 
1598 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
1599 
1600 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
1601 
1602 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
1603 
1604 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
1605 
1606 
1607 
1608 			Note: a punctured transmission is indicated by the
1609 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
1610 			TLV
1611 
1612 
1613 
1614 			<legal all>
1615 */
1616 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044
1617 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
1618 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
1619 
1620  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
1621 
1622 
1623 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
1624 
1625 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1626 			over multiple buffers, this field will be valid in the Last
1627 			buffer used by the MSDU
1628 
1629 
1630 
1631 			<enum 0 Not_first_msdu> This is not the first MSDU in
1632 			the MPDU.
1633 
1634 			<enum 1 first_msdu> This MSDU is the first one in the
1635 			MPDU.
1636 
1637 
1638 
1639 			<legal all>
1640 */
1641 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
1642 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
1643 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
1644 
1645 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
1646 
1647 			Consumer: WBM/REO/SW/FW
1648 
1649 			Producer: RXDMA
1650 
1651 
1652 
1653 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1654 			over multiple buffers, this field will be valid in the Last
1655 			buffer used by the MSDU
1656 
1657 
1658 
1659 			<enum 0 Not_last_msdu> There are more MSDUs linked to
1660 			this MSDU that belongs to this MPDU
1661 
1662 			<enum 1 Last_msdu> this MSDU is the last one in the
1663 			MPDU. This setting is only allowed in combination with
1664 			'Msdu_continuation' set to 0. This implies that when an msdu
1665 			is spread out over multiple buffers and thus
1666 			msdu_continuation is set, only for the very last buffer of
1667 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
1668 
1669 
1670 
1671 			When both first_msdu_in_mpdu_flag and
1672 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
1673 			belongs to only contains a single MSDU.
1674 
1675 
1676 
1677 
1678 
1679 			<legal all>
1680 */
1681 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
1682 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
1683 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
1684 
1685 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
1686 
1687 			When set, this MSDU buffer was not able to hold the
1688 			entire MSDU. The next buffer will therefor contain
1689 			additional information related to this MSDU.
1690 
1691 
1692 
1693 			<legal all>
1694 */
1695 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048
1696 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
1697 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
1698 
1699 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
1700 
1701 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
1702 			over multiple buffers, this field will be valid in the First
1703 			buffer used by MSDU.
1704 
1705 
1706 
1707 			Full MSDU length in bytes after decapsulation.
1708 
1709 
1710 
1711 			This field is still valid for MPDU frames without
1712 			A-MSDU.  It still represents MSDU length after decapsulation
1713 
1714 
1715 
1716 			Or in case of RAW MPDUs, it indicates the length of the
1717 			entire MPDU (without FCS field)
1718 
1719 			<legal all>
1720 */
1721 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048
1722 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
1723 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
1724 
1725 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
1726 
1727 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1728 			over multiple buffers, this field will be valid in the Last
1729 			buffer used by the MSDU
1730 
1731 
1732 
1733 			The ID of the REO exit ring where the MSDU frame shall
1734 			push after (MPDU level) reordering has finished.
1735 
1736 
1737 
1738 			<enum 0 reo_destination_tcl> Reo will push the frame
1739 			into the REO2TCL ring
1740 
1741 			<enum 1 reo_destination_sw1> Reo will push the frame
1742 			into the REO2SW1 ring
1743 
1744 			<enum 2 reo_destination_sw2> Reo will push the frame
1745 			into the REO2SW1 ring
1746 
1747 			<enum 3 reo_destination_sw3> Reo will push the frame
1748 			into the REO2SW1 ring
1749 
1750 			<enum 4 reo_destination_sw4> Reo will push the frame
1751 			into the REO2SW1 ring
1752 
1753 			<enum 5 reo_destination_release> Reo will push the frame
1754 			into the REO_release ring
1755 
1756 			<enum 6 reo_destination_fw> Reo will push the frame into
1757 			the REO2FW ring
1758 
1759 			<enum 7 reo_destination_7> REO remaps this
1760 
1761 			<enum 8 reo_destination_8> REO remaps this <enum 9
1762 			reo_destination_9> REO remaps this <enum 10
1763 			reo_destination_10> REO remaps this
1764 
1765 			<enum 11 reo_destination_11> REO remaps this
1766 
1767 			<enum 12 reo_destination_12> REO remaps this <enum 13
1768 			reo_destination_13> REO remaps this
1769 
1770 			<enum 14 reo_destination_14> REO remaps this
1771 
1772 			<enum 15 reo_destination_15> REO remaps this
1773 
1774 			<enum 16 reo_destination_16> REO remaps this
1775 
1776 			<enum 17 reo_destination_17> REO remaps this
1777 
1778 			<enum 18 reo_destination_18> REO remaps this
1779 
1780 			<enum 19 reo_destination_19> REO remaps this
1781 
1782 			<enum 20 reo_destination_20> REO remaps this
1783 
1784 			<enum 21 reo_destination_21> REO remaps this
1785 
1786 			<enum 22 reo_destination_22> REO remaps this
1787 
1788 			<enum 23 reo_destination_23> REO remaps this
1789 
1790 			<enum 24 reo_destination_24> REO remaps this
1791 
1792 			<enum 25 reo_destination_25> REO remaps this
1793 
1794 			<enum 26 reo_destination_26> REO remaps this
1795 
1796 			<enum 27 reo_destination_27> REO remaps this
1797 
1798 			<enum 28 reo_destination_28> REO remaps this
1799 
1800 			<enum 29 reo_destination_29> REO remaps this
1801 
1802 			<enum 30 reo_destination_30> REO remaps this
1803 
1804 			<enum 31 reo_destination_31> REO remaps this
1805 
1806 
1807 
1808 			<legal all>
1809 */
1810 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048
1811 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
1812 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
1813 
1814 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
1815 
1816 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1817 			over multiple buffers, this field will be valid in the Last
1818 			buffer used by the MSDU
1819 
1820 
1821 
1822 			When set, REO shall drop this MSDU and not forward it to
1823 			any other ring...
1824 
1825 			<legal all>
1826 */
1827 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048
1828 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
1829 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
1830 
1831 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
1832 
1833 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1834 			over multiple buffers, this field will be valid in the Last
1835 			buffer used by the MSDU
1836 
1837 
1838 
1839 			Indicates that OLE found a valid SA entry for this MSDU
1840 
1841 			<legal all>
1842 */
1843 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048
1844 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
1845 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
1846 
1847 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
1848 
1849 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1850 			over multiple buffers, this field will be valid in the Last
1851 			buffer used by the MSDU
1852 
1853 
1854 
1855 			Indicates an unsuccessful MAC source address search due
1856 			to the expiring of the search timer for this MSDU
1857 
1858 			<legal all>
1859 */
1860 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048
1861 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
1862 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
1863 
1864 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
1865 
1866 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1867 			over multiple buffers, this field will be valid in the Last
1868 			buffer used by the MSDU
1869 
1870 
1871 
1872 			Indicates that OLE found a valid DA entry for this MSDU
1873 
1874 			<legal all>
1875 */
1876 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048
1877 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
1878 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
1879 
1880 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
1881 
1882 			Field Only valid if da_is_valid is set
1883 
1884 
1885 
1886 			Indicates the DA address was a Multicast of Broadcast
1887 			address for this MSDU
1888 
1889 			<legal all>
1890 */
1891 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048
1892 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
1893 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
1894 
1895 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
1896 
1897 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
1898 			over multiple buffers, this field will be valid in the Last
1899 			buffer used by the MSDU
1900 
1901 
1902 
1903 			Indicates an unsuccessful MAC destination address search
1904 			due to the expiring of the search timer for this MSDU
1905 
1906 			<legal all>
1907 */
1908 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048
1909 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
1910 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
1911 
1912 /* Description		RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
1913 
1914 			<legal 0>
1915 */
1916 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048
1917 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
1918 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
1919 
1920 /* Description		RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
1921 
1922 			<legal 0>
1923 */
1924 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000004c
1925 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
1926 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
1927 
1928  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */
1929 
1930 
1931  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
1932 
1933 
1934 /* Description		RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
1935 
1936 			Address (lower 32 bits) of the MSDU buffer OR
1937 			MSDU_EXTENSION descriptor OR Link Descriptor
1938 
1939 
1940 
1941 			In case of 'NULL' pointer, this field is set to 0
1942 
1943 			<legal all>
1944 */
1945 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050
1946 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
1947 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
1948 
1949 /* Description		RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
1950 
1951 			Address (upper 8 bits) of the MSDU buffer OR
1952 			MSDU_EXTENSION descriptor OR Link Descriptor
1953 
1954 
1955 
1956 			In case of 'NULL' pointer, this field is set to 0
1957 
1958 			<legal all>
1959 */
1960 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054
1961 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
1962 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
1963 
1964 /* Description		RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
1965 
1966 			Consumer: WBM
1967 
1968 			Producer: SW/FW
1969 
1970 
1971 
1972 			In case of 'NULL' pointer, this field is set to 0
1973 
1974 
1975 
1976 			Indicates to which buffer manager the buffer OR
1977 			MSDU_EXTENSION descriptor OR link descriptor that is being
1978 			pointed to shall be returned after the frame has been
1979 			processed. It is used by WBM for routing purposes.
1980 
1981 
1982 
1983 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
1984 			to the WMB buffer idle list
1985 
1986 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
1987 			returned to the WMB idle link descriptor idle list
1988 
1989 			<enum 2 FW_BM> This buffer shall be returned to the FW
1990 
1991 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
1992 			ring 0
1993 
1994 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
1995 			ring 1
1996 
1997 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
1998 			ring 2
1999 
2000 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
2001 			ring 3
2002 
2003 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
2004 			ring 3
2005 
2006 
2007 
2008 			<legal all>
2009 */
2010 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
2011 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
2012 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
2013 
2014 /* Description		RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
2015 
2016 			Cookie field exclusively used by SW.
2017 
2018 
2019 
2020 			In case of 'NULL' pointer, this field is set to 0
2021 
2022 
2023 
2024 			HW ignores the contents, accept that it passes the
2025 			programmed value on to other descriptors together with the
2026 			physical address
2027 
2028 
2029 
2030 			Field can be used by SW to for example associate the
2031 			buffers physical address with the virtual address
2032 
2033 			The bit definitions as used by SW are within SW HLD
2034 			specification
2035 
2036 
2037 
2038 			NOTE:
2039 
2040 			The three most significant bits can have a special
2041 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
2042 			STRUCT, and field transmit_bw_restriction is set
2043 
2044 
2045 
2046 			In case of NON punctured transmission:
2047 
2048 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
2049 
2050 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
2051 
2052 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
2053 
2054 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
2055 
2056 
2057 
2058 			In case of punctured transmission:
2059 
2060 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
2061 
2062 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
2063 
2064 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
2065 
2066 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
2067 
2068 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
2069 
2070 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
2071 
2072 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
2073 
2074 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
2075 
2076 
2077 
2078 			Note: a punctured transmission is indicated by the
2079 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
2080 			TLV
2081 
2082 
2083 
2084 			<legal all>
2085 */
2086 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054
2087 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
2088 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
2089 
2090  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
2091 
2092 
2093 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
2094 
2095 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2096 			over multiple buffers, this field will be valid in the Last
2097 			buffer used by the MSDU
2098 
2099 
2100 
2101 			<enum 0 Not_first_msdu> This is not the first MSDU in
2102 			the MPDU.
2103 
2104 			<enum 1 first_msdu> This MSDU is the first one in the
2105 			MPDU.
2106 
2107 
2108 
2109 			<legal all>
2110 */
2111 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
2112 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
2113 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
2114 
2115 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
2116 
2117 			Consumer: WBM/REO/SW/FW
2118 
2119 			Producer: RXDMA
2120 
2121 
2122 
2123 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2124 			over multiple buffers, this field will be valid in the Last
2125 			buffer used by the MSDU
2126 
2127 
2128 
2129 			<enum 0 Not_last_msdu> There are more MSDUs linked to
2130 			this MSDU that belongs to this MPDU
2131 
2132 			<enum 1 Last_msdu> this MSDU is the last one in the
2133 			MPDU. This setting is only allowed in combination with
2134 			'Msdu_continuation' set to 0. This implies that when an msdu
2135 			is spread out over multiple buffers and thus
2136 			msdu_continuation is set, only for the very last buffer of
2137 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
2138 
2139 
2140 
2141 			When both first_msdu_in_mpdu_flag and
2142 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
2143 			belongs to only contains a single MSDU.
2144 
2145 
2146 
2147 
2148 
2149 			<legal all>
2150 */
2151 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
2152 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
2153 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
2154 
2155 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
2156 
2157 			When set, this MSDU buffer was not able to hold the
2158 			entire MSDU. The next buffer will therefor contain
2159 			additional information related to this MSDU.
2160 
2161 
2162 
2163 			<legal all>
2164 */
2165 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058
2166 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
2167 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
2168 
2169 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
2170 
2171 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
2172 			over multiple buffers, this field will be valid in the First
2173 			buffer used by MSDU.
2174 
2175 
2176 
2177 			Full MSDU length in bytes after decapsulation.
2178 
2179 
2180 
2181 			This field is still valid for MPDU frames without
2182 			A-MSDU.  It still represents MSDU length after decapsulation
2183 
2184 
2185 
2186 			Or in case of RAW MPDUs, it indicates the length of the
2187 			entire MPDU (without FCS field)
2188 
2189 			<legal all>
2190 */
2191 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058
2192 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
2193 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
2194 
2195 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
2196 
2197 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2198 			over multiple buffers, this field will be valid in the Last
2199 			buffer used by the MSDU
2200 
2201 
2202 
2203 			The ID of the REO exit ring where the MSDU frame shall
2204 			push after (MPDU level) reordering has finished.
2205 
2206 
2207 
2208 			<enum 0 reo_destination_tcl> Reo will push the frame
2209 			into the REO2TCL ring
2210 
2211 			<enum 1 reo_destination_sw1> Reo will push the frame
2212 			into the REO2SW1 ring
2213 
2214 			<enum 2 reo_destination_sw2> Reo will push the frame
2215 			into the REO2SW1 ring
2216 
2217 			<enum 3 reo_destination_sw3> Reo will push the frame
2218 			into the REO2SW1 ring
2219 
2220 			<enum 4 reo_destination_sw4> Reo will push the frame
2221 			into the REO2SW1 ring
2222 
2223 			<enum 5 reo_destination_release> Reo will push the frame
2224 			into the REO_release ring
2225 
2226 			<enum 6 reo_destination_fw> Reo will push the frame into
2227 			the REO2FW ring
2228 
2229 			<enum 7 reo_destination_7> REO remaps this
2230 
2231 			<enum 8 reo_destination_8> REO remaps this <enum 9
2232 			reo_destination_9> REO remaps this <enum 10
2233 			reo_destination_10> REO remaps this
2234 
2235 			<enum 11 reo_destination_11> REO remaps this
2236 
2237 			<enum 12 reo_destination_12> REO remaps this <enum 13
2238 			reo_destination_13> REO remaps this
2239 
2240 			<enum 14 reo_destination_14> REO remaps this
2241 
2242 			<enum 15 reo_destination_15> REO remaps this
2243 
2244 			<enum 16 reo_destination_16> REO remaps this
2245 
2246 			<enum 17 reo_destination_17> REO remaps this
2247 
2248 			<enum 18 reo_destination_18> REO remaps this
2249 
2250 			<enum 19 reo_destination_19> REO remaps this
2251 
2252 			<enum 20 reo_destination_20> REO remaps this
2253 
2254 			<enum 21 reo_destination_21> REO remaps this
2255 
2256 			<enum 22 reo_destination_22> REO remaps this
2257 
2258 			<enum 23 reo_destination_23> REO remaps this
2259 
2260 			<enum 24 reo_destination_24> REO remaps this
2261 
2262 			<enum 25 reo_destination_25> REO remaps this
2263 
2264 			<enum 26 reo_destination_26> REO remaps this
2265 
2266 			<enum 27 reo_destination_27> REO remaps this
2267 
2268 			<enum 28 reo_destination_28> REO remaps this
2269 
2270 			<enum 29 reo_destination_29> REO remaps this
2271 
2272 			<enum 30 reo_destination_30> REO remaps this
2273 
2274 			<enum 31 reo_destination_31> REO remaps this
2275 
2276 
2277 
2278 			<legal all>
2279 */
2280 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058
2281 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
2282 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
2283 
2284 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
2285 
2286 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2287 			over multiple buffers, this field will be valid in the Last
2288 			buffer used by the MSDU
2289 
2290 
2291 
2292 			When set, REO shall drop this MSDU and not forward it to
2293 			any other ring...
2294 
2295 			<legal all>
2296 */
2297 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058
2298 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
2299 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
2300 
2301 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
2302 
2303 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2304 			over multiple buffers, this field will be valid in the Last
2305 			buffer used by the MSDU
2306 
2307 
2308 
2309 			Indicates that OLE found a valid SA entry for this MSDU
2310 
2311 			<legal all>
2312 */
2313 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058
2314 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
2315 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
2316 
2317 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
2318 
2319 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2320 			over multiple buffers, this field will be valid in the Last
2321 			buffer used by the MSDU
2322 
2323 
2324 
2325 			Indicates an unsuccessful MAC source address search due
2326 			to the expiring of the search timer for this MSDU
2327 
2328 			<legal all>
2329 */
2330 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058
2331 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
2332 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
2333 
2334 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
2335 
2336 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2337 			over multiple buffers, this field will be valid in the Last
2338 			buffer used by the MSDU
2339 
2340 
2341 
2342 			Indicates that OLE found a valid DA entry for this MSDU
2343 
2344 			<legal all>
2345 */
2346 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058
2347 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
2348 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
2349 
2350 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
2351 
2352 			Field Only valid if da_is_valid is set
2353 
2354 
2355 
2356 			Indicates the DA address was a Multicast of Broadcast
2357 			address for this MSDU
2358 
2359 			<legal all>
2360 */
2361 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058
2362 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
2363 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
2364 
2365 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
2366 
2367 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2368 			over multiple buffers, this field will be valid in the Last
2369 			buffer used by the MSDU
2370 
2371 
2372 
2373 			Indicates an unsuccessful MAC destination address search
2374 			due to the expiring of the search timer for this MSDU
2375 
2376 			<legal all>
2377 */
2378 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058
2379 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
2380 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
2381 
2382 /* Description		RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
2383 
2384 			<legal 0>
2385 */
2386 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058
2387 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
2388 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
2389 
2390 /* Description		RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
2391 
2392 			<legal 0>
2393 */
2394 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000005c
2395 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
2396 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
2397 
2398  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */
2399 
2400 
2401  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
2402 
2403 
2404 /* Description		RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
2405 
2406 			Address (lower 32 bits) of the MSDU buffer OR
2407 			MSDU_EXTENSION descriptor OR Link Descriptor
2408 
2409 
2410 
2411 			In case of 'NULL' pointer, this field is set to 0
2412 
2413 			<legal all>
2414 */
2415 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060
2416 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
2417 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
2418 
2419 /* Description		RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
2420 
2421 			Address (upper 8 bits) of the MSDU buffer OR
2422 			MSDU_EXTENSION descriptor OR Link Descriptor
2423 
2424 
2425 
2426 			In case of 'NULL' pointer, this field is set to 0
2427 
2428 			<legal all>
2429 */
2430 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064
2431 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
2432 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
2433 
2434 /* Description		RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
2435 
2436 			Consumer: WBM
2437 
2438 			Producer: SW/FW
2439 
2440 
2441 
2442 			In case of 'NULL' pointer, this field is set to 0
2443 
2444 
2445 
2446 			Indicates to which buffer manager the buffer OR
2447 			MSDU_EXTENSION descriptor OR link descriptor that is being
2448 			pointed to shall be returned after the frame has been
2449 			processed. It is used by WBM for routing purposes.
2450 
2451 
2452 
2453 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
2454 			to the WMB buffer idle list
2455 
2456 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
2457 			returned to the WMB idle link descriptor idle list
2458 
2459 			<enum 2 FW_BM> This buffer shall be returned to the FW
2460 
2461 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
2462 			ring 0
2463 
2464 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
2465 			ring 1
2466 
2467 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
2468 			ring 2
2469 
2470 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
2471 			ring 3
2472 
2473 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
2474 			ring 3
2475 
2476 
2477 
2478 			<legal all>
2479 */
2480 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
2481 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
2482 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
2483 
2484 /* Description		RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
2485 
2486 			Cookie field exclusively used by SW.
2487 
2488 
2489 
2490 			In case of 'NULL' pointer, this field is set to 0
2491 
2492 
2493 
2494 			HW ignores the contents, accept that it passes the
2495 			programmed value on to other descriptors together with the
2496 			physical address
2497 
2498 
2499 
2500 			Field can be used by SW to for example associate the
2501 			buffers physical address with the virtual address
2502 
2503 			The bit definitions as used by SW are within SW HLD
2504 			specification
2505 
2506 
2507 
2508 			NOTE:
2509 
2510 			The three most significant bits can have a special
2511 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
2512 			STRUCT, and field transmit_bw_restriction is set
2513 
2514 
2515 
2516 			In case of NON punctured transmission:
2517 
2518 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
2519 
2520 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
2521 
2522 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
2523 
2524 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
2525 
2526 
2527 
2528 			In case of punctured transmission:
2529 
2530 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
2531 
2532 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
2533 
2534 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
2535 
2536 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
2537 
2538 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
2539 
2540 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
2541 
2542 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
2543 
2544 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
2545 
2546 
2547 
2548 			Note: a punctured transmission is indicated by the
2549 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
2550 			TLV
2551 
2552 
2553 
2554 			<legal all>
2555 */
2556 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064
2557 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
2558 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
2559 
2560  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
2561 
2562 
2563 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
2564 
2565 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2566 			over multiple buffers, this field will be valid in the Last
2567 			buffer used by the MSDU
2568 
2569 
2570 
2571 			<enum 0 Not_first_msdu> This is not the first MSDU in
2572 			the MPDU.
2573 
2574 			<enum 1 first_msdu> This MSDU is the first one in the
2575 			MPDU.
2576 
2577 
2578 
2579 			<legal all>
2580 */
2581 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
2582 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
2583 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
2584 
2585 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
2586 
2587 			Consumer: WBM/REO/SW/FW
2588 
2589 			Producer: RXDMA
2590 
2591 
2592 
2593 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2594 			over multiple buffers, this field will be valid in the Last
2595 			buffer used by the MSDU
2596 
2597 
2598 
2599 			<enum 0 Not_last_msdu> There are more MSDUs linked to
2600 			this MSDU that belongs to this MPDU
2601 
2602 			<enum 1 Last_msdu> this MSDU is the last one in the
2603 			MPDU. This setting is only allowed in combination with
2604 			'Msdu_continuation' set to 0. This implies that when an msdu
2605 			is spread out over multiple buffers and thus
2606 			msdu_continuation is set, only for the very last buffer of
2607 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
2608 
2609 
2610 
2611 			When both first_msdu_in_mpdu_flag and
2612 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
2613 			belongs to only contains a single MSDU.
2614 
2615 
2616 
2617 
2618 
2619 			<legal all>
2620 */
2621 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
2622 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
2623 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
2624 
2625 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
2626 
2627 			When set, this MSDU buffer was not able to hold the
2628 			entire MSDU. The next buffer will therefor contain
2629 			additional information related to this MSDU.
2630 
2631 
2632 
2633 			<legal all>
2634 */
2635 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068
2636 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
2637 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
2638 
2639 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
2640 
2641 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
2642 			over multiple buffers, this field will be valid in the First
2643 			buffer used by MSDU.
2644 
2645 
2646 
2647 			Full MSDU length in bytes after decapsulation.
2648 
2649 
2650 
2651 			This field is still valid for MPDU frames without
2652 			A-MSDU.  It still represents MSDU length after decapsulation
2653 
2654 
2655 
2656 			Or in case of RAW MPDUs, it indicates the length of the
2657 			entire MPDU (without FCS field)
2658 
2659 			<legal all>
2660 */
2661 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068
2662 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
2663 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
2664 
2665 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
2666 
2667 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2668 			over multiple buffers, this field will be valid in the Last
2669 			buffer used by the MSDU
2670 
2671 
2672 
2673 			The ID of the REO exit ring where the MSDU frame shall
2674 			push after (MPDU level) reordering has finished.
2675 
2676 
2677 
2678 			<enum 0 reo_destination_tcl> Reo will push the frame
2679 			into the REO2TCL ring
2680 
2681 			<enum 1 reo_destination_sw1> Reo will push the frame
2682 			into the REO2SW1 ring
2683 
2684 			<enum 2 reo_destination_sw2> Reo will push the frame
2685 			into the REO2SW1 ring
2686 
2687 			<enum 3 reo_destination_sw3> Reo will push the frame
2688 			into the REO2SW1 ring
2689 
2690 			<enum 4 reo_destination_sw4> Reo will push the frame
2691 			into the REO2SW1 ring
2692 
2693 			<enum 5 reo_destination_release> Reo will push the frame
2694 			into the REO_release ring
2695 
2696 			<enum 6 reo_destination_fw> Reo will push the frame into
2697 			the REO2FW ring
2698 
2699 			<enum 7 reo_destination_7> REO remaps this
2700 
2701 			<enum 8 reo_destination_8> REO remaps this <enum 9
2702 			reo_destination_9> REO remaps this <enum 10
2703 			reo_destination_10> REO remaps this
2704 
2705 			<enum 11 reo_destination_11> REO remaps this
2706 
2707 			<enum 12 reo_destination_12> REO remaps this <enum 13
2708 			reo_destination_13> REO remaps this
2709 
2710 			<enum 14 reo_destination_14> REO remaps this
2711 
2712 			<enum 15 reo_destination_15> REO remaps this
2713 
2714 			<enum 16 reo_destination_16> REO remaps this
2715 
2716 			<enum 17 reo_destination_17> REO remaps this
2717 
2718 			<enum 18 reo_destination_18> REO remaps this
2719 
2720 			<enum 19 reo_destination_19> REO remaps this
2721 
2722 			<enum 20 reo_destination_20> REO remaps this
2723 
2724 			<enum 21 reo_destination_21> REO remaps this
2725 
2726 			<enum 22 reo_destination_22> REO remaps this
2727 
2728 			<enum 23 reo_destination_23> REO remaps this
2729 
2730 			<enum 24 reo_destination_24> REO remaps this
2731 
2732 			<enum 25 reo_destination_25> REO remaps this
2733 
2734 			<enum 26 reo_destination_26> REO remaps this
2735 
2736 			<enum 27 reo_destination_27> REO remaps this
2737 
2738 			<enum 28 reo_destination_28> REO remaps this
2739 
2740 			<enum 29 reo_destination_29> REO remaps this
2741 
2742 			<enum 30 reo_destination_30> REO remaps this
2743 
2744 			<enum 31 reo_destination_31> REO remaps this
2745 
2746 
2747 
2748 			<legal all>
2749 */
2750 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068
2751 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
2752 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
2753 
2754 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
2755 
2756 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2757 			over multiple buffers, this field will be valid in the Last
2758 			buffer used by the MSDU
2759 
2760 
2761 
2762 			When set, REO shall drop this MSDU and not forward it to
2763 			any other ring...
2764 
2765 			<legal all>
2766 */
2767 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068
2768 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
2769 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
2770 
2771 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
2772 
2773 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2774 			over multiple buffers, this field will be valid in the Last
2775 			buffer used by the MSDU
2776 
2777 
2778 
2779 			Indicates that OLE found a valid SA entry for this MSDU
2780 
2781 			<legal all>
2782 */
2783 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068
2784 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
2785 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
2786 
2787 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
2788 
2789 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2790 			over multiple buffers, this field will be valid in the Last
2791 			buffer used by the MSDU
2792 
2793 
2794 
2795 			Indicates an unsuccessful MAC source address search due
2796 			to the expiring of the search timer for this MSDU
2797 
2798 			<legal all>
2799 */
2800 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068
2801 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
2802 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
2803 
2804 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
2805 
2806 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2807 			over multiple buffers, this field will be valid in the Last
2808 			buffer used by the MSDU
2809 
2810 
2811 
2812 			Indicates that OLE found a valid DA entry for this MSDU
2813 
2814 			<legal all>
2815 */
2816 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068
2817 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
2818 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
2819 
2820 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
2821 
2822 			Field Only valid if da_is_valid is set
2823 
2824 
2825 
2826 			Indicates the DA address was a Multicast of Broadcast
2827 			address for this MSDU
2828 
2829 			<legal all>
2830 */
2831 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068
2832 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
2833 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
2834 
2835 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
2836 
2837 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
2838 			over multiple buffers, this field will be valid in the Last
2839 			buffer used by the MSDU
2840 
2841 
2842 
2843 			Indicates an unsuccessful MAC destination address search
2844 			due to the expiring of the search timer for this MSDU
2845 
2846 			<legal all>
2847 */
2848 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068
2849 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
2850 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
2851 
2852 /* Description		RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
2853 
2854 			<legal 0>
2855 */
2856 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068
2857 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
2858 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
2859 
2860 /* Description		RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
2861 
2862 			<legal 0>
2863 */
2864 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000006c
2865 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
2866 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
2867 
2868  /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */
2869 
2870 
2871  /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
2872 
2873 
2874 /* Description		RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
2875 
2876 			Address (lower 32 bits) of the MSDU buffer OR
2877 			MSDU_EXTENSION descriptor OR Link Descriptor
2878 
2879 
2880 
2881 			In case of 'NULL' pointer, this field is set to 0
2882 
2883 			<legal all>
2884 */
2885 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070
2886 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
2887 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
2888 
2889 /* Description		RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
2890 
2891 			Address (upper 8 bits) of the MSDU buffer OR
2892 			MSDU_EXTENSION descriptor OR Link Descriptor
2893 
2894 
2895 
2896 			In case of 'NULL' pointer, this field is set to 0
2897 
2898 			<legal all>
2899 */
2900 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074
2901 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
2902 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
2903 
2904 /* Description		RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
2905 
2906 			Consumer: WBM
2907 
2908 			Producer: SW/FW
2909 
2910 
2911 
2912 			In case of 'NULL' pointer, this field is set to 0
2913 
2914 
2915 
2916 			Indicates to which buffer manager the buffer OR
2917 			MSDU_EXTENSION descriptor OR link descriptor that is being
2918 			pointed to shall be returned after the frame has been
2919 			processed. It is used by WBM for routing purposes.
2920 
2921 
2922 
2923 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
2924 			to the WMB buffer idle list
2925 
2926 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
2927 			returned to the WMB idle link descriptor idle list
2928 
2929 			<enum 2 FW_BM> This buffer shall be returned to the FW
2930 
2931 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
2932 			ring 0
2933 
2934 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
2935 			ring 1
2936 
2937 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
2938 			ring 2
2939 
2940 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
2941 			ring 3
2942 
2943 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
2944 			ring 3
2945 
2946 
2947 
2948 			<legal all>
2949 */
2950 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
2951 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
2952 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
2953 
2954 /* Description		RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
2955 
2956 			Cookie field exclusively used by SW.
2957 
2958 
2959 
2960 			In case of 'NULL' pointer, this field is set to 0
2961 
2962 
2963 
2964 			HW ignores the contents, accept that it passes the
2965 			programmed value on to other descriptors together with the
2966 			physical address
2967 
2968 
2969 
2970 			Field can be used by SW to for example associate the
2971 			buffers physical address with the virtual address
2972 
2973 			The bit definitions as used by SW are within SW HLD
2974 			specification
2975 
2976 
2977 
2978 			NOTE:
2979 
2980 			The three most significant bits can have a special
2981 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
2982 			STRUCT, and field transmit_bw_restriction is set
2983 
2984 
2985 
2986 			In case of NON punctured transmission:
2987 
2988 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
2989 
2990 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
2991 
2992 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
2993 
2994 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
2995 
2996 
2997 
2998 			In case of punctured transmission:
2999 
3000 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
3001 
3002 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
3003 
3004 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
3005 
3006 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
3007 
3008 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
3009 
3010 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
3011 
3012 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
3013 
3014 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
3015 
3016 
3017 
3018 			Note: a punctured transmission is indicated by the
3019 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
3020 			TLV
3021 
3022 
3023 
3024 			<legal all>
3025 */
3026 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074
3027 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
3028 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
3029 
3030  /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
3031 
3032 
3033 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
3034 
3035 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3036 			over multiple buffers, this field will be valid in the Last
3037 			buffer used by the MSDU
3038 
3039 
3040 
3041 			<enum 0 Not_first_msdu> This is not the first MSDU in
3042 			the MPDU.
3043 
3044 			<enum 1 first_msdu> This MSDU is the first one in the
3045 			MPDU.
3046 
3047 
3048 
3049 			<legal all>
3050 */
3051 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
3052 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
3053 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
3054 
3055 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
3056 
3057 			Consumer: WBM/REO/SW/FW
3058 
3059 			Producer: RXDMA
3060 
3061 
3062 
3063 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3064 			over multiple buffers, this field will be valid in the Last
3065 			buffer used by the MSDU
3066 
3067 
3068 
3069 			<enum 0 Not_last_msdu> There are more MSDUs linked to
3070 			this MSDU that belongs to this MPDU
3071 
3072 			<enum 1 Last_msdu> this MSDU is the last one in the
3073 			MPDU. This setting is only allowed in combination with
3074 			'Msdu_continuation' set to 0. This implies that when an msdu
3075 			is spread out over multiple buffers and thus
3076 			msdu_continuation is set, only for the very last buffer of
3077 			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
3078 
3079 
3080 
3081 			When both first_msdu_in_mpdu_flag and
3082 			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
3083 			belongs to only contains a single MSDU.
3084 
3085 
3086 
3087 
3088 
3089 			<legal all>
3090 */
3091 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
3092 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
3093 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
3094 
3095 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
3096 
3097 			When set, this MSDU buffer was not able to hold the
3098 			entire MSDU. The next buffer will therefor contain
3099 			additional information related to this MSDU.
3100 
3101 
3102 
3103 			<legal all>
3104 */
3105 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078
3106 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
3107 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
3108 
3109 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
3110 
3111 			Parsed from RX_MSDU_START TLV . In the case MSDU spans
3112 			over multiple buffers, this field will be valid in the First
3113 			buffer used by MSDU.
3114 
3115 
3116 
3117 			Full MSDU length in bytes after decapsulation.
3118 
3119 
3120 
3121 			This field is still valid for MPDU frames without
3122 			A-MSDU.  It still represents MSDU length after decapsulation
3123 
3124 
3125 
3126 			Or in case of RAW MPDUs, it indicates the length of the
3127 			entire MPDU (without FCS field)
3128 
3129 			<legal all>
3130 */
3131 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078
3132 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
3133 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
3134 
3135 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
3136 
3137 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3138 			over multiple buffers, this field will be valid in the Last
3139 			buffer used by the MSDU
3140 
3141 
3142 
3143 			The ID of the REO exit ring where the MSDU frame shall
3144 			push after (MPDU level) reordering has finished.
3145 
3146 
3147 
3148 			<enum 0 reo_destination_tcl> Reo will push the frame
3149 			into the REO2TCL ring
3150 
3151 			<enum 1 reo_destination_sw1> Reo will push the frame
3152 			into the REO2SW1 ring
3153 
3154 			<enum 2 reo_destination_sw2> Reo will push the frame
3155 			into the REO2SW1 ring
3156 
3157 			<enum 3 reo_destination_sw3> Reo will push the frame
3158 			into the REO2SW1 ring
3159 
3160 			<enum 4 reo_destination_sw4> Reo will push the frame
3161 			into the REO2SW1 ring
3162 
3163 			<enum 5 reo_destination_release> Reo will push the frame
3164 			into the REO_release ring
3165 
3166 			<enum 6 reo_destination_fw> Reo will push the frame into
3167 			the REO2FW ring
3168 
3169 			<enum 7 reo_destination_7> REO remaps this
3170 
3171 			<enum 8 reo_destination_8> REO remaps this <enum 9
3172 			reo_destination_9> REO remaps this <enum 10
3173 			reo_destination_10> REO remaps this
3174 
3175 			<enum 11 reo_destination_11> REO remaps this
3176 
3177 			<enum 12 reo_destination_12> REO remaps this <enum 13
3178 			reo_destination_13> REO remaps this
3179 
3180 			<enum 14 reo_destination_14> REO remaps this
3181 
3182 			<enum 15 reo_destination_15> REO remaps this
3183 
3184 			<enum 16 reo_destination_16> REO remaps this
3185 
3186 			<enum 17 reo_destination_17> REO remaps this
3187 
3188 			<enum 18 reo_destination_18> REO remaps this
3189 
3190 			<enum 19 reo_destination_19> REO remaps this
3191 
3192 			<enum 20 reo_destination_20> REO remaps this
3193 
3194 			<enum 21 reo_destination_21> REO remaps this
3195 
3196 			<enum 22 reo_destination_22> REO remaps this
3197 
3198 			<enum 23 reo_destination_23> REO remaps this
3199 
3200 			<enum 24 reo_destination_24> REO remaps this
3201 
3202 			<enum 25 reo_destination_25> REO remaps this
3203 
3204 			<enum 26 reo_destination_26> REO remaps this
3205 
3206 			<enum 27 reo_destination_27> REO remaps this
3207 
3208 			<enum 28 reo_destination_28> REO remaps this
3209 
3210 			<enum 29 reo_destination_29> REO remaps this
3211 
3212 			<enum 30 reo_destination_30> REO remaps this
3213 
3214 			<enum 31 reo_destination_31> REO remaps this
3215 
3216 
3217 
3218 			<legal all>
3219 */
3220 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078
3221 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
3222 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
3223 
3224 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
3225 
3226 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3227 			over multiple buffers, this field will be valid in the Last
3228 			buffer used by the MSDU
3229 
3230 
3231 
3232 			When set, REO shall drop this MSDU and not forward it to
3233 			any other ring...
3234 
3235 			<legal all>
3236 */
3237 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078
3238 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
3239 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
3240 
3241 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
3242 
3243 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3244 			over multiple buffers, this field will be valid in the Last
3245 			buffer used by the MSDU
3246 
3247 
3248 
3249 			Indicates that OLE found a valid SA entry for this MSDU
3250 
3251 			<legal all>
3252 */
3253 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078
3254 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
3255 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
3256 
3257 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
3258 
3259 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3260 			over multiple buffers, this field will be valid in the Last
3261 			buffer used by the MSDU
3262 
3263 
3264 
3265 			Indicates an unsuccessful MAC source address search due
3266 			to the expiring of the search timer for this MSDU
3267 
3268 			<legal all>
3269 */
3270 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078
3271 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
3272 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
3273 
3274 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
3275 
3276 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3277 			over multiple buffers, this field will be valid in the Last
3278 			buffer used by the MSDU
3279 
3280 
3281 
3282 			Indicates that OLE found a valid DA entry for this MSDU
3283 
3284 			<legal all>
3285 */
3286 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078
3287 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
3288 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
3289 
3290 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
3291 
3292 			Field Only valid if da_is_valid is set
3293 
3294 
3295 
3296 			Indicates the DA address was a Multicast of Broadcast
3297 			address for this MSDU
3298 
3299 			<legal all>
3300 */
3301 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078
3302 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
3303 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
3304 
3305 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
3306 
3307 			Parsed from RX_MSDU_END TLV . In the case MSDU spans
3308 			over multiple buffers, this field will be valid in the Last
3309 			buffer used by the MSDU
3310 
3311 
3312 
3313 			Indicates an unsuccessful MAC destination address search
3314 			due to the expiring of the search timer for this MSDU
3315 
3316 			<legal all>
3317 */
3318 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078
3319 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
3320 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
3321 
3322 /* Description		RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
3323 
3324 			<legal 0>
3325 */
3326 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078
3327 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28
3328 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
3329 
3330 /* Description		RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
3331 
3332 			<legal 0>
3333 */
3334 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000007c
3335 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0
3336 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
3337 
3338 
3339 #endif // _RX_MSDU_LINK_H_
3340