1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _RX_MSDU_END_H_
24 #define _RX_MSDU_END_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 
29 // ################ START SUMMARY #################
30 //
31 //	Dword	Fields
32 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
33 //	1	ip_hdr_chksum[15:0], tcp_udp_chksum[31:16]
34 //	2	key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16]
35 //	3	ext_wapi_pn_95_64[31:0]
36 //	4	ext_wapi_pn_127_96[31:0]
37 //	5	reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28]
38 //	6	ipv6_options_crc[31:0]
39 //	7	tcp_seq_number[31:0]
40 //	8	tcp_ack_number[31:0]
41 //	9	tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16]
42 //	10	da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_10a[15:14], l3_type[31:16]
43 //	11	rule_indication_31_0[31:0]
44 //	12	rule_indication_63_32[31:0]
45 //	13	sa_idx[15:0], da_idx_or_sw_peer_id[31:16]
46 //	14	msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26]
47 //	15	fse_metadata[31:0]
48 //	16	cce_metadata[15:0], sa_sw_peer_id[31:16]
49 //
50 // ################ END SUMMARY #################
51 
52 #define NUM_OF_DWORDS_RX_MSDU_END 17
53 
54 struct rx_msdu_end {
55              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
56                       sw_frame_group_id               :  7, //[8:2]
57                       reserved_0                      :  7, //[15:9]
58                       phy_ppdu_id                     : 16; //[31:16]
59              uint32_t ip_hdr_chksum                   : 16, //[15:0]
60                       tcp_udp_chksum                  : 16; //[31:16]
61              uint32_t key_id_octet                    :  8, //[7:0]
62                       cce_super_rule                  :  6, //[13:8]
63                       cce_classify_not_done_truncate  :  1, //[14]
64                       cce_classify_not_done_cce_dis   :  1, //[15]
65                       ext_wapi_pn_63_48               : 16; //[31:16]
66              uint32_t ext_wapi_pn_95_64               : 32; //[31:0]
67              uint32_t ext_wapi_pn_127_96              : 32; //[31:0]
68              uint32_t reported_mpdu_length            : 14, //[13:0]
69                       first_msdu                      :  1, //[14]
70                       last_msdu                       :  1, //[15]
71                       sa_idx_timeout                  :  1, //[16]
72                       da_idx_timeout                  :  1, //[17]
73                       msdu_limit_error                :  1, //[18]
74                       flow_idx_timeout                :  1, //[19]
75                       flow_idx_invalid                :  1, //[20]
76                       wifi_parser_error               :  1, //[21]
77                       amsdu_parser_error              :  1, //[22]
78                       sa_is_valid                     :  1, //[23]
79                       da_is_valid                     :  1, //[24]
80                       da_is_mcbc                      :  1, //[25]
81                       l3_header_padding               :  2, //[27:26]
82                       reserved_5a                     :  4; //[31:28]
83              uint32_t ipv6_options_crc                : 32; //[31:0]
84              uint32_t tcp_seq_number                  : 32; //[31:0]
85              uint32_t tcp_ack_number                  : 32; //[31:0]
86              uint32_t tcp_flag                        :  9, //[8:0]
87                       lro_eligible                    :  1, //[9]
88                       reserved_9a                     :  6, //[15:10]
89                       window_size                     : 16; //[31:16]
90              uint32_t da_offset                       :  6, //[5:0]
91                       sa_offset                       :  6, //[11:6]
92                       da_offset_valid                 :  1, //[12]
93                       sa_offset_valid                 :  1, //[13]
94                       reserved_10a                    :  2, //[15:14]
95                       l3_type                         : 16; //[31:16]
96              uint32_t rule_indication_31_0            : 32; //[31:0]
97              uint32_t rule_indication_63_32           : 32; //[31:0]
98              uint32_t sa_idx                          : 16, //[15:0]
99                       da_idx_or_sw_peer_id            : 16; //[31:16]
100              uint32_t msdu_drop                       :  1, //[0]
101                       reo_destination_indication      :  5, //[5:1]
102                       flow_idx                        : 20, //[25:6]
103                       reserved_14                     :  6; //[31:26]
104              uint32_t fse_metadata                    : 32; //[31:0]
105              uint32_t cce_metadata                    : 16, //[15:0]
106                       sa_sw_peer_id                   : 16; //[31:16]
107 };
108 
109 /*
110 
111 rxpcu_mpdu_filter_in_category
112 
113 			Field indicates what the reason was that this MPDU frame
114 			was allowed to come into the receive path by RXPCU
115 
116 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
117 			frame filter programming of rxpcu
118 
119 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
120 			regular frame filter and would have been dropped, were it
121 			not for the frame fitting into the 'monitor_client'
122 			category.
123 
124 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
125 			regular frame filter and also did not pass the
126 			rxpcu_monitor_client filter. It would have been dropped
127 			accept that it did pass the 'monitor_other' category.
128 
129 			<legal 0-2>
130 
131 sw_frame_group_id
132 
133 			SW processes frames based on certain classifications.
134 			This field indicates to what sw classification this MPDU is
135 			mapped.
136 
137 			The classification is given in priority order
138 
139 
140 
141 			<enum 0 sw_frame_group_NDP_frame>
142 
143 
144 
145 			<enum 1 sw_frame_group_Multicast_data>
146 
147 			<enum 2 sw_frame_group_Unicast_data>
148 
149 			<enum 3 sw_frame_group_Null_data > This includes mpdus
150 			of type Data Null as well as QoS Data Null
151 
152 
153 
154 			<enum 4 sw_frame_group_mgmt_0000 >
155 
156 			<enum 5 sw_frame_group_mgmt_0001 >
157 
158 			<enum 6 sw_frame_group_mgmt_0010 >
159 
160 			<enum 7 sw_frame_group_mgmt_0011 >
161 
162 			<enum 8 sw_frame_group_mgmt_0100 >
163 
164 			<enum 9 sw_frame_group_mgmt_0101 >
165 
166 			<enum 10 sw_frame_group_mgmt_0110 >
167 
168 			<enum 11 sw_frame_group_mgmt_0111 >
169 
170 			<enum 12 sw_frame_group_mgmt_1000 >
171 
172 			<enum 13 sw_frame_group_mgmt_1001 >
173 
174 			<enum 14 sw_frame_group_mgmt_1010 >
175 
176 			<enum 15 sw_frame_group_mgmt_1011 >
177 
178 			<enum 16 sw_frame_group_mgmt_1100 >
179 
180 			<enum 17 sw_frame_group_mgmt_1101 >
181 
182 			<enum 18 sw_frame_group_mgmt_1110 >
183 
184 			<enum 19 sw_frame_group_mgmt_1111 >
185 
186 
187 
188 			<enum 20 sw_frame_group_ctrl_0000 >
189 
190 			<enum 21 sw_frame_group_ctrl_0001 >
191 
192 			<enum 22 sw_frame_group_ctrl_0010 >
193 
194 			<enum 23 sw_frame_group_ctrl_0011 >
195 
196 			<enum 24 sw_frame_group_ctrl_0100 >
197 
198 			<enum 25 sw_frame_group_ctrl_0101 >
199 
200 			<enum 26 sw_frame_group_ctrl_0110 >
201 
202 			<enum 27 sw_frame_group_ctrl_0111 >
203 
204 			<enum 28 sw_frame_group_ctrl_1000 >
205 
206 			<enum 29 sw_frame_group_ctrl_1001 >
207 
208 			<enum 30 sw_frame_group_ctrl_1010 >
209 
210 			<enum 31 sw_frame_group_ctrl_1011 >
211 
212 			<enum 32 sw_frame_group_ctrl_1100 >
213 
214 			<enum 33 sw_frame_group_ctrl_1101 >
215 
216 			<enum 34 sw_frame_group_ctrl_1110 >
217 
218 			<enum 35 sw_frame_group_ctrl_1111 >
219 
220 
221 
222 			<enum 36 sw_frame_group_unsupported> This covers type 3
223 			and protocol version != 0
224 
225 
226 
227 
228 
229 
230 			<legal 0-37>
231 
232 reserved_0
233 
234 			<legal 0>
235 
236 phy_ppdu_id
237 
238 			A ppdu counter value that PHY increments for every PPDU
239 			received. The counter value wraps around
240 
241 			<legal all>
242 
243 ip_hdr_chksum
244 
245 			This can include the IP header checksum or the pseudo
246 			header checksum used by TCP/UDP checksum.
247 
248 			(with the first byte in the MSB and the second byte in
249 			the LSB, i.e. requiring a byte-swap for little-endian FW/SW
250 			w.r.t. the byte order in a packet)
251 
252 tcp_udp_chksum
253 
254 			The value of the computed TCP/UDP checksum.  A mode bit
255 			selects whether this checksum is the full checksum or the
256 			partial checksum which does not include the pseudo header.
257 			(with the first byte in the MSB and the second byte in the
258 			LSB, i.e. requiring a byte-swap for little-endian FW/SW
259 			w.r.t. the byte order in a packet)
260 
261 key_id_octet
262 
263 			The key ID octet from the IV.  Only valid when
264 			first_msdu is set.
265 
266 cce_super_rule
267 
268 			Indicates the super filter rule
269 
270 cce_classify_not_done_truncate
271 
272 			Classification failed due to truncated frame
273 
274 cce_classify_not_done_cce_dis
275 
276 			Classification failed due to CCE global disable
277 
278 ext_wapi_pn_63_48
279 
280 			Extension PN (packet number) which is only used by WAPI.
281 			This corresponds to WAPI PN bits [63:48] (pn6 and pn7).
282 			The WAPI PN bits [63:0] are in the pn field of the
283 			rx_mpdu_start descriptor.
284 
285 ext_wapi_pn_95_64
286 
287 			Extension PN (packet number) which is only used by WAPI.
288 			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
289 			and pn11).
290 
291 ext_wapi_pn_127_96
292 
293 			Extension PN (packet number) which is only used by WAPI.
294 			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
295 			pn14, pn15).
296 
297 reported_mpdu_length
298 
299 			MPDU length before decapsulation.  Only valid when
300 			first_msdu is set.  This field is taken directly from the
301 			length field of the A-MPDU delimiter or the preamble length
302 			field for non-A-MPDU frames.
303 
304 first_msdu
305 
306 			Indicates the first MSDU of A-MSDU.  If both first_msdu
307 			and last_msdu are set in the MSDU then this is a
308 			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
309 			A-MSDU shall have both first_mpdu and last_mpdu bits set to
310 			0.
311 
312 last_msdu
313 
314 			Indicates the last MSDU of the A-MSDU.  MPDU end status
315 			is only valid when last_msdu is set.
316 
317 sa_idx_timeout
318 
319 			Indicates an unsuccessful MAC source address search due
320 			to the expiring of the search timer.
321 
322 da_idx_timeout
323 
324 			Indicates an unsuccessful MAC destination address search
325 			due to the expiring of the search timer.
326 
327 msdu_limit_error
328 
329 			Indicates that the MSDU threshold was exceeded and thus
330 			all the rest of the MSDUs will not be scattered and will not
331 			be decapsulated but will be DMA'ed in RAW format as a single
332 			MSDU buffer
333 
334 flow_idx_timeout
335 
336 			Indicates an unsuccessful flow search due to the
337 			expiring of the search timer.
338 
339 			<legal all>
340 
341 flow_idx_invalid
342 
343 			flow id is not valid
344 
345 			<legal all>
346 
347 wifi_parser_error
348 
349 			Indicates that the WiFi frame has one of the following
350 			errors
351 
352 			o has less than minimum allowed bytes as per standard
353 
354 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
355 
356 			<legal all>
357 
358 amsdu_parser_error
359 
360 			A-MSDU could not be properly de-agregated.
361 
362 			<legal all>
363 
364 sa_is_valid
365 
366 			Indicates that OLE found a valid SA entry
367 
368 da_is_valid
369 
370 			Indicates that OLE found a valid DA entry
371 
372 da_is_mcbc
373 
374 			Field Only valid if da_is_valid is set
375 
376 
377 
378 			Indicates the DA address was a Multicast of Broadcast
379 			address.
380 
381 l3_header_padding
382 
383 			Number of bytes padded  to make sure that the L3 header
384 			will always start of a Dword   boundary
385 
386 reserved_5a
387 
388 			<legal 0>
389 
390 ipv6_options_crc
391 
392 			32 bit CRC computed out of  IP v6 extension headers
393 
394 tcp_seq_number
395 
396 			TCP sequence number (as a number assembled from a TCP
397 			packet in big-endian order, i.e. requiring a byte-swap for
398 			little-endian FW/SW w.r.t. the byte order in a packet)
399 
400 tcp_ack_number
401 
402 			TCP acknowledge number (as a number assembled from a TCP
403 			packet in big-endian order, i.e. requiring a byte-swap for
404 			little-endian FW/SW w.r.t. the byte order in a packet)
405 
406 tcp_flag
407 
408 			TCP flags
409 
410 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
411 			in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
412 			i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
413 			the byte order in a packet)
414 
415 lro_eligible
416 
417 			Computed out of TCP and IP fields to indicate that this
418 			MSDU is eligible for  LRO
419 
420 reserved_9a
421 
422 			NOTE: DO not assign a field... Internally used in
423 			RXOLE..
424 
425 			<legal 0>
426 
427 window_size
428 
429 			TCP receive window size (as a number assembled from a
430 			TCP packet in big-endian order, i.e. requiring a byte-swap
431 			for little-endian FW/SW w.r.t. the byte order in a packet)
432 
433 da_offset
434 
435 			Offset into MSDU buffer for DA
436 
437 sa_offset
438 
439 			Offset into MSDU buffer for SA
440 
441 da_offset_valid
442 
443 			da_offset field is valid. This will be set to 0 in case
444 			of a dynamic A-MSDU when DA is compressed
445 
446 sa_offset_valid
447 
448 			sa_offset field is valid. This will be set to 0 in case
449 			of a dynamic A-MSDU when SA is compressed
450 
451 reserved_10a
452 
453 			<legal 0>
454 
455 l3_type
456 
457 			The 16-bit type value indicating the type of L3 later
458 			extracted from LLC/SNAP, set to zero if SNAP is not
459 			available
460 
461 rule_indication_31_0
462 
463 			Bitmap indicating which of rules 31-0 have matched
464 
465 rule_indication_63_32
466 
467 			Bitmap indicating which of rules 63-32 have matched
468 
469 sa_idx
470 
471 			The offset in the address table which matches the MAC
472 			source address.
473 
474 da_idx_or_sw_peer_id
475 
476 			Based on a register configuration in RXOLE, this field
477 			will contain:
478 
479 
480 
481 			The offset in the address table which matches the
482 			destination address
483 
484 			OR
485 
486 			Sw_peer_id from the address search entry corresponding
487 			to the DA of the MSDU
488 
489 msdu_drop
490 
491 			When set, REO shall drop this MSDU and not forward it to
492 			any other ring...
493 
494 			<legal all>
495 
496 reo_destination_indication
497 
498 			The ID of the REO exit ring where the MSDU frame shall
499 			push after (MPDU level) reordering has finished.
500 
501 
502 
503 			<enum 0 reo_destination_tcl> Reo will push the frame
504 			into the REO2TCL ring
505 
506 			<enum 1 reo_destination_sw1> Reo will push the frame
507 			into the REO2SW1 ring
508 
509 			<enum 2 reo_destination_sw2> Reo will push the frame
510 			into the REO2SW1 ring
511 
512 			<enum 3 reo_destination_sw3> Reo will push the frame
513 			into the REO2SW1 ring
514 
515 			<enum 4 reo_destination_sw4> Reo will push the frame
516 			into the REO2SW1 ring
517 
518 			<enum 5 reo_destination_release> Reo will push the frame
519 			into the REO_release ring
520 
521 			<enum 6 reo_destination_fw> Reo will push the frame into
522 			the REO2FW ring
523 
524 			<enum 7 reo_destination_7> REO remaps this
525 
526 			<enum 8 reo_destination_8> REO remaps this <enum 9
527 			reo_destination_9> REO remaps this <enum 10
528 			reo_destination_10> REO remaps this
529 
530 			<enum 11 reo_destination_11> REO remaps this
531 
532 			<enum 12 reo_destination_12> REO remaps this <enum 13
533 			reo_destination_13> REO remaps this
534 
535 			<enum 14 reo_destination_14> REO remaps this
536 
537 			<enum 15 reo_destination_15> REO remaps this
538 
539 			<enum 16 reo_destination_16> REO remaps this
540 
541 			<enum 17 reo_destination_17> REO remaps this
542 
543 			<enum 18 reo_destination_18> REO remaps this
544 
545 			<enum 19 reo_destination_19> REO remaps this
546 
547 			<enum 20 reo_destination_20> REO remaps this
548 
549 			<enum 21 reo_destination_21> REO remaps this
550 
551 			<enum 22 reo_destination_22> REO remaps this
552 
553 			<enum 23 reo_destination_23> REO remaps this
554 
555 			<enum 24 reo_destination_24> REO remaps this
556 
557 			<enum 25 reo_destination_25> REO remaps this
558 
559 			<enum 26 reo_destination_26> REO remaps this
560 
561 			<enum 27 reo_destination_27> REO remaps this
562 
563 			<enum 28 reo_destination_28> REO remaps this
564 
565 			<enum 29 reo_destination_29> REO remaps this
566 
567 			<enum 30 reo_destination_30> REO remaps this
568 
569 			<enum 31 reo_destination_31> REO remaps this
570 
571 
572 
573 			<legal all>
574 
575 flow_idx
576 
577 			Flow table index
578 
579 			<legal all>
580 
581 reserved_14
582 
583 			<legal 0>
584 
585 fse_metadata
586 
587 			FSE related meta data:
588 
589 			<legal all>
590 
591 cce_metadata
592 
593 			CCE related meta data:
594 
595 			<legal all>
596 
597 sa_sw_peer_id
598 
599 			sw_peer_id from the address search entry corresponding
600 			to the source address of the MSDU
601 
602 			<legal 0>
603 */
604 
605 
606 /* Description		RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
607 
608 			Field indicates what the reason was that this MPDU frame
609 			was allowed to come into the receive path by RXPCU
610 
611 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
612 			frame filter programming of rxpcu
613 
614 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
615 			regular frame filter and would have been dropped, were it
616 			not for the frame fitting into the 'monitor_client'
617 			category.
618 
619 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
620 			regular frame filter and also did not pass the
621 			rxpcu_monitor_client filter. It would have been dropped
622 			accept that it did pass the 'monitor_other' category.
623 
624 			<legal 0-2>
625 */
626 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
627 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
628 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
629 
630 /* Description		RX_MSDU_END_0_SW_FRAME_GROUP_ID
631 
632 			SW processes frames based on certain classifications.
633 			This field indicates to what sw classification this MPDU is
634 			mapped.
635 
636 			The classification is given in priority order
637 
638 
639 
640 			<enum 0 sw_frame_group_NDP_frame>
641 
642 
643 
644 			<enum 1 sw_frame_group_Multicast_data>
645 
646 			<enum 2 sw_frame_group_Unicast_data>
647 
648 			<enum 3 sw_frame_group_Null_data > This includes mpdus
649 			of type Data Null as well as QoS Data Null
650 
651 
652 
653 			<enum 4 sw_frame_group_mgmt_0000 >
654 
655 			<enum 5 sw_frame_group_mgmt_0001 >
656 
657 			<enum 6 sw_frame_group_mgmt_0010 >
658 
659 			<enum 7 sw_frame_group_mgmt_0011 >
660 
661 			<enum 8 sw_frame_group_mgmt_0100 >
662 
663 			<enum 9 sw_frame_group_mgmt_0101 >
664 
665 			<enum 10 sw_frame_group_mgmt_0110 >
666 
667 			<enum 11 sw_frame_group_mgmt_0111 >
668 
669 			<enum 12 sw_frame_group_mgmt_1000 >
670 
671 			<enum 13 sw_frame_group_mgmt_1001 >
672 
673 			<enum 14 sw_frame_group_mgmt_1010 >
674 
675 			<enum 15 sw_frame_group_mgmt_1011 >
676 
677 			<enum 16 sw_frame_group_mgmt_1100 >
678 
679 			<enum 17 sw_frame_group_mgmt_1101 >
680 
681 			<enum 18 sw_frame_group_mgmt_1110 >
682 
683 			<enum 19 sw_frame_group_mgmt_1111 >
684 
685 
686 
687 			<enum 20 sw_frame_group_ctrl_0000 >
688 
689 			<enum 21 sw_frame_group_ctrl_0001 >
690 
691 			<enum 22 sw_frame_group_ctrl_0010 >
692 
693 			<enum 23 sw_frame_group_ctrl_0011 >
694 
695 			<enum 24 sw_frame_group_ctrl_0100 >
696 
697 			<enum 25 sw_frame_group_ctrl_0101 >
698 
699 			<enum 26 sw_frame_group_ctrl_0110 >
700 
701 			<enum 27 sw_frame_group_ctrl_0111 >
702 
703 			<enum 28 sw_frame_group_ctrl_1000 >
704 
705 			<enum 29 sw_frame_group_ctrl_1001 >
706 
707 			<enum 30 sw_frame_group_ctrl_1010 >
708 
709 			<enum 31 sw_frame_group_ctrl_1011 >
710 
711 			<enum 32 sw_frame_group_ctrl_1100 >
712 
713 			<enum 33 sw_frame_group_ctrl_1101 >
714 
715 			<enum 34 sw_frame_group_ctrl_1110 >
716 
717 			<enum 35 sw_frame_group_ctrl_1111 >
718 
719 
720 
721 			<enum 36 sw_frame_group_unsupported> This covers type 3
722 			and protocol version != 0
723 
724 
725 
726 
727 
728 
729 			<legal 0-37>
730 */
731 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
732 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
733 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
734 
735 /* Description		RX_MSDU_END_0_RESERVED_0
736 
737 			<legal 0>
738 */
739 #define RX_MSDU_END_0_RESERVED_0_OFFSET                              0x00000000
740 #define RX_MSDU_END_0_RESERVED_0_LSB                                 9
741 #define RX_MSDU_END_0_RESERVED_0_MASK                                0x0000fe00
742 
743 /* Description		RX_MSDU_END_0_PHY_PPDU_ID
744 
745 			A ppdu counter value that PHY increments for every PPDU
746 			received. The counter value wraps around
747 
748 			<legal all>
749 */
750 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
751 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB                                16
752 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
753 
754 /* Description		RX_MSDU_END_1_IP_HDR_CHKSUM
755 
756 			This can include the IP header checksum or the pseudo
757 			header checksum used by TCP/UDP checksum.
758 
759 			(with the first byte in the MSB and the second byte in
760 			the LSB, i.e. requiring a byte-swap for little-endian FW/SW
761 			w.r.t. the byte order in a packet)
762 */
763 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET                           0x00000004
764 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB                              0
765 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK                             0x0000ffff
766 
767 /* Description		RX_MSDU_END_1_TCP_UDP_CHKSUM
768 
769 			The value of the computed TCP/UDP checksum.  A mode bit
770 			selects whether this checksum is the full checksum or the
771 			partial checksum which does not include the pseudo header.
772 			(with the first byte in the MSB and the second byte in the
773 			LSB, i.e. requiring a byte-swap for little-endian FW/SW
774 			w.r.t. the byte order in a packet)
775 */
776 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET                          0x00000004
777 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB                             16
778 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK                            0xffff0000
779 
780 /* Description		RX_MSDU_END_2_KEY_ID_OCTET
781 
782 			The key ID octet from the IV.  Only valid when
783 			first_msdu is set.
784 */
785 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET                            0x00000008
786 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB                               0
787 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK                              0x000000ff
788 
789 /* Description		RX_MSDU_END_2_CCE_SUPER_RULE
790 
791 			Indicates the super filter rule
792 */
793 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET                          0x00000008
794 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB                             8
795 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK                            0x00003f00
796 
797 /* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE
798 
799 			Classification failed due to truncated frame
800 */
801 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET          0x00000008
802 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB             14
803 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK            0x00004000
804 
805 /* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS
806 
807 			Classification failed due to CCE global disable
808 */
809 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET           0x00000008
810 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB              15
811 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK             0x00008000
812 
813 /* Description		RX_MSDU_END_2_EXT_WAPI_PN_63_48
814 
815 			Extension PN (packet number) which is only used by WAPI.
816 			This corresponds to WAPI PN bits [63:48] (pn6 and pn7).
817 			The WAPI PN bits [63:0] are in the pn field of the
818 			rx_mpdu_start descriptor.
819 */
820 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET                       0x00000008
821 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB                          16
822 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK                         0xffff0000
823 
824 /* Description		RX_MSDU_END_3_EXT_WAPI_PN_95_64
825 
826 			Extension PN (packet number) which is only used by WAPI.
827 			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
828 			and pn11).
829 */
830 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET                       0x0000000c
831 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB                          0
832 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK                         0xffffffff
833 
834 /* Description		RX_MSDU_END_4_EXT_WAPI_PN_127_96
835 
836 			Extension PN (packet number) which is only used by WAPI.
837 			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
838 			pn14, pn15).
839 */
840 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET                      0x00000010
841 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB                         0
842 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK                        0xffffffff
843 
844 /* Description		RX_MSDU_END_5_REPORTED_MPDU_LENGTH
845 
846 			MPDU length before decapsulation.  Only valid when
847 			first_msdu is set.  This field is taken directly from the
848 			length field of the A-MPDU delimiter or the preamble length
849 			field for non-A-MPDU frames.
850 */
851 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET                    0x00000014
852 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB                       0
853 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK                      0x00003fff
854 
855 /* Description		RX_MSDU_END_5_FIRST_MSDU
856 
857 			Indicates the first MSDU of A-MSDU.  If both first_msdu
858 			and last_msdu are set in the MSDU then this is a
859 			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
860 			A-MSDU shall have both first_mpdu and last_mpdu bits set to
861 			0.
862 */
863 #define RX_MSDU_END_5_FIRST_MSDU_OFFSET                              0x00000014
864 #define RX_MSDU_END_5_FIRST_MSDU_LSB                                 14
865 #define RX_MSDU_END_5_FIRST_MSDU_MASK                                0x00004000
866 
867 /* Description		RX_MSDU_END_5_LAST_MSDU
868 
869 			Indicates the last MSDU of the A-MSDU.  MPDU end status
870 			is only valid when last_msdu is set.
871 */
872 #define RX_MSDU_END_5_LAST_MSDU_OFFSET                               0x00000014
873 #define RX_MSDU_END_5_LAST_MSDU_LSB                                  15
874 #define RX_MSDU_END_5_LAST_MSDU_MASK                                 0x00008000
875 
876 /* Description		RX_MSDU_END_5_SA_IDX_TIMEOUT
877 
878 			Indicates an unsuccessful MAC source address search due
879 			to the expiring of the search timer.
880 */
881 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET                          0x00000014
882 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB                             16
883 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK                            0x00010000
884 
885 /* Description		RX_MSDU_END_5_DA_IDX_TIMEOUT
886 
887 			Indicates an unsuccessful MAC destination address search
888 			due to the expiring of the search timer.
889 */
890 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET                          0x00000014
891 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB                             17
892 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK                            0x00020000
893 
894 /* Description		RX_MSDU_END_5_MSDU_LIMIT_ERROR
895 
896 			Indicates that the MSDU threshold was exceeded and thus
897 			all the rest of the MSDUs will not be scattered and will not
898 			be decapsulated but will be DMA'ed in RAW format as a single
899 			MSDU buffer
900 */
901 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET                        0x00000014
902 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB                           18
903 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK                          0x00040000
904 
905 /* Description		RX_MSDU_END_5_FLOW_IDX_TIMEOUT
906 
907 			Indicates an unsuccessful flow search due to the
908 			expiring of the search timer.
909 
910 			<legal all>
911 */
912 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET                        0x00000014
913 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB                           19
914 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK                          0x00080000
915 
916 /* Description		RX_MSDU_END_5_FLOW_IDX_INVALID
917 
918 			flow id is not valid
919 
920 			<legal all>
921 */
922 #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET                        0x00000014
923 #define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB                           20
924 #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK                          0x00100000
925 
926 /* Description		RX_MSDU_END_5_WIFI_PARSER_ERROR
927 
928 			Indicates that the WiFi frame has one of the following
929 			errors
930 
931 			o has less than minimum allowed bytes as per standard
932 
933 			o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
934 
935 			<legal all>
936 */
937 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET                       0x00000014
938 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB                          21
939 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK                         0x00200000
940 
941 /* Description		RX_MSDU_END_5_AMSDU_PARSER_ERROR
942 
943 			A-MSDU could not be properly de-agregated.
944 
945 			<legal all>
946 */
947 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET                      0x00000014
948 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB                         22
949 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK                        0x00400000
950 
951 /* Description		RX_MSDU_END_5_SA_IS_VALID
952 
953 			Indicates that OLE found a valid SA entry
954 */
955 #define RX_MSDU_END_5_SA_IS_VALID_OFFSET                             0x00000014
956 #define RX_MSDU_END_5_SA_IS_VALID_LSB                                23
957 #define RX_MSDU_END_5_SA_IS_VALID_MASK                               0x00800000
958 
959 /* Description		RX_MSDU_END_5_DA_IS_VALID
960 
961 			Indicates that OLE found a valid DA entry
962 */
963 #define RX_MSDU_END_5_DA_IS_VALID_OFFSET                             0x00000014
964 #define RX_MSDU_END_5_DA_IS_VALID_LSB                                24
965 #define RX_MSDU_END_5_DA_IS_VALID_MASK                               0x01000000
966 
967 /* Description		RX_MSDU_END_5_DA_IS_MCBC
968 
969 			Field Only valid if da_is_valid is set
970 
971 
972 
973 			Indicates the DA address was a Multicast of Broadcast
974 			address.
975 */
976 #define RX_MSDU_END_5_DA_IS_MCBC_OFFSET                              0x00000014
977 #define RX_MSDU_END_5_DA_IS_MCBC_LSB                                 25
978 #define RX_MSDU_END_5_DA_IS_MCBC_MASK                                0x02000000
979 
980 /* Description		RX_MSDU_END_5_L3_HEADER_PADDING
981 
982 			Number of bytes padded  to make sure that the L3 header
983 			will always start of a Dword   boundary
984 */
985 #define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET                       0x00000014
986 #define RX_MSDU_END_5_L3_HEADER_PADDING_LSB                          26
987 #define RX_MSDU_END_5_L3_HEADER_PADDING_MASK                         0x0c000000
988 
989 /* Description		RX_MSDU_END_5_RESERVED_5A
990 
991 			<legal 0>
992 */
993 #define RX_MSDU_END_5_RESERVED_5A_OFFSET                             0x00000014
994 #define RX_MSDU_END_5_RESERVED_5A_LSB                                28
995 #define RX_MSDU_END_5_RESERVED_5A_MASK                               0xf0000000
996 
997 /* Description		RX_MSDU_END_6_IPV6_OPTIONS_CRC
998 
999 			32 bit CRC computed out of  IP v6 extension headers
1000 */
1001 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET                        0x00000018
1002 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB                           0
1003 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK                          0xffffffff
1004 
1005 /* Description		RX_MSDU_END_7_TCP_SEQ_NUMBER
1006 
1007 			TCP sequence number (as a number assembled from a TCP
1008 			packet in big-endian order, i.e. requiring a byte-swap for
1009 			little-endian FW/SW w.r.t. the byte order in a packet)
1010 */
1011 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET                          0x0000001c
1012 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB                             0
1013 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK                            0xffffffff
1014 
1015 /* Description		RX_MSDU_END_8_TCP_ACK_NUMBER
1016 
1017 			TCP acknowledge number (as a number assembled from a TCP
1018 			packet in big-endian order, i.e. requiring a byte-swap for
1019 			little-endian FW/SW w.r.t. the byte order in a packet)
1020 */
1021 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET                          0x00000020
1022 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB                             0
1023 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK                            0xffffffff
1024 
1025 /* Description		RX_MSDU_END_9_TCP_FLAG
1026 
1027 			TCP flags
1028 
1029 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
1030 			in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
1031 			i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
1032 			the byte order in a packet)
1033 */
1034 #define RX_MSDU_END_9_TCP_FLAG_OFFSET                                0x00000024
1035 #define RX_MSDU_END_9_TCP_FLAG_LSB                                   0
1036 #define RX_MSDU_END_9_TCP_FLAG_MASK                                  0x000001ff
1037 
1038 /* Description		RX_MSDU_END_9_LRO_ELIGIBLE
1039 
1040 			Computed out of TCP and IP fields to indicate that this
1041 			MSDU is eligible for  LRO
1042 */
1043 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET                            0x00000024
1044 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB                               9
1045 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK                              0x00000200
1046 
1047 /* Description		RX_MSDU_END_9_RESERVED_9A
1048 
1049 			NOTE: DO not assign a field... Internally used in
1050 			RXOLE..
1051 
1052 			<legal 0>
1053 */
1054 #define RX_MSDU_END_9_RESERVED_9A_OFFSET                             0x00000024
1055 #define RX_MSDU_END_9_RESERVED_9A_LSB                                10
1056 #define RX_MSDU_END_9_RESERVED_9A_MASK                               0x0000fc00
1057 
1058 /* Description		RX_MSDU_END_9_WINDOW_SIZE
1059 
1060 			TCP receive window size (as a number assembled from a
1061 			TCP packet in big-endian order, i.e. requiring a byte-swap
1062 			for little-endian FW/SW w.r.t. the byte order in a packet)
1063 */
1064 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET                             0x00000024
1065 #define RX_MSDU_END_9_WINDOW_SIZE_LSB                                16
1066 #define RX_MSDU_END_9_WINDOW_SIZE_MASK                               0xffff0000
1067 
1068 /* Description		RX_MSDU_END_10_DA_OFFSET
1069 
1070 			Offset into MSDU buffer for DA
1071 */
1072 #define RX_MSDU_END_10_DA_OFFSET_OFFSET                              0x00000028
1073 #define RX_MSDU_END_10_DA_OFFSET_LSB                                 0
1074 #define RX_MSDU_END_10_DA_OFFSET_MASK                                0x0000003f
1075 
1076 /* Description		RX_MSDU_END_10_SA_OFFSET
1077 
1078 			Offset into MSDU buffer for SA
1079 */
1080 #define RX_MSDU_END_10_SA_OFFSET_OFFSET                              0x00000028
1081 #define RX_MSDU_END_10_SA_OFFSET_LSB                                 6
1082 #define RX_MSDU_END_10_SA_OFFSET_MASK                                0x00000fc0
1083 
1084 /* Description		RX_MSDU_END_10_DA_OFFSET_VALID
1085 
1086 			da_offset field is valid. This will be set to 0 in case
1087 			of a dynamic A-MSDU when DA is compressed
1088 */
1089 #define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET                        0x00000028
1090 #define RX_MSDU_END_10_DA_OFFSET_VALID_LSB                           12
1091 #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK                          0x00001000
1092 
1093 /* Description		RX_MSDU_END_10_SA_OFFSET_VALID
1094 
1095 			sa_offset field is valid. This will be set to 0 in case
1096 			of a dynamic A-MSDU when SA is compressed
1097 */
1098 #define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET                        0x00000028
1099 #define RX_MSDU_END_10_SA_OFFSET_VALID_LSB                           13
1100 #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK                          0x00002000
1101 
1102 /* Description		RX_MSDU_END_10_RESERVED_10A
1103 
1104 			<legal 0>
1105 */
1106 #define RX_MSDU_END_10_RESERVED_10A_OFFSET                           0x00000028
1107 #define RX_MSDU_END_10_RESERVED_10A_LSB                              14
1108 #define RX_MSDU_END_10_RESERVED_10A_MASK                             0x0000c000
1109 
1110 /* Description		RX_MSDU_END_10_L3_TYPE
1111 
1112 			The 16-bit type value indicating the type of L3 later
1113 			extracted from LLC/SNAP, set to zero if SNAP is not
1114 			available
1115 */
1116 #define RX_MSDU_END_10_L3_TYPE_OFFSET                                0x00000028
1117 #define RX_MSDU_END_10_L3_TYPE_LSB                                   16
1118 #define RX_MSDU_END_10_L3_TYPE_MASK                                  0xffff0000
1119 
1120 /* Description		RX_MSDU_END_11_RULE_INDICATION_31_0
1121 
1122 			Bitmap indicating which of rules 31-0 have matched
1123 */
1124 #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET                   0x0000002c
1125 #define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB                      0
1126 #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK                     0xffffffff
1127 
1128 /* Description		RX_MSDU_END_12_RULE_INDICATION_63_32
1129 
1130 			Bitmap indicating which of rules 63-32 have matched
1131 */
1132 #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET                  0x00000030
1133 #define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB                     0
1134 #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK                    0xffffffff
1135 
1136 /* Description		RX_MSDU_END_13_SA_IDX
1137 
1138 			The offset in the address table which matches the MAC
1139 			source address.
1140 */
1141 #define RX_MSDU_END_13_SA_IDX_OFFSET                                 0x00000034
1142 #define RX_MSDU_END_13_SA_IDX_LSB                                    0
1143 #define RX_MSDU_END_13_SA_IDX_MASK                                   0x0000ffff
1144 
1145 /* Description		RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID
1146 
1147 			Based on a register configuration in RXOLE, this field
1148 			will contain:
1149 
1150 
1151 
1152 			The offset in the address table which matches the
1153 			destination address
1154 
1155 			OR
1156 
1157 			Sw_peer_id from the address search entry corresponding
1158 			to the DA of the MSDU
1159 */
1160 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET                   0x00000034
1161 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB                      16
1162 #define RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK                     0xffff0000
1163 
1164 /* Description		RX_MSDU_END_14_MSDU_DROP
1165 
1166 			When set, REO shall drop this MSDU and not forward it to
1167 			any other ring...
1168 
1169 			<legal all>
1170 */
1171 #define RX_MSDU_END_14_MSDU_DROP_OFFSET                              0x00000038
1172 #define RX_MSDU_END_14_MSDU_DROP_LSB                                 0
1173 #define RX_MSDU_END_14_MSDU_DROP_MASK                                0x00000001
1174 
1175 /* Description		RX_MSDU_END_14_REO_DESTINATION_INDICATION
1176 
1177 			The ID of the REO exit ring where the MSDU frame shall
1178 			push after (MPDU level) reordering has finished.
1179 
1180 
1181 
1182 			<enum 0 reo_destination_tcl> Reo will push the frame
1183 			into the REO2TCL ring
1184 
1185 			<enum 1 reo_destination_sw1> Reo will push the frame
1186 			into the REO2SW1 ring
1187 
1188 			<enum 2 reo_destination_sw2> Reo will push the frame
1189 			into the REO2SW1 ring
1190 
1191 			<enum 3 reo_destination_sw3> Reo will push the frame
1192 			into the REO2SW1 ring
1193 
1194 			<enum 4 reo_destination_sw4> Reo will push the frame
1195 			into the REO2SW1 ring
1196 
1197 			<enum 5 reo_destination_release> Reo will push the frame
1198 			into the REO_release ring
1199 
1200 			<enum 6 reo_destination_fw> Reo will push the frame into
1201 			the REO2FW ring
1202 
1203 			<enum 7 reo_destination_7> REO remaps this
1204 
1205 			<enum 8 reo_destination_8> REO remaps this <enum 9
1206 			reo_destination_9> REO remaps this <enum 10
1207 			reo_destination_10> REO remaps this
1208 
1209 			<enum 11 reo_destination_11> REO remaps this
1210 
1211 			<enum 12 reo_destination_12> REO remaps this <enum 13
1212 			reo_destination_13> REO remaps this
1213 
1214 			<enum 14 reo_destination_14> REO remaps this
1215 
1216 			<enum 15 reo_destination_15> REO remaps this
1217 
1218 			<enum 16 reo_destination_16> REO remaps this
1219 
1220 			<enum 17 reo_destination_17> REO remaps this
1221 
1222 			<enum 18 reo_destination_18> REO remaps this
1223 
1224 			<enum 19 reo_destination_19> REO remaps this
1225 
1226 			<enum 20 reo_destination_20> REO remaps this
1227 
1228 			<enum 21 reo_destination_21> REO remaps this
1229 
1230 			<enum 22 reo_destination_22> REO remaps this
1231 
1232 			<enum 23 reo_destination_23> REO remaps this
1233 
1234 			<enum 24 reo_destination_24> REO remaps this
1235 
1236 			<enum 25 reo_destination_25> REO remaps this
1237 
1238 			<enum 26 reo_destination_26> REO remaps this
1239 
1240 			<enum 27 reo_destination_27> REO remaps this
1241 
1242 			<enum 28 reo_destination_28> REO remaps this
1243 
1244 			<enum 29 reo_destination_29> REO remaps this
1245 
1246 			<enum 30 reo_destination_30> REO remaps this
1247 
1248 			<enum 31 reo_destination_31> REO remaps this
1249 
1250 
1251 
1252 			<legal all>
1253 */
1254 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET             0x00000038
1255 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB                1
1256 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK               0x0000003e
1257 
1258 /* Description		RX_MSDU_END_14_FLOW_IDX
1259 
1260 			Flow table index
1261 
1262 			<legal all>
1263 */
1264 #define RX_MSDU_END_14_FLOW_IDX_OFFSET                               0x00000038
1265 #define RX_MSDU_END_14_FLOW_IDX_LSB                                  6
1266 #define RX_MSDU_END_14_FLOW_IDX_MASK                                 0x03ffffc0
1267 
1268 /* Description		RX_MSDU_END_14_RESERVED_14
1269 
1270 			<legal 0>
1271 */
1272 #define RX_MSDU_END_14_RESERVED_14_OFFSET                            0x00000038
1273 #define RX_MSDU_END_14_RESERVED_14_LSB                               26
1274 #define RX_MSDU_END_14_RESERVED_14_MASK                              0xfc000000
1275 
1276 /* Description		RX_MSDU_END_15_FSE_METADATA
1277 
1278 			FSE related meta data:
1279 
1280 			<legal all>
1281 */
1282 #define RX_MSDU_END_15_FSE_METADATA_OFFSET                           0x0000003c
1283 #define RX_MSDU_END_15_FSE_METADATA_LSB                              0
1284 #define RX_MSDU_END_15_FSE_METADATA_MASK                             0xffffffff
1285 
1286 /* Description		RX_MSDU_END_16_CCE_METADATA
1287 
1288 			CCE related meta data:
1289 
1290 			<legal all>
1291 */
1292 #define RX_MSDU_END_16_CCE_METADATA_OFFSET                           0x00000040
1293 #define RX_MSDU_END_16_CCE_METADATA_LSB                              0
1294 #define RX_MSDU_END_16_CCE_METADATA_MASK                             0x0000ffff
1295 
1296 /* Description		RX_MSDU_END_16_SA_SW_PEER_ID
1297 
1298 			sw_peer_id from the address search entry corresponding
1299 			to the source address of the MSDU
1300 
1301 			<legal 0>
1302 */
1303 #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET                          0x00000040
1304 #define RX_MSDU_END_16_SA_SW_PEER_ID_LSB                             16
1305 #define RX_MSDU_END_16_SA_SW_PEER_ID_MASK                            0xffff0000
1306 
1307 
1308 #endif // _RX_MSDU_END_H_
1309