1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_MPDU_START_H_ 24 #define _RX_MPDU_START_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "rx_mpdu_info.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0-22 struct rx_mpdu_info rx_mpdu_info_details; 34 // 23 raw_mpdu[0], reserved_23[31:1] 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_RX_MPDU_START 24 39 40 struct rx_mpdu_start { 41 struct rx_mpdu_info rx_mpdu_info_details; 42 uint32_t raw_mpdu : 1, //[0] 43 reserved_23 : 31; //[31:1] 44 }; 45 46 /* 47 48 struct rx_mpdu_info rx_mpdu_info_details 49 50 Structure containing all the MPDU header details that 51 might be needed for other modules further down the received 52 path 53 54 raw_mpdu 55 56 Set by OLE when it has not performed any .11 to .3 57 header conversion on this MPDU. 58 59 <legal all> 60 61 reserved_23 62 63 <legal 0> 64 */ 65 66 67 /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */ 68 69 70 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY 71 72 Field indicates what the reason was that this MPDU frame 73 was allowed to come into the receive path by RXPCU 74 75 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 76 frame filter programming of rxpcu 77 78 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 79 regular frame filter and would have been dropped, were it 80 not for the frame fitting into the 'monitor_client' 81 category. 82 83 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 84 regular frame filter and also did not pass the 85 rxpcu_monitor_client filter. It would have been dropped 86 accept that it did pass the 'monitor_other' category. 87 88 89 90 Note: for ndp frame, if it was expected because the 91 preceding NDPA was filter_pass, the setting 92 rxpcu_filter_pass will be used. This setting will also be 93 used for every ndp frame in case Promiscuous mode is 94 enabled. 95 96 97 98 In case promiscuous is not enabled, and an NDP is not 99 preceded by a NPDA filter pass frame, the only other setting 100 that could appear here for the NDP is rxpcu_monitor_other. 101 102 (rxpcu has a configuration bit specifically for this 103 scenario) 104 105 106 107 Note: for 108 109 <legal 0-2> 110 */ 111 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 112 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 113 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 114 115 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID 116 117 SW processes frames based on certain classifications. 118 This field indicates to what sw classification this MPDU is 119 mapped. 120 121 The classification is given in priority order 122 123 124 125 <enum 0 sw_frame_group_NDP_frame> Note: The 126 corresponding Rxpcu_Mpdu_filter_in_category can be 127 rxpcu_filter_pass or rxpcu_monitor_other 128 129 130 131 <enum 1 sw_frame_group_Multicast_data> 132 133 <enum 2 sw_frame_group_Unicast_data> 134 135 <enum 3 sw_frame_group_Null_data > This includes mpdus 136 of type Data Null as well as QoS Data Null 137 138 139 140 <enum 4 sw_frame_group_mgmt_0000 > 141 142 <enum 5 sw_frame_group_mgmt_0001 > 143 144 <enum 6 sw_frame_group_mgmt_0010 > 145 146 <enum 7 sw_frame_group_mgmt_0011 > 147 148 <enum 8 sw_frame_group_mgmt_0100 > 149 150 <enum 9 sw_frame_group_mgmt_0101 > 151 152 <enum 10 sw_frame_group_mgmt_0110 > 153 154 <enum 11 sw_frame_group_mgmt_0111 > 155 156 <enum 12 sw_frame_group_mgmt_1000 > 157 158 <enum 13 sw_frame_group_mgmt_1001 > 159 160 <enum 14 sw_frame_group_mgmt_1010 > 161 162 <enum 15 sw_frame_group_mgmt_1011 > 163 164 <enum 16 sw_frame_group_mgmt_1100 > 165 166 <enum 17 sw_frame_group_mgmt_1101 > 167 168 <enum 18 sw_frame_group_mgmt_1110 > 169 170 <enum 19 sw_frame_group_mgmt_1111 > 171 172 173 174 <enum 20 sw_frame_group_ctrl_0000 > 175 176 <enum 21 sw_frame_group_ctrl_0001 > 177 178 <enum 22 sw_frame_group_ctrl_0010 > 179 180 <enum 23 sw_frame_group_ctrl_0011 > 181 182 <enum 24 sw_frame_group_ctrl_0100 > 183 184 <enum 25 sw_frame_group_ctrl_0101 > 185 186 <enum 26 sw_frame_group_ctrl_0110 > 187 188 <enum 27 sw_frame_group_ctrl_0111 > 189 190 <enum 28 sw_frame_group_ctrl_1000 > 191 192 <enum 29 sw_frame_group_ctrl_1001 > 193 194 <enum 30 sw_frame_group_ctrl_1010 > 195 196 <enum 31 sw_frame_group_ctrl_1011 > 197 198 <enum 32 sw_frame_group_ctrl_1100 > 199 200 <enum 33 sw_frame_group_ctrl_1101 > 201 202 <enum 34 sw_frame_group_ctrl_1110 > 203 204 <enum 35 sw_frame_group_ctrl_1111 > 205 206 207 208 <enum 36 sw_frame_group_unsupported> This covers type 3 209 and protocol version != 0 210 211 Note: The corresponding Rxpcu_Mpdu_filter_in_category 212 can only be rxpcu_monitor_other 213 214 215 216 217 Note: The corresponding Rxpcu_Mpdu_filter_in_category 218 can be rxpcu_filter_pass 219 220 221 222 <legal 0-37> 223 */ 224 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000000 225 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 226 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc 227 228 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_NDP_FRAME 229 230 When set, the received frame was an NDP frame, and thus 231 there will be no MPDU data. 232 233 <legal all> 234 */ 235 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000000 236 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 237 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 238 239 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR 240 241 When set, a PHY error was received before MAC received 242 any data, and thus there will be no MPDU data. 243 244 <legal all> 245 */ 246 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000000 247 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 248 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 249 250 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER 251 252 When set, a PHY error was received before MAC received 253 the complete MPDU header which was needed for proper 254 decoding 255 256 <legal all> 257 */ 258 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 259 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 260 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 261 262 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR 263 264 Set when RXPCU detected a version error in the Frame 265 control field 266 267 <legal all> 268 */ 269 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 270 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 271 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 272 273 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID 274 275 When set, AST based lookup for this frame has found a 276 valid result. 277 278 279 280 Note that for NDP frame this will never be set 281 282 <legal all> 283 */ 284 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 285 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 286 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 287 288 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RESERVED_0A 289 290 <legal 0> 291 */ 292 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 293 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RESERVED_0A_LSB 14 294 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RESERVED_0A_MASK 0x0000c000 295 296 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID 297 298 A ppdu counter value that PHY increments for every PPDU 299 received. The counter value wraps around 300 301 <legal all> 302 */ 303 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 304 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 305 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 306 307 /* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_AST_INDEX 308 309 This field indicates the index of the AST entry 310 corresponding to this MPDU. It is provided by the GSE module 311 instantiated in RXPCU. 312 313 A value of 0xFFFF indicates an invalid AST index, 314 meaning that No AST entry was found or NO AST search was 315 performed 316 317 318 319 In case of ndp or phy_err, this field will be set to 320 0xFFFF 321 322 <legal all> 323 */ 324 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000004 325 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 326 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff 327 328 /* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_SW_PEER_ID 329 330 In case of ndp or phy_err or AST_based_lookup_valid == 331 0, this field will be set to 0 332 333 334 335 This field indicates a unique peer identifier. It is set 336 equal to field 'sw_peer_id' from the AST entry 337 338 339 340 <legal all> 341 */ 342 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000004 343 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 344 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 345 346 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID 347 348 When set, the field Mpdu_Frame_control_field has valid 349 information 350 351 352 353 354 <legal all> 355 */ 356 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 357 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 358 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 359 360 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID 361 362 When set, the field Mpdu_duration_field has valid 363 information 364 365 366 367 368 <legal all> 369 */ 370 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x00000008 371 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 372 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 373 374 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID 375 376 When set, the fields mac_addr_ad1_..... have valid 377 information 378 379 380 381 382 <legal all> 383 */ 384 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 385 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 386 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 387 388 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID 389 390 When set, the fields mac_addr_ad2_..... have valid 391 information 392 393 394 395 396 397 398 399 <legal all> 400 */ 401 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 402 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 403 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 404 405 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID 406 407 When set, the fields mac_addr_ad3_..... have valid 408 information 409 410 411 412 413 414 415 416 <legal all> 417 */ 418 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 419 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 420 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 421 422 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID 423 424 When set, the fields mac_addr_ad4_..... have valid 425 information 426 427 428 429 430 431 432 433 <legal all> 434 */ 435 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 436 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 437 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 438 439 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID 440 441 When set, the fields mpdu_sequence_control_field and 442 mpdu_sequence_number have valid information as well as field 443 444 445 446 For MPDUs without a sequence control field, this field 447 will not be set. 448 449 450 451 452 <legal all> 453 */ 454 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 455 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 456 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 457 458 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID 459 460 When set, the field mpdu_qos_control_field has valid 461 information 462 463 464 465 For MPDUs without a QoS control field, this field will 466 not be set. 467 468 469 470 471 <legal all> 472 */ 473 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 474 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 475 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 476 477 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID 478 479 When set, the field mpdu_HT_control_field has valid 480 information 481 482 483 484 For MPDUs without a HT control field, this field will 485 not be set. 486 487 488 489 490 <legal all> 491 */ 492 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 493 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 494 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 495 496 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID 497 498 When set, the encryption related info fields, like IV 499 and PN are valid 500 501 502 503 For MPDUs that are not encrypted, this will not be set. 504 505 506 507 508 <legal all> 509 */ 510 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 511 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 512 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 513 514 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER 515 516 Field only valid when Mpdu_sequence_control_valid is set 517 AND Fragment_flag is set 518 519 520 521 The fragment number from the 802.11 header. 522 523 <legal all> 524 */ 525 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000008 526 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 527 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 528 529 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG 530 531 The More Fragment bit setting from the MPDU header of 532 the received frame 533 534 535 536 <legal all> 537 */ 538 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 539 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 540 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 541 542 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A 543 544 <legal 0> 545 */ 546 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 547 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 15 548 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00008000 549 550 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FR_DS 551 552 Field only valid when Mpdu_frame_control_valid is set 553 554 555 556 Set if the from DS bit is set in the frame control. 557 558 <legal all> 559 */ 560 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x00000008 561 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 562 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 563 564 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_TO_DS 565 566 Field only valid when Mpdu_frame_control_valid is set 567 568 569 570 Set if the to DS bit is set in the frame control. 571 572 <legal all> 573 */ 574 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x00000008 575 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 576 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 577 578 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_ENCRYPTED 579 580 Field only valid when Mpdu_frame_control_valid is set. 581 582 583 584 Protected bit from the frame control. 585 586 <legal all> 587 */ 588 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x00000008 589 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 590 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 591 592 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_RETRY 593 594 Field only valid when Mpdu_frame_control_valid is set. 595 596 597 598 Retry bit from the frame control. Only valid when 599 first_msdu is set. 600 601 <legal all> 602 */ 603 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x00000008 604 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 605 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 606 607 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 608 609 Field only valid when Mpdu_sequence_control_valid is 610 set. 611 612 613 614 The sequence number from the 802.11 header. 615 616 <legal all> 617 */ 618 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 619 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 620 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 621 622 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_EPD_EN 623 624 Field only valid when AST_based_lookup_valid == 1. 625 626 627 628 629 630 In case of ndp or phy_err or AST_based_lookup_valid == 631 0, this field will be set to 0 632 633 634 635 If set to one use EPD instead of LPD 636 637 638 639 640 <legal all> 641 */ 642 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000c 643 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 644 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 645 646 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED 647 648 In case of ndp or phy_err or AST_based_lookup_valid == 649 0, this field will be set to 0 650 651 652 653 When set, all frames (data only ?) shall be encrypted. 654 If not, RX CRYPTO shall set an error flag. 655 656 <legal all> 657 */ 658 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 659 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 660 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 661 662 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE 663 664 In case of ndp or phy_err or AST_based_lookup_valid == 665 0, this field will be set to 0 666 667 668 669 Indicates type of decrypt cipher used (as defined in the 670 peer entry) 671 672 673 674 <enum 0 wep_40> WEP 40-bit 675 676 <enum 1 wep_104> WEP 104-bit 677 678 <enum 2 tkip_no_mic> TKIP without MIC 679 680 <enum 3 wep_128> WEP 128-bit 681 682 <enum 4 tkip_with_mic> TKIP with MIC 683 684 <enum 5 wapi> WAPI 685 686 <enum 6 aes_ccmp_128> AES CCMP 128 687 688 <enum 7 no_cipher> No crypto 689 690 <enum 8 aes_ccmp_256> AES CCMP 256 691 692 <enum 9 aes_gcmp_128> AES CCMP 128 693 694 <enum 10 aes_gcmp_256> AES CCMP 256 695 696 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 697 698 699 700 <enum 12 wep_varied_width> WEP encryption. As for WEP 701 per keyid the key bit width can vary, the key bit width for 702 this MPDU will be indicated in field 703 wep_key_width_for_variable key 704 705 <legal 0-12> 706 */ 707 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000c 708 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 709 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c 710 711 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 712 713 Field only valid when key_type is set to 714 wep_varied_width. 715 716 717 718 This field indicates the size of the wep key for this 719 MPDU. 720 721 722 723 <enum 0 wep_varied_width_40> WEP 40-bit 724 725 <enum 1 wep_varied_width_104> WEP 104-bit 726 727 <enum 2 wep_varied_width_128> WEP 128-bit 728 729 730 731 <legal 0-2> 732 */ 733 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000c 734 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 735 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 736 737 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_MESH_STA 738 739 In case of ndp or phy_err or AST_based_lookup_valid == 740 0, this field will be set to 0 741 742 743 744 When set, this is a Mesh (11s) STA 745 746 <legal all> 747 */ 748 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000c 749 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8 750 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000100 751 752 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_HIT 753 754 In case of ndp or phy_err or AST_based_lookup_valid == 755 0, this field will be set to 0 756 757 758 759 When set, the BSSID of the incoming frame matched one of 760 the 8 BSSID register values 761 762 763 764 <legal all> 765 */ 766 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000c 767 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 9 768 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000200 769 770 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_NUMBER 771 772 Field only valid when bssid_hit is set. 773 774 775 776 This number indicates which one out of the 8 BSSID 777 register values matched the incoming frame 778 779 <legal all> 780 */ 781 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000c 782 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 10 783 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00003c00 784 785 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_TID 786 787 Field only valid when mpdu_qos_control_valid is set 788 789 790 791 The TID field in the QoS control field 792 793 <legal all> 794 */ 795 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000c 796 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_TID_LSB 14 797 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_TID_MASK 0x0003c000 798 799 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_RESERVED_3A 800 801 <legal 0> 802 */ 803 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c 804 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_RESERVED_3A_LSB 18 805 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_RESERVED_3A_MASK 0xfffc0000 806 807 /* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_31_0 808 809 810 811 812 813 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 814 is valid. 815 816 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 817 WEPSeed[1], pn1}. Only pn[47:0] is valid. 818 819 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 820 pn1, pn0}. Only pn[47:0] is valid. 821 822 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 823 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 824 pn0}. pn[127:0] are valid. 825 826 827 828 */ 829 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 830 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 831 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff 832 833 /* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_63_32 834 835 836 837 838 Bits [63:32] of the PN number. See description for 839 pn_31_0. 840 841 842 843 */ 844 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000014 845 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 846 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff 847 848 /* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_95_64 849 850 851 852 853 Bits [95:64] of the PN number. See description for 854 pn_31_0. 855 856 857 858 */ 859 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000018 860 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 861 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff 862 863 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_PN_127_96 864 865 866 867 868 Bits [127:96] of the PN number. See description for 869 pn_31_0. 870 871 872 873 */ 874 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000001c 875 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 876 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff 877 878 /* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA 879 880 In case of ndp or phy_err or AST_based_lookup_valid == 881 0, this field will be set to 0 882 883 884 885 Meta data that SW has programmed in the Peer table entry 886 of the transmitting STA. 887 888 <legal all> 889 */ 890 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 891 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 892 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 893 894 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 895 896 897 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 898 899 The ID of the REO exit ring where the MSDU frame shall 900 push after (MPDU level) reordering has finished. 901 902 903 904 <enum 0 reo_destination_tcl> Reo will push the frame 905 into the REO2TCL ring 906 907 <enum 1 reo_destination_sw1> Reo will push the frame 908 into the REO2SW1 ring 909 910 <enum 2 reo_destination_sw2> Reo will push the frame 911 into the REO2SW1 ring 912 913 <enum 3 reo_destination_sw3> Reo will push the frame 914 into the REO2SW1 ring 915 916 <enum 4 reo_destination_sw4> Reo will push the frame 917 into the REO2SW1 ring 918 919 <enum 5 reo_destination_release> Reo will push the frame 920 into the REO_release ring 921 922 <enum 6 reo_destination_fw> Reo will push the frame into 923 the REO2FW ring 924 925 <enum 7 reo_destination_7> REO remaps this 926 927 <enum 8 reo_destination_8> REO remaps this <enum 9 928 reo_destination_9> REO remaps this <enum 10 929 reo_destination_10> REO remaps this 930 931 <enum 11 reo_destination_11> REO remaps this 932 933 <enum 12 reo_destination_12> REO remaps this <enum 13 934 reo_destination_13> REO remaps this 935 936 <enum 14 reo_destination_14> REO remaps this 937 938 <enum 15 reo_destination_15> REO remaps this 939 940 <enum 16 reo_destination_16> REO remaps this 941 942 <enum 17 reo_destination_17> REO remaps this 943 944 <enum 18 reo_destination_18> REO remaps this 945 946 <enum 19 reo_destination_19> REO remaps this 947 948 <enum 20 reo_destination_20> REO remaps this 949 950 <enum 21 reo_destination_21> REO remaps this 951 952 <enum 22 reo_destination_22> REO remaps this 953 954 <enum 23 reo_destination_23> REO remaps this 955 956 <enum 24 reo_destination_24> REO remaps this 957 958 <enum 25 reo_destination_25> REO remaps this 959 960 <enum 26 reo_destination_26> REO remaps this 961 962 <enum 27 reo_destination_27> REO remaps this 963 964 <enum 28 reo_destination_28> REO remaps this 965 966 <enum 29 reo_destination_29> REO remaps this 967 968 <enum 30 reo_destination_30> REO remaps this 969 970 <enum 31 reo_destination_31> REO remaps this 971 972 973 974 <legal all> 975 */ 976 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000024 977 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 978 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 979 980 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A 981 982 <legal 0> 983 */ 984 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000024 985 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_LSB 5 986 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_MASK 0x00000060 987 988 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 989 990 Field is used to enable classification based on the 991 chosen Toeplitz hash from Common Parser (without reference 992 to each hash type). 993 994 <legal all> 995 */ 996 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000024 997 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 998 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 999 1000 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 1001 1002 Filter pass ucast data frame routing selection. 1003 1004 1005 1006 1'b0: source and destination rings are selected from the 1007 RxOLE register settings for the packet type 1008 1009 1010 1011 1'b1: source ring and destination ring is selected from 1012 the rxdma0_source_ring_selection and 1013 rxdma0_destination_ring_selection fields in this STRUCT 1014 1015 <legal all> 1016 */ 1017 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000024 1018 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 1019 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 1020 1021 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 1022 1023 Filter pass multicase data frame routing selection. 1024 1025 1026 1027 1'b0: source and destination rings are selected from the 1028 RxOLE register settings for the packet type 1029 1030 1031 1032 1'b1: source ring and destination ring is selected from 1033 the rxdma0_source_ring_selection and 1034 rxdma0_destination_ring_selection fields in this STRUCT 1035 1036 <legal all> 1037 */ 1038 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000024 1039 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 1040 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 1041 1042 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 1043 1044 Filter pass control bar frame routing selection. 1045 1046 1047 1048 1'b0: source and destination rings are selected from the 1049 RxOLE register settings for the packet type 1050 1051 1052 1053 1'b1: source ring and destination ring is selected from 1054 the rxdma0_source_ring_selection and 1055 rxdma0_destination_ring_selection fields in this STRUCT 1056 1057 <legal all> 1058 */ 1059 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000024 1060 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 1061 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 1062 1063 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 1064 1065 Field only valid when for the received frame type the 1066 corresponding pkt_selection_fp_... bit is set 1067 1068 1069 1070 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 1071 this frame shall be sourced by wbm2rxdma buffer source ring 1072 1073 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 1074 this frame shall be sourced by fw2rxdma buffer source ring 1075 1076 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 1077 this frame shall be sourced by sw2rxdma buffer source ring 1078 1079 <enum 3 no_buffer_ring> The frame shall not be written 1080 to any data buffer 1081 1082 <legal all> 1083 */ 1084 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000024 1085 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 1086 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 1087 1088 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 1089 1090 Field only valid when for the received frame type the 1091 corresponding pkt_selection_fp_... bit is set 1092 1093 1094 1095 <enum 0 rxdma_release_ring > RXDMA0 shall push the 1096 frame to the Release ring. Effectively this means the frame 1097 needs to be dropped. 1098 1099 1100 1101 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 1102 the FW ring 1103 1104 1105 1106 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 1107 the SW ring 1108 1109 1110 1111 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 1112 to the REO entrance ring 1113 1114 <legal all> 1115 */ 1116 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000024 1117 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 1118 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 1119 1120 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 1121 1122 <legal 0> 1123 */ 1124 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000024 1125 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 1126 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 1127 1128 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0 1129 1130 In case of ndp or phy_err or AST_based_lookup_valid == 1131 0, this field will be set to 0 1132 1133 1134 1135 Address (lower 32 bits) of the REO queue descriptor. 1136 1137 1138 1139 If no Peer entry lookup happened for this frame, the 1140 value wil be set to 0, and the frame shall never be pushed 1141 to REO entrance ring. 1142 1143 <legal all> 1144 */ 1145 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 1146 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1147 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1148 1149 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32 1150 1151 In case of ndp or phy_err or AST_based_lookup_valid == 1152 0, this field will be set to 0 1153 1154 1155 1156 Address (upper 8 bits) of the REO queue descriptor. 1157 1158 1159 1160 If no Peer entry lookup happened for this frame, the 1161 value wil be set to 0, and the frame shall never be pushed 1162 to REO entrance ring. 1163 1164 <legal all> 1165 */ 1166 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 1167 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1168 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1169 1170 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER 1171 1172 In case of ndp or phy_err or AST_based_lookup_valid == 1173 0, this field will be set to 0 1174 1175 1176 1177 Indicates the MPDU queue ID to which this MPDU link 1178 descriptor belongs 1179 1180 Used for tracking and debugging 1181 1182 <legal all> 1183 */ 1184 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 1185 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 1186 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 1187 1188 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING 1189 1190 Indicates that a delimiter FCS error was found in 1191 between the Previous MPDU and this MPDU. 1192 1193 1194 1195 Note that this is just a warning, and does not mean that 1196 this MPDU is corrupted in any way. If it is, there will be 1197 other errors indicated such as FCS or decrypt errors 1198 1199 1200 1201 In case of ndp or phy_err, this field will indicate at 1202 least one of delimiters located after the last MPDU in the 1203 previous PPDU has been corrupted. 1204 */ 1205 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 1206 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 1207 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 1208 1209 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR 1210 1211 Indicates that the first delimiter had a FCS failure. 1212 Only valid when first_mpdu and first_msdu are set. 1213 1214 1215 1216 */ 1217 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000002c 1218 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 1219 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 1220 1221 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11 1222 1223 <legal 0> 1224 */ 1225 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11_OFFSET 0x0000002c 1226 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11_LSB 26 1227 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11_MASK 0xfc000000 1228 1229 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET 1230 1231 1232 1233 1234 The key ID octet from the IV. 1235 1236 1237 1238 In case of ndp or phy_err or AST_based_lookup_valid == 1239 0, this field will be set to 0 1240 1241 <legal all> 1242 */ 1243 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 1244 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1245 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff 1246 1247 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY 1248 1249 In case of ndp or phy_err or AST_based_lookup_valid == 1250 0, this field will be set to 0 1251 1252 1253 1254 Set if new RX_PEER_ENTRY TLV follows. If clear, 1255 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 1256 uses old peer entry or not decrypt. 1257 1258 <legal all> 1259 */ 1260 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 1261 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1262 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 1263 1264 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED 1265 1266 In case of ndp or phy_err or AST_based_lookup_valid == 1267 0, this field will be set to 0 1268 1269 1270 1271 Set if decryption is needed. 1272 1273 1274 1275 Note: 1276 1277 When RXPCU sets bit 'ast_index_not_found' and/or 1278 ast_index_timeout', RXPCU will also ensure that this bit is 1279 NOT set 1280 1281 CRYPTO for that reason only needs to evaluate this bit 1282 and non of the other ones. 1283 1284 <legal all> 1285 */ 1286 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 1287 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1288 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 1289 1290 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE 1291 1292 In case of ndp or phy_err or AST_based_lookup_valid == 1293 0, this field will be set to 0 1294 1295 1296 1297 Used by the OLE during decapsulation. 1298 1299 1300 1301 Indicates the decapsulation that HW will perform: 1302 1303 1304 1305 <enum 0 RAW> No encapsulation 1306 1307 <enum 1 Native_WiFi> 1308 1309 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 1310 SNAP/LLC) 1311 1312 <enum 3 802_3> Indicate Ethernet 1313 1314 1315 1316 <legal all> 1317 */ 1318 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 1319 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1320 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 1321 1322 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING 1323 1324 In case of ndp or phy_err or AST_based_lookup_valid == 1325 0, this field will be set to 0 1326 1327 1328 1329 Insert 4 byte of all zeros as VLAN tag if the rx payload 1330 does not have VLAN. Used during decapsulation. 1331 1332 <legal all> 1333 */ 1334 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1335 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1336 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1337 1338 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING 1339 1340 In case of ndp or phy_err or AST_based_lookup_valid == 1341 0, this field will be set to 0 1342 1343 1344 1345 Insert 4 byte of all zeros as double VLAN tag if the rx 1346 payload does not have VLAN. Used during 1347 1348 <legal all> 1349 */ 1350 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1351 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1352 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1353 1354 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP 1355 1356 In case of ndp or phy_err or AST_based_lookup_valid == 1357 0, this field will be set to 0 1358 1359 1360 1361 Strip the VLAN during decapsulation. Used by the OLE. 1362 1363 <legal all> 1364 */ 1365 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1366 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1367 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1368 1369 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP 1370 1371 In case of ndp or phy_err or AST_based_lookup_valid == 1372 0, this field will be set to 0 1373 1374 1375 1376 Strip the double VLAN during decapsulation. Used by 1377 the OLE. 1378 1379 <legal all> 1380 */ 1381 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1382 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1383 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1384 1385 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT 1386 1387 The number of delimiters before this MPDU. 1388 1389 1390 1391 Note that this number is cleared at PPDU start. 1392 1393 1394 1395 If this MPDU is the first received MPDU in the PPDU and 1396 this MPDU gets filtered-in, this field will indicate the 1397 number of delimiters located after the last MPDU in the 1398 previous PPDU. 1399 1400 1401 1402 If this MPDU is located after the first received MPDU in 1403 an PPDU, this field will indicate the number of delimiters 1404 located between the previous MPDU and this MPDU. 1405 1406 1407 1408 In case of ndp or phy_err, this field will indicate the 1409 number of delimiters located after the last MPDU in the 1410 previous PPDU. 1411 1412 <legal all> 1413 */ 1414 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 1415 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1416 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 1417 1418 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG 1419 1420 When set, received frame was part of an A-MPDU. 1421 1422 1423 1424 1425 <legal all> 1426 */ 1427 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 1428 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1429 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 1430 1431 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME 1432 1433 In case of ndp or phy_err or AST_based_lookup_valid == 1434 0, this field will be set to 0 1435 1436 1437 1438 When set, received frame is a BAR frame 1439 1440 <legal all> 1441 */ 1442 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 1443 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1444 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 1445 1446 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12 1447 1448 <legal 0>. 1449 */ 1450 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 1451 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 30 1452 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0xc0000000 1453 1454 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH 1455 1456 In case of ndp or phy_err this field will be set to 0 1457 1458 1459 1460 MPDU length before decapsulation. 1461 1462 <legal all> 1463 */ 1464 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 1465 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 1466 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff 1467 1468 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU 1469 1470 See definition in RX attention descriptor 1471 1472 1473 1474 In case of ndp or phy_err, this field will be set. Note 1475 however that there will not actually be any data contents in 1476 the MPDU. 1477 1478 <legal all> 1479 */ 1480 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 1481 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 1482 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 1483 1484 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST 1485 1486 In case of ndp or phy_err or Phy_err_during_mpdu_header 1487 this field will be set to 0 1488 1489 1490 1491 See definition in RX attention descriptor 1492 1493 <legal all> 1494 */ 1495 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 1496 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 1497 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 1498 1499 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND 1500 1501 In case of ndp or phy_err or Phy_err_during_mpdu_header 1502 this field will be set to 0 1503 1504 1505 1506 See definition in RX attention descriptor 1507 1508 <legal all> 1509 */ 1510 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1511 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 1512 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 1513 1514 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT 1515 1516 In case of ndp or phy_err or Phy_err_during_mpdu_header 1517 this field will be set to 0 1518 1519 1520 1521 See definition in RX attention descriptor 1522 1523 <legal all> 1524 */ 1525 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1526 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 1527 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 1528 1529 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT 1530 1531 In case of ndp or phy_err or Phy_err_during_mpdu_header 1532 this field will be set to 0 1533 1534 1535 1536 See definition in RX attention descriptor 1537 1538 <legal all> 1539 */ 1540 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 1541 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 1542 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 1543 1544 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS 1545 1546 In case of ndp or phy_err or Phy_err_during_mpdu_header 1547 this field will be set to 1 1548 1549 1550 1551 See definition in RX attention descriptor 1552 1553 <legal all> 1554 */ 1555 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 1556 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 1557 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 1558 1559 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA 1560 1561 In case of ndp or phy_err or Phy_err_during_mpdu_header 1562 this field will be set to 0 1563 1564 1565 1566 See definition in RX attention descriptor 1567 1568 <legal all> 1569 */ 1570 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 1571 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 1572 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 1573 1574 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE 1575 1576 In case of ndp or phy_err or Phy_err_during_mpdu_header 1577 this field will be set to 0 1578 1579 1580 1581 See definition in RX attention descriptor 1582 1583 <legal all> 1584 */ 1585 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 1586 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 1587 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 1588 1589 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE 1590 1591 In case of ndp or phy_err or Phy_err_during_mpdu_header 1592 this field will be set to 0 1593 1594 1595 1596 See definition in RX attention descriptor 1597 1598 <legal all> 1599 */ 1600 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 1601 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 1602 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 1603 1604 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA 1605 1606 In case of ndp or phy_err or Phy_err_during_mpdu_header 1607 this field will be set to 0 1608 1609 1610 1611 See definition in RX attention descriptor 1612 1613 <legal all> 1614 */ 1615 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 1616 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 1617 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 1618 1619 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP 1620 1621 In case of ndp or phy_err or Phy_err_during_mpdu_header 1622 this field will be set to 0 1623 1624 1625 1626 See definition in RX attention descriptor 1627 1628 <legal all> 1629 */ 1630 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 1631 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 1632 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 1633 1634 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG 1635 1636 In case of ndp or phy_err or Phy_err_during_mpdu_header 1637 this field will be set to 0 1638 1639 1640 1641 See definition in RX attention descriptor 1642 1643 <legal all> 1644 */ 1645 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 1646 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 1647 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 1648 1649 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER 1650 1651 In case of ndp or phy_err or Phy_err_during_mpdu_header 1652 this field will be set to 0 1653 1654 1655 1656 See definition in RX attention descriptor 1657 1658 1659 1660 <legal all> 1661 */ 1662 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 1663 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 1664 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 1665 1666 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER 1667 1668 In case of ndp or phy_err or Phy_err_during_mpdu_header 1669 this field will be set to 0 1670 1671 1672 1673 See definition in RX attention descriptor 1674 1675 <legal all> 1676 */ 1677 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 1678 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 1679 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 1680 1681 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED 1682 1683 In case of ndp or phy_err or Phy_err_during_mpdu_header 1684 this field will be set to 0 1685 1686 1687 1688 See definition in RX attention descriptor 1689 1690 <legal all> 1691 */ 1692 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 1693 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 1694 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 1695 1696 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED 1697 1698 In case of ndp or phy_err or Phy_err_during_mpdu_header 1699 this field will be set to 0 1700 1701 1702 1703 See definition in RX attention descriptor 1704 1705 <legal all> 1706 */ 1707 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 1708 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 1709 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 1710 1711 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13 1712 1713 <legal 0> 1714 */ 1715 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 1716 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 30 1717 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0xc0000000 1718 1719 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD 1720 1721 Field only valid when Mpdu_frame_control_valid is set 1722 1723 1724 1725 The frame control field of this received MPDU. 1726 1727 1728 1729 Field only valid when Ndp_frame and phy_err are NOT set 1730 1731 1732 1733 Bytes 0 + 1 of the received MPDU 1734 1735 <legal all> 1736 */ 1737 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1738 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1739 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1740 1741 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD 1742 1743 Field only valid when Mpdu_duration_valid is set 1744 1745 1746 1747 The duration field of this received MPDU. 1748 1749 <legal all> 1750 */ 1751 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 1752 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1753 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 1754 1755 /* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0 1756 1757 Field only valid when mac_addr_ad1_valid is set 1758 1759 1760 1761 The Least Significant 4 bytes of the Received Frames MAC 1762 Address AD1 1763 1764 <legal all> 1765 */ 1766 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1767 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 1768 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1769 1770 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32 1771 1772 Field only valid when mac_addr_ad1_valid is set 1773 1774 1775 1776 The 2 most significant bytes of the Received Frames MAC 1777 Address AD1 1778 1779 <legal all> 1780 */ 1781 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1782 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1783 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1784 1785 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0 1786 1787 Field only valid when mac_addr_ad2_valid is set 1788 1789 1790 1791 The Least Significant 2 bytes of the Received Frames MAC 1792 Address AD2 1793 1794 <legal all> 1795 */ 1796 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1797 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1798 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1799 1800 /* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16 1801 1802 Field only valid when mac_addr_ad2_valid is set 1803 1804 1805 1806 The 4 most significant bytes of the Received Frames MAC 1807 Address AD2 1808 1809 <legal all> 1810 */ 1811 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1812 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 1813 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1814 1815 /* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0 1816 1817 Field only valid when mac_addr_ad3_valid is set 1818 1819 1820 1821 The Least Significant 4 bytes of the Received Frames MAC 1822 Address AD3 1823 1824 <legal all> 1825 */ 1826 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1827 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1828 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1829 1830 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32 1831 1832 Field only valid when mac_addr_ad3_valid is set 1833 1834 1835 1836 The 2 most significant bytes of the Received Frames MAC 1837 Address AD3 1838 1839 <legal all> 1840 */ 1841 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1842 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 1843 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1844 1845 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD 1846 1847 1848 1849 1850 The sequence control field of the MPDU 1851 1852 <legal all> 1853 */ 1854 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1855 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1856 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1857 1858 /* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0 1859 1860 Field only valid when mac_addr_ad4_valid is set 1861 1862 1863 1864 The Least Significant 4 bytes of the Received Frames MAC 1865 Address AD4 1866 1867 <legal all> 1868 */ 1869 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1870 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1871 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1872 1873 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32 1874 1875 Field only valid when mac_addr_ad4_valid is set 1876 1877 1878 1879 The 2 most significant bytes of the Received Frames MAC 1880 Address AD4 1881 1882 <legal all> 1883 */ 1884 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1885 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 1886 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1887 1888 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD 1889 1890 Field only valid when mpdu_qos_control_valid is set 1891 1892 1893 1894 The sequence control field of the MPDU 1895 1896 <legal all> 1897 */ 1898 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1899 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 1900 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1901 1902 /* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD 1903 1904 Field only valid when mpdu_qos_control_valid is set 1905 1906 1907 1908 The HT control field of the MPDU 1909 1910 <legal all> 1911 */ 1912 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1913 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 1914 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1915 1916 /* Description RX_MPDU_START_23_RAW_MPDU 1917 1918 Set by OLE when it has not performed any .11 to .3 1919 header conversion on this MPDU. 1920 1921 <legal all> 1922 */ 1923 #define RX_MPDU_START_23_RAW_MPDU_OFFSET 0x0000005c 1924 #define RX_MPDU_START_23_RAW_MPDU_LSB 0 1925 #define RX_MPDU_START_23_RAW_MPDU_MASK 0x00000001 1926 1927 /* Description RX_MPDU_START_23_RESERVED_23 1928 1929 <legal 0> 1930 */ 1931 #define RX_MPDU_START_23_RESERVED_23_OFFSET 0x0000005c 1932 #define RX_MPDU_START_23_RESERVED_23_LSB 1 1933 #define RX_MPDU_START_23_RESERVED_23_MASK 0xfffffffe 1934 1935 1936 #endif // _RX_MPDU_START_H_ 1937