1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _REO_ENTRANCE_RING_H_
24 #define _REO_ENTRANCE_RING_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 #include "rx_mpdu_details.h"
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
34 //	4	rx_reo_queue_desc_addr_31_0[31:0]
35 //	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
36 //	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], reserved_6a[31:11]
37 //	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
38 //
39 // ################ END SUMMARY #################
40 
41 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
42 
43 struct reo_entrance_ring {
44     struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
45              uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
46              uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
47                       rounded_mpdu_byte_count         : 14, //[21:8]
48                       reo_destination_indication      :  5, //[26:22]
49                       frameless_bar                   :  1, //[27]
50                       reserved_5a                     :  4; //[31:28]
51              uint32_t rxdma_push_reason               :  2, //[1:0]
52                       rxdma_error_code                :  5, //[6:2]
53                       mpdu_fragment_number            :  4, //[10:7]
54                       reserved_6a                     : 21; //[31:11]
55              uint32_t reserved_7a                     : 20, //[19:0]
56                       ring_id                         :  8, //[27:20]
57                       looping_count                   :  4; //[31:28]
58 };
59 
60 /*
61 
62 struct rx_mpdu_details reo_level_mpdu_frame_info
63 
64 			Consumer: REO
65 
66 			Producer: RXDMA
67 
68 
69 
70 			Details related to the MPDU being pushed into the REO
71 
72 rx_reo_queue_desc_addr_31_0
73 
74 			Consumer: REO
75 
76 			Producer: RXDMA
77 
78 
79 
80 			Address (lower 32 bits) of the REO queue descriptor.
81 
82 			<legal all>
83 
84 rx_reo_queue_desc_addr_39_32
85 
86 			Consumer: REO
87 
88 			Producer: RXDMA
89 
90 
91 
92 			Address (upper 8 bits) of the REO queue descriptor.
93 
94 			<legal all>
95 
96 rounded_mpdu_byte_count
97 
98 			An approximation of the number of bytes received in this
99 			MPDU.
100 
101 			Used to keeps stats on the amount of data flowing
102 			through a queue.
103 
104 			<legal all>
105 
106 reo_destination_indication
107 
108 			RXDMA copy the MPDU's first MSDU's destination
109 			indication field here. This is used for REO to be able to
110 			re-route the packet to a different SW destination ring if
111 			the packet is detected as error in REO.
112 
113 
114 
115 			The ID of the REO exit ring where the MSDU frame shall
116 			push after (MPDU level) reordering has finished.
117 
118 
119 
120 			<enum 0 reo_destination_tcl> Reo will push the frame
121 			into the REO2TCL ring
122 
123 			<enum 1 reo_destination_sw1> Reo will push the frame
124 			into the REO2SW1 ring
125 
126 			<enum 2 reo_destination_sw2> Reo will push the frame
127 			into the REO2SW1 ring
128 
129 			<enum 3 reo_destination_sw3> Reo will push the frame
130 			into the REO2SW1 ring
131 
132 			<enum 4 reo_destination_sw4> Reo will push the frame
133 			into the REO2SW1 ring
134 
135 			<enum 5 reo_destination_release> Reo will push the frame
136 			into the REO_release ring
137 
138 			<enum 6 reo_destination_fw> Reo will push the frame into
139 			the REO2FW ring
140 
141 			<enum 7 reo_destination_7> REO remaps this
142 
143 			<enum 8 reo_destination_8> REO remaps this <enum 9
144 			reo_destination_9> REO remaps this <enum 10
145 			reo_destination_10> REO remaps this
146 
147 			<enum 11 reo_destination_11> REO remaps this
148 
149 			<enum 12 reo_destination_12> REO remaps this <enum 13
150 			reo_destination_13> REO remaps this
151 
152 			<enum 14 reo_destination_14> REO remaps this
153 
154 			<enum 15 reo_destination_15> REO remaps this
155 
156 			<enum 16 reo_destination_16> REO remaps this
157 
158 			<enum 17 reo_destination_17> REO remaps this
159 
160 			<enum 18 reo_destination_18> REO remaps this
161 
162 			<enum 19 reo_destination_19> REO remaps this
163 
164 			<enum 20 reo_destination_20> REO remaps this
165 
166 			<enum 21 reo_destination_21> REO remaps this
167 
168 			<enum 22 reo_destination_22> REO remaps this
169 
170 			<enum 23 reo_destination_23> REO remaps this
171 
172 			<enum 24 reo_destination_24> REO remaps this
173 
174 			<enum 25 reo_destination_25> REO remaps this
175 
176 			<enum 26 reo_destination_26> REO remaps this
177 
178 			<enum 27 reo_destination_27> REO remaps this
179 
180 			<enum 28 reo_destination_28> REO remaps this
181 
182 			<enum 29 reo_destination_29> REO remaps this
183 
184 			<enum 30 reo_destination_30> REO remaps this
185 
186 			<enum 31 reo_destination_31> REO remaps this
187 
188 
189 
190 			<legal all>
191 
192 frameless_bar
193 
194 			When set, this REO entrance ring struct contains BAR
195 			info from a multi TID BAR frame. The original multi TID BAR
196 			frame itself contained all the REO info for the first TID,
197 			but all the subsequent TID info and their linkage to the REO
198 			descriptors is passed down as 'frameless' BAR info.
199 
200 
201 
202 			The only fields valid in this descriptor when this bit
203 			is set are:
204 
205 			Rx_reo_queue_desc_addr_31_0
206 
207 			RX_reo_queue_desc_addr_39_32
208 
209 
210 
211 			And within the
212 
213 			Reo_level_mpdu_frame_info:
214 
215 			   Within Rx_mpdu_desc_info_details:
216 
217 			Mpdu_Sequence_number
218 
219 			BAR_frame
220 
221 			Peer_meta_data
222 
223 			All other fields shall be set to 0
224 
225 
226 
227 			<legal all>
228 
229 reserved_5a
230 
231 			<legal 0>
232 
233 rxdma_push_reason
234 
235 			Indicates why rxdma pushed the frame to this ring
236 
237 
238 
239 			This field is ignored by REO.
240 
241 
242 
243 			<enum 0 rxdma_error_detected> RXDMA detected an error an
244 			pushed this frame to this queue
245 
246 			<enum 1 rxdma_routing_instruction> RXDMA pushed the
247 			frame to this queue per received routing instructions. No
248 			error within RXDMA was detected
249 
250 			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
251 			result the MSDU link descriptor might not have the
252 			last_msdu_in_mpdu_flag set, but instead WBM might just see a
253 			NULL pointer in the MSDU link descriptor. This is to be
254 			considered a normal condition for this scenario.
255 
256 
257 
258 			<legal 0 - 2>
259 
260 rxdma_error_code
261 
262 			Field only valid when 'rxdma_push_reason' set to
263 			'rxdma_error_detected'.
264 
265 
266 
267 			This field is ignored by REO.
268 
269 
270 
271 			<enum 0 rxdma_overflow_err>MPDU frame is not complete
272 			due to a FIFO overflow error in RXPCU.
273 
274 			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
275 			due to receiving incomplete MPDU from the PHY
276 
277 
278 			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
279 			error or CRYPTO received an encrypted frame, but did not get
280 			a valid corresponding key id in the peer entry.
281 
282 			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
283 			error
284 
285 			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
286 			unencrypted frame error when encrypted was expected
287 
288 			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
289 			length error
290 
291 			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
292 			number of MSDUs allowed in an MPDU got exceeded
293 
294 			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
295 			error
296 
297 			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
298 			parsing error
299 
300 			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
301 			during SA search
302 
303 			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
304 			during DA search
305 
306 			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
307 			timeout during flow search
308 
309 			<enum 13 Rxdma_flush_request>RXDMA received a flush
310 			request
311 
312 mpdu_fragment_number
313 
314 			Field only valid when Reo_level_mpdu_frame_info.
315 
316 			Rx_mpdu_desc_info_details.
317 
318 			Fragment_flag  is set.
319 
320 
321 
322 			The fragment number from the 802.11 header.
323 
324 
325 
326 			Note that the sequence number is embedded in field:
327 			Reo_level_mpdu_frame_info.
328 
329 			Rx_mpdu_desc_info_details.
330 
331 			Mpdu_Sequence_number
332 
333 
334 
335 			<legal all>
336 
337 reserved_6a
338 
339 			<legal 0>
340 
341 reserved_7a
342 
343 			<legal 0>
344 
345 ring_id
346 
347 			Consumer: SW/REO/DEBUG
348 
349 			Producer: SRNG (of RXDMA)
350 
351 
352 
353 			For debugging.
354 
355 			This field is filled in by the SRNG module.
356 
357 			It help to identify the ring that is being looked <legal
358 			all>
359 
360 looping_count
361 
362 			Consumer: SW/REO/DEBUG
363 
364 			Producer: SRNG (of RXDMA)
365 
366 
367 
368 			For debugging.
369 
370 			This field is filled in by the SRNG module.
371 
372 
373 
374 			A count value that indicates the number of times the
375 			producer of entries into this Ring has looped around the
376 			ring.
377 
378 			At initialization time, this value is set to 0. On the
379 			first loop, this value is set to 1. After the max value is
380 			reached allowed by the number of bits for this field, the
381 			count value continues with 0 again.
382 
383 
384 
385 			In case SW is the consumer of the ring entries, it can
386 			use this field to figure out up to where the producer of
387 			entries has created new entries. This eliminates the need to
388 			check where the head pointer' of the ring is located once
389 			the SW starts processing an interrupt indicating that new
390 			entries have been put into this ring...
391 
392 
393 
394 			Also note that SW if it wants only needs to look at the
395 			LSB bit of this count value.
396 
397 			<legal all>
398 */
399 
400 
401  /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */
402 
403 
404  /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
405 
406 
407 /* Description		REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
408 
409 			Address (lower 32 bits) of the MSDU buffer OR
410 			MSDU_EXTENSION descriptor OR Link Descriptor
411 
412 
413 
414 			In case of 'NULL' pointer, this field is set to 0
415 
416 			<legal all>
417 */
418 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
419 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
420 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
421 
422 /* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
423 
424 			Address (upper 8 bits) of the MSDU buffer OR
425 			MSDU_EXTENSION descriptor OR Link Descriptor
426 
427 
428 
429 			In case of 'NULL' pointer, this field is set to 0
430 
431 			<legal all>
432 */
433 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
434 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
435 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
436 
437 /* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
438 
439 			Consumer: WBM
440 
441 			Producer: SW/FW
442 
443 
444 
445 			In case of 'NULL' pointer, this field is set to 0
446 
447 
448 
449 			Indicates to which buffer manager the buffer OR
450 			MSDU_EXTENSION descriptor OR link descriptor that is being
451 			pointed to shall be returned after the frame has been
452 			processed. It is used by WBM for routing purposes.
453 
454 
455 
456 			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
457 			to the WMB buffer idle list
458 
459 			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
460 			returned to the WMB idle link descriptor idle list
461 
462 			<enum 2 FW_BM> This buffer shall be returned to the FW
463 
464 			<enum 3 SW0_BM> This buffer shall be returned to the SW,
465 			ring 0
466 
467 			<enum 4 SW1_BM> This buffer shall be returned to the SW,
468 			ring 1
469 
470 			<enum 5 SW2_BM> This buffer shall be returned to the SW,
471 			ring 2
472 
473 			<enum 6 SW3_BM> This buffer shall be returned to the SW,
474 			ring 3
475 
476 			<enum 7 SW4_BM> This buffer shall be returned to the SW,
477 			ring 3
478 
479 
480 
481 			<legal all>
482 */
483 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
484 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
485 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
486 
487 /* Description		REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
488 
489 			Cookie field exclusively used by SW.
490 
491 
492 
493 			In case of 'NULL' pointer, this field is set to 0
494 
495 
496 
497 			HW ignores the contents, accept that it passes the
498 			programmed value on to other descriptors together with the
499 			physical address
500 
501 
502 
503 			Field can be used by SW to for example associate the
504 			buffers physical address with the virtual address
505 
506 			The bit definitions as used by SW are within SW HLD
507 			specification
508 
509 
510 
511 			NOTE:
512 
513 			The three most significant bits can have a special
514 			meaning in case this struct is embedded in a TX_MPDU_DETAILS
515 			STRUCT, and field transmit_bw_restriction is set
516 
517 
518 
519 			In case of NON punctured transmission:
520 
521 			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
522 
523 			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
524 
525 			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
526 
527 			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
528 
529 
530 
531 			In case of punctured transmission:
532 
533 			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
534 
535 			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
536 
537 			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
538 
539 			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
540 
541 			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
542 
543 			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
544 
545 			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
546 
547 			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
548 
549 
550 
551 			Note: a punctured transmission is indicated by the
552 			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
553 			TLV
554 
555 
556 
557 			<legal all>
558 */
559 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
560 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
561 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
562 
563  /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
564 
565 
566 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
567 
568 			Consumer: REO/SW/FW
569 
570 			Producer: RXDMA
571 
572 
573 
574 			The number of MSDUs within the MPDU
575 
576 			<legal all>
577 */
578 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
579 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
580 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
581 
582 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
583 
584 			Consumer: REO/SW/FW
585 
586 			Producer: RXDMA
587 
588 
589 
590 			The field can have two different meanings based on the
591 			setting of field 'BAR_frame':
592 
593 
594 
595 			'BAR_frame' is NOT set:
596 
597 			The MPDU sequence number of the received frame.
598 
599 
600 
601 			'BAR_frame' is set.
602 
603 			The MPDU Start sequence number from the BAR frame
604 
605 			<legal all>
606 */
607 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
608 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
609 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
610 
611 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
612 
613 			Consumer: REO/SW/FW
614 
615 			Producer: RXDMA
616 
617 
618 
619 			When set, this MPDU is a fragment and REO should forward
620 			this fragment MPDU to the REO destination ring without any
621 			reorder checks, pn checks or bitmap update. This implies
622 			that REO is forwarding the pointer to the MSDU link
623 			descriptor. The destination ring is coming from a
624 			programmable register setting in REO
625 
626 
627 
628 			<legal all>
629 */
630 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
631 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
632 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
633 
634 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
635 
636 			Consumer: REO/SW/FW
637 
638 			Producer: RXDMA
639 
640 
641 
642 			The retry bit setting from the MPDU header of the
643 			received frame
644 
645 			<legal all>
646 */
647 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
648 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
649 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
650 
651 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
652 
653 			Consumer: REO/SW/FW
654 
655 			Producer: RXDMA
656 
657 
658 
659 			When set, the MPDU was received as part of an A-MPDU.
660 
661 			<legal all>
662 */
663 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
664 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
665 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
666 
667 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
668 
669 			Consumer: REO/SW/FW
670 
671 			Producer: RXDMA
672 
673 
674 
675 			When set, the received frame is a BAR frame. After
676 			processing, this frame shall be pushed to SW or deleted.
677 
678 			<legal all>
679 */
680 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
681 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
682 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
683 
684 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
685 
686 			Consumer: REO/SW/FW
687 
688 			Producer: RXDMA
689 
690 
691 
692 			Copied here by RXDMA from RX_MPDU_END
693 
694 			When not set, REO will Not perform a PN sequence number
695 			check
696 */
697 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
698 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
699 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
700 
701 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
702 
703 			When set, OLE found a valid SA entry for all MSDUs in
704 			this MPDU
705 
706 			<legal all>
707 */
708 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
709 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
710 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
711 
712 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
713 
714 			When set, at least 1 MSDU within the MPDU has an
715 			unsuccessful MAC source address search due to the expiration
716 			of the search timer.
717 
718 			<legal all>
719 */
720 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
721 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
722 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
723 
724 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
725 
726 			When set, OLE found a valid DA entry for all MSDUs in
727 			this MPDU
728 
729 			<legal all>
730 */
731 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
732 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
733 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
734 
735 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
736 
737 			Field Only valid if da_is_valid is set
738 
739 
740 
741 			When set, at least one of the DA addresses is a
742 			Multicast or Broadcast address.
743 
744 			<legal all>
745 */
746 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
747 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
748 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
749 
750 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
751 
752 			When set, at least 1 MSDU within the MPDU has an
753 			unsuccessful MAC destination address search due to the
754 			expiration of the search timer.
755 
756 			<legal all>
757 */
758 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
759 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
760 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
761 
762 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
763 
764 			Field only valid when first_msdu_in_mpdu_flag is set.
765 
766 
767 
768 			When set, the contents in the MSDU buffer contains a
769 			'RAW' MPDU. This 'RAW' MPDU might be spread out over
770 			multiple MSDU buffers.
771 
772 			<legal all>
773 */
774 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
775 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
776 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
777 
778 /* Description		REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
779 
780 			The More Fragment bit setting from the MPDU header of
781 			the received frame
782 
783 
784 
785 			<legal all>
786 */
787 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
788 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
789 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
790 
791 /* Description		REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
792 
793 			Meta data that SW has programmed in the Peer table entry
794 			of the transmitting STA.
795 
796 			<legal all>
797 */
798 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
799 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
800 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
801 
802 /* Description		REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
803 
804 			Consumer: REO
805 
806 			Producer: RXDMA
807 
808 
809 
810 			Address (lower 32 bits) of the REO queue descriptor.
811 
812 			<legal all>
813 */
814 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
815 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
816 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
817 
818 /* Description		REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
819 
820 			Consumer: REO
821 
822 			Producer: RXDMA
823 
824 
825 
826 			Address (upper 8 bits) of the REO queue descriptor.
827 
828 			<legal all>
829 */
830 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
831 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
832 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
833 
834 /* Description		REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
835 
836 			An approximation of the number of bytes received in this
837 			MPDU.
838 
839 			Used to keeps stats on the amount of data flowing
840 			through a queue.
841 
842 			<legal all>
843 */
844 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
845 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
846 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
847 
848 /* Description		REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
849 
850 			RXDMA copy the MPDU's first MSDU's destination
851 			indication field here. This is used for REO to be able to
852 			re-route the packet to a different SW destination ring if
853 			the packet is detected as error in REO.
854 
855 
856 
857 			The ID of the REO exit ring where the MSDU frame shall
858 			push after (MPDU level) reordering has finished.
859 
860 
861 
862 			<enum 0 reo_destination_tcl> Reo will push the frame
863 			into the REO2TCL ring
864 
865 			<enum 1 reo_destination_sw1> Reo will push the frame
866 			into the REO2SW1 ring
867 
868 			<enum 2 reo_destination_sw2> Reo will push the frame
869 			into the REO2SW1 ring
870 
871 			<enum 3 reo_destination_sw3> Reo will push the frame
872 			into the REO2SW1 ring
873 
874 			<enum 4 reo_destination_sw4> Reo will push the frame
875 			into the REO2SW1 ring
876 
877 			<enum 5 reo_destination_release> Reo will push the frame
878 			into the REO_release ring
879 
880 			<enum 6 reo_destination_fw> Reo will push the frame into
881 			the REO2FW ring
882 
883 			<enum 7 reo_destination_7> REO remaps this
884 
885 			<enum 8 reo_destination_8> REO remaps this <enum 9
886 			reo_destination_9> REO remaps this <enum 10
887 			reo_destination_10> REO remaps this
888 
889 			<enum 11 reo_destination_11> REO remaps this
890 
891 			<enum 12 reo_destination_12> REO remaps this <enum 13
892 			reo_destination_13> REO remaps this
893 
894 			<enum 14 reo_destination_14> REO remaps this
895 
896 			<enum 15 reo_destination_15> REO remaps this
897 
898 			<enum 16 reo_destination_16> REO remaps this
899 
900 			<enum 17 reo_destination_17> REO remaps this
901 
902 			<enum 18 reo_destination_18> REO remaps this
903 
904 			<enum 19 reo_destination_19> REO remaps this
905 
906 			<enum 20 reo_destination_20> REO remaps this
907 
908 			<enum 21 reo_destination_21> REO remaps this
909 
910 			<enum 22 reo_destination_22> REO remaps this
911 
912 			<enum 23 reo_destination_23> REO remaps this
913 
914 			<enum 24 reo_destination_24> REO remaps this
915 
916 			<enum 25 reo_destination_25> REO remaps this
917 
918 			<enum 26 reo_destination_26> REO remaps this
919 
920 			<enum 27 reo_destination_27> REO remaps this
921 
922 			<enum 28 reo_destination_28> REO remaps this
923 
924 			<enum 29 reo_destination_29> REO remaps this
925 
926 			<enum 30 reo_destination_30> REO remaps this
927 
928 			<enum 31 reo_destination_31> REO remaps this
929 
930 
931 
932 			<legal all>
933 */
934 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
935 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
936 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
937 
938 /* Description		REO_ENTRANCE_RING_5_FRAMELESS_BAR
939 
940 			When set, this REO entrance ring struct contains BAR
941 			info from a multi TID BAR frame. The original multi TID BAR
942 			frame itself contained all the REO info for the first TID,
943 			but all the subsequent TID info and their linkage to the REO
944 			descriptors is passed down as 'frameless' BAR info.
945 
946 
947 
948 			The only fields valid in this descriptor when this bit
949 			is set are:
950 
951 			Rx_reo_queue_desc_addr_31_0
952 
953 			RX_reo_queue_desc_addr_39_32
954 
955 
956 
957 			And within the
958 
959 			Reo_level_mpdu_frame_info:
960 
961 			   Within Rx_mpdu_desc_info_details:
962 
963 			Mpdu_Sequence_number
964 
965 			BAR_frame
966 
967 			Peer_meta_data
968 
969 			All other fields shall be set to 0
970 
971 
972 
973 			<legal all>
974 */
975 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
976 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
977 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
978 
979 /* Description		REO_ENTRANCE_RING_5_RESERVED_5A
980 
981 			<legal 0>
982 */
983 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
984 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
985 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
986 
987 /* Description		REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
988 
989 			Indicates why rxdma pushed the frame to this ring
990 
991 
992 
993 			This field is ignored by REO.
994 
995 
996 
997 			<enum 0 rxdma_error_detected> RXDMA detected an error an
998 			pushed this frame to this queue
999 
1000 			<enum 1 rxdma_routing_instruction> RXDMA pushed the
1001 			frame to this queue per received routing instructions. No
1002 			error within RXDMA was detected
1003 
1004 			<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
1005 			result the MSDU link descriptor might not have the
1006 			last_msdu_in_mpdu_flag set, but instead WBM might just see a
1007 			NULL pointer in the MSDU link descriptor. This is to be
1008 			considered a normal condition for this scenario.
1009 
1010 
1011 
1012 			<legal 0 - 2>
1013 */
1014 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
1015 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
1016 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
1017 
1018 /* Description		REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
1019 
1020 			Field only valid when 'rxdma_push_reason' set to
1021 			'rxdma_error_detected'.
1022 
1023 
1024 
1025 			This field is ignored by REO.
1026 
1027 
1028 
1029 			<enum 0 rxdma_overflow_err>MPDU frame is not complete
1030 			due to a FIFO overflow error in RXPCU.
1031 
1032 			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
1033 			due to receiving incomplete MPDU from the PHY
1034 
1035 
1036 			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
1037 			error or CRYPTO received an encrypted frame, but did not get
1038 			a valid corresponding key id in the peer entry.
1039 
1040 			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
1041 			error
1042 
1043 			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
1044 			unencrypted frame error when encrypted was expected
1045 
1046 			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
1047 			length error
1048 
1049 			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
1050 			number of MSDUs allowed in an MPDU got exceeded
1051 
1052 			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
1053 			error
1054 
1055 			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
1056 			parsing error
1057 
1058 			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
1059 			during SA search
1060 
1061 			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
1062 			during DA search
1063 
1064 			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
1065 			timeout during flow search
1066 
1067 			<enum 13 Rxdma_flush_request>RXDMA received a flush
1068 			request
1069 */
1070 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
1071 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
1072 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
1073 
1074 /* Description		REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER
1075 
1076 			Field only valid when Reo_level_mpdu_frame_info.
1077 
1078 			Rx_mpdu_desc_info_details.
1079 
1080 			Fragment_flag  is set.
1081 
1082 
1083 
1084 			The fragment number from the 802.11 header.
1085 
1086 
1087 
1088 			Note that the sequence number is embedded in field:
1089 			Reo_level_mpdu_frame_info.
1090 
1091 			Rx_mpdu_desc_info_details.
1092 
1093 			Mpdu_Sequence_number
1094 
1095 
1096 
1097 			<legal all>
1098 */
1099 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET              0x00000018
1100 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB                 7
1101 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK                0x00000780
1102 
1103 /* Description		REO_ENTRANCE_RING_6_RESERVED_6A
1104 
1105 			<legal 0>
1106 */
1107 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
1108 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          11
1109 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xfffff800
1110 
1111 /* Description		REO_ENTRANCE_RING_7_RESERVED_7A
1112 
1113 			<legal 0>
1114 */
1115 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
1116 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
1117 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
1118 
1119 /* Description		REO_ENTRANCE_RING_7_RING_ID
1120 
1121 			Consumer: SW/REO/DEBUG
1122 
1123 			Producer: SRNG (of RXDMA)
1124 
1125 
1126 
1127 			For debugging.
1128 
1129 			This field is filled in by the SRNG module.
1130 
1131 			It help to identify the ring that is being looked <legal
1132 			all>
1133 */
1134 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
1135 #define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
1136 #define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
1137 
1138 /* Description		REO_ENTRANCE_RING_7_LOOPING_COUNT
1139 
1140 			Consumer: SW/REO/DEBUG
1141 
1142 			Producer: SRNG (of RXDMA)
1143 
1144 
1145 
1146 			For debugging.
1147 
1148 			This field is filled in by the SRNG module.
1149 
1150 
1151 
1152 			A count value that indicates the number of times the
1153 			producer of entries into this Ring has looped around the
1154 			ring.
1155 
1156 			At initialization time, this value is set to 0. On the
1157 			first loop, this value is set to 1. After the max value is
1158 			reached allowed by the number of bits for this field, the
1159 			count value continues with 0 again.
1160 
1161 
1162 
1163 			In case SW is the consumer of the ring entries, it can
1164 			use this field to figure out up to where the producer of
1165 			entries has created new entries. This eliminates the need to
1166 			check where the head pointer' of the ring is located once
1167 			the SW starts processing an interrupt indicating that new
1168 			entries have been put into this ring...
1169 
1170 
1171 
1172 			Also note that SW if it wants only needs to look at the
1173 			LSB bit of this count value.
1174 
1175 			<legal all>
1176 */
1177 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
1178 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
1179 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
1180 
1181 
1182 #endif // _REO_ENTRANCE_RING_H_
1183