1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _REO_FLUSH_CACHE_H_ 24 #define _REO_FLUSH_CACHE_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_reo_cmd_header.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 struct uniform_reo_cmd_header cmd_header; 34 // 1 flush_addr_31_0[31:0] 35 // 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15] 36 // 3 reserved_3a[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[31:0] 40 // 7 reserved_7a[31:0] 41 // 8 reserved_8a[31:0] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 46 47 struct reo_flush_cache { 48 struct uniform_reo_cmd_header cmd_header; 49 uint32_t flush_addr_31_0 : 32; //[31:0] 50 uint32_t flush_addr_39_32 : 8, //[7:0] 51 forward_all_mpdus_in_queue : 1, //[8] 52 release_cache_block_index : 1, //[9] 53 cache_block_resource_index : 2, //[11:10] 54 flush_without_invalidate : 1, //[12] 55 block_cache_usage_after_flush : 1, //[13] 56 flush_entire_cache : 1, //[14] 57 reserved_2b : 17; //[31:15] 58 uint32_t reserved_3a : 32; //[31:0] 59 uint32_t reserved_4a : 32; //[31:0] 60 uint32_t reserved_5a : 32; //[31:0] 61 uint32_t reserved_6a : 32; //[31:0] 62 uint32_t reserved_7a : 32; //[31:0] 63 uint32_t reserved_8a : 32; //[31:0] 64 }; 65 66 /* 67 68 struct uniform_reo_cmd_header cmd_header 69 70 Consumer: REO 71 72 Producer: SW 73 74 75 76 Details for command execution tracking purposes. 77 78 flush_addr_31_0 79 80 Consumer: REO 81 82 Producer: SW 83 84 85 86 Address (lower 32 bits) of the descriptor to flush 87 88 <legal all> 89 90 flush_addr_39_32 91 92 Consumer: REO 93 94 Producer: SW 95 96 97 98 Address (upper 8 bits) of the descriptor to flush 99 100 <legal all> 101 102 forward_all_mpdus_in_queue 103 104 Is only allowed to be set when the flush address 105 corresponds with a REO descriptor. 106 107 108 109 When set, REO shall first forward all the MPDUs held in 110 the indicated re-order queue, before flushing the descriptor 111 from the cache. 112 113 <legal all> 114 115 release_cache_block_index 116 117 Field not valid when Flush_entire_cache is set. 118 119 120 121 If SW has previously used a blocking resource that it 122 now wants to re-use for this command, this bit shall be set. 123 It prevents SW from having to send a separate 124 REO_UNBLOCK_CACHE command. 125 126 127 128 When set, HW will first release the blocking resource 129 (indicated in field 'Cache_block_resouce_index') before this 130 command gets executed. 131 132 If that resource was already unblocked, this will be 133 considered an error. This command will not be executed, and 134 an error shall be returned. 135 136 <legal all> 137 138 cache_block_resource_index 139 140 Field not valid when Flush_entire_cache is set. 141 142 143 144 Indicates which of the four blocking resources in REO 145 will be assigned for managing the blocking of this 146 (descriptor) address 147 148 <legal all> 149 150 flush_without_invalidate 151 152 Field not valid when Flush_entire_cache is set. 153 154 155 156 When set, REO shall flush the cache line contents from 157 the cache, but there is NO need to invalidate the cache line 158 entry... The contents in the cache can be maintained. This 159 feature can be used by SW (and DV) to get a current snapshot 160 of the contents in the cache 161 162 163 164 <legal all> 165 166 block_cache_usage_after_flush 167 168 Field not valid when Flush_entire_cache is set. 169 170 171 172 When set, REO shall block any cache accesses to this 173 address till explicitly unblocked. 174 175 176 177 Whenever SW sets this bit, SW shall also set bit 178 'Forward_all_mpdus_in_queue' to ensure all packets are 179 flushed out in order to make sure this queue desc is not in 180 one of the aging link lists. In case SW does not want to 181 flush the MPDUs in the queue, see the recipe description 182 below this TLV definition. 183 184 185 186 The 'blocking' index to be used for this is indicated in 187 field 'cache_block_resource_index'. If SW had previously 188 used this blocking resource and was not freed up yet, SW 189 shall first unblock that index (by setting bit 190 Release_cache_block_index) or use an unblock command. 191 192 193 194 If the resource indicated here was already blocked (and 195 did not get unblocked in this command), it is considered an 196 error scenario... 197 198 No flush shall happen. The status for this command shall 199 indicate error. 200 201 202 203 <legal all> 204 205 flush_entire_cache 206 207 When set, the entire cache shall be flushed. The entire 208 cache will also remain blocked, till the 209 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 210 to unblock_cache. All other fields in this command are to be 211 ignored. 212 213 214 215 Note that flushing the entire cache has no changes to 216 the current settings of the blocking resource settings 217 218 219 220 <legal all> 221 222 reserved_2b 223 224 <legal 0> 225 226 reserved_3a 227 228 <legal 0> 229 230 reserved_4a 231 232 <legal 0> 233 234 reserved_5a 235 236 <legal 0> 237 238 reserved_6a 239 240 <legal 0> 241 242 reserved_7a 243 244 <legal 0> 245 246 reserved_8a 247 248 <legal 0> 249 */ 250 251 252 /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ 253 254 255 /* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER 256 257 Consumer: REO/SW/DEBUG 258 259 Producer: SW 260 261 262 263 This number can be used by SW to track, identify and 264 link the created commands with the command statusses 265 266 267 268 269 270 <legal all> 271 */ 272 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 273 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 274 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 275 276 /* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED 277 278 Consumer: REO 279 280 Producer: SW 281 282 283 284 <enum 0 NoStatus> REO does not need to generate a status 285 TLV for the execution of this command 286 287 <enum 1 StatusRequired> REO shall generate a status TLV 288 for the execution of this command 289 290 291 292 <legal all> 293 */ 294 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 295 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 296 #define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 297 298 /* Description REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A 299 300 <legal 0> 301 */ 302 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 303 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 304 #define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 305 306 /* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0 307 308 Consumer: REO 309 310 Producer: SW 311 312 313 314 Address (lower 32 bits) of the descriptor to flush 315 316 <legal all> 317 */ 318 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 319 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 320 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff 321 322 /* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32 323 324 Consumer: REO 325 326 Producer: SW 327 328 329 330 Address (upper 8 bits) of the descriptor to flush 331 332 <legal all> 333 */ 334 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 335 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 336 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff 337 338 /* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE 339 340 Is only allowed to be set when the flush address 341 corresponds with a REO descriptor. 342 343 344 345 When set, REO shall first forward all the MPDUs held in 346 the indicated re-order queue, before flushing the descriptor 347 from the cache. 348 349 <legal all> 350 */ 351 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 352 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 353 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 354 355 /* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX 356 357 Field not valid when Flush_entire_cache is set. 358 359 360 361 If SW has previously used a blocking resource that it 362 now wants to re-use for this command, this bit shall be set. 363 It prevents SW from having to send a separate 364 REO_UNBLOCK_CACHE command. 365 366 367 368 When set, HW will first release the blocking resource 369 (indicated in field 'Cache_block_resouce_index') before this 370 command gets executed. 371 372 If that resource was already unblocked, this will be 373 considered an error. This command will not be executed, and 374 an error shall be returned. 375 376 <legal all> 377 */ 378 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 379 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 380 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 381 382 /* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX 383 384 Field not valid when Flush_entire_cache is set. 385 386 387 388 Indicates which of the four blocking resources in REO 389 will be assigned for managing the blocking of this 390 (descriptor) address 391 392 <legal all> 393 */ 394 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 395 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 396 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 397 398 /* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE 399 400 Field not valid when Flush_entire_cache is set. 401 402 403 404 When set, REO shall flush the cache line contents from 405 the cache, but there is NO need to invalidate the cache line 406 entry... The contents in the cache can be maintained. This 407 feature can be used by SW (and DV) to get a current snapshot 408 of the contents in the cache 409 410 411 412 <legal all> 413 */ 414 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 415 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 416 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 417 418 /* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH 419 420 Field not valid when Flush_entire_cache is set. 421 422 423 424 When set, REO shall block any cache accesses to this 425 address till explicitly unblocked. 426 427 428 429 Whenever SW sets this bit, SW shall also set bit 430 'Forward_all_mpdus_in_queue' to ensure all packets are 431 flushed out in order to make sure this queue desc is not in 432 one of the aging link lists. In case SW does not want to 433 flush the MPDUs in the queue, see the recipe description 434 below this TLV definition. 435 436 437 438 The 'blocking' index to be used for this is indicated in 439 field 'cache_block_resource_index'. If SW had previously 440 used this blocking resource and was not freed up yet, SW 441 shall first unblock that index (by setting bit 442 Release_cache_block_index) or use an unblock command. 443 444 445 446 If the resource indicated here was already blocked (and 447 did not get unblocked in this command), it is considered an 448 error scenario... 449 450 No flush shall happen. The status for this command shall 451 indicate error. 452 453 454 455 <legal all> 456 */ 457 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 458 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 459 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 460 461 /* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE 462 463 When set, the entire cache shall be flushed. The entire 464 cache will also remain blocked, till the 465 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 466 to unblock_cache. All other fields in this command are to be 467 ignored. 468 469 470 471 Note that flushing the entire cache has no changes to 472 the current settings of the blocking resource settings 473 474 475 476 <legal all> 477 */ 478 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 479 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 480 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 481 482 /* Description REO_FLUSH_CACHE_2_RESERVED_2B 483 484 <legal 0> 485 */ 486 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 487 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 488 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 489 490 /* Description REO_FLUSH_CACHE_3_RESERVED_3A 491 492 <legal 0> 493 */ 494 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c 495 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 496 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff 497 498 /* Description REO_FLUSH_CACHE_4_RESERVED_4A 499 500 <legal 0> 501 */ 502 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 503 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 504 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff 505 506 /* Description REO_FLUSH_CACHE_5_RESERVED_5A 507 508 <legal 0> 509 */ 510 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 511 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 512 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff 513 514 /* Description REO_FLUSH_CACHE_6_RESERVED_6A 515 516 <legal 0> 517 */ 518 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 519 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 520 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff 521 522 /* Description REO_FLUSH_CACHE_7_RESERVED_7A 523 524 <legal 0> 525 */ 526 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c 527 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 528 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff 529 530 /* Description REO_FLUSH_CACHE_8_RESERVED_8A 531 532 <legal 0> 533 */ 534 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 535 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 536 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff 537 538 539 #endif // _REO_FLUSH_CACHE_H_ 540