1 /*
2  * Copyright (c) 2016 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 // $ATH_LICENSE_HW_HDR_C$
20 //
21 // DO NOT EDIT!  This file is automatically generated
22 //               These definitions are tied to a particular hardware layout
23 
24 
25 #ifndef _RX_REO_QUEUE_H_
26 #define _RX_REO_QUEUE_H_
27 #if !defined(__ASSEMBLER__)
28 #endif
29 
30 #include "uniform_descriptor_header.h"
31 
32 // ################ START SUMMARY #################
33 //
34 //	Dword	Fields
35 //	0	struct uniform_descriptor_header descriptor_header;
36 //	1	receive_queue_number[15:0], reserved_1b[31:16]
37 //	2	vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26]
38 //	3	svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31]
39 //	4	pn_31_0[31:0]
40 //	5	pn_63_32[31:0]
41 //	6	pn_95_64[31:0]
42 //	7	pn_127_96[31:0]
43 //	8	last_rx_enqueue_timestamp[31:0]
44 //	9	last_rx_dequeue_timestamp[31:0]
45 //	10	ptr_to_next_aging_queue_31_0[31:0]
46 //	11	ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8]
47 //	12	ptr_to_previous_aging_queue_31_0[31:0]
48 //	13	ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8]
49 //	14	rx_bitmap_31_0[31:0]
50 //	15	rx_bitmap_63_32[31:0]
51 //	16	rx_bitmap_95_64[31:0]
52 //	17	rx_bitmap_127_96[31:0]
53 //	18	rx_bitmap_159_128[31:0]
54 //	19	rx_bitmap_191_160[31:0]
55 //	20	rx_bitmap_223_192[31:0]
56 //	21	rx_bitmap_255_224[31:0]
57 //	22	current_mpdu_count[6:0], current_msdu_count[31:7]
58 //	23	reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
59 //	24	frames_in_order_count[23:0], bar_received_count[31:24]
60 //	25	mpdu_frames_processed_count[31:0]
61 //	26	msdu_frames_processed_count[31:0]
62 //	27	total_processed_byte_count[31:0]
63 //	28	late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
64 //	29	reserved_29[31:0]
65 //	30	reserved_30[31:0]
66 //	31	reserved_31[31:0]
67 //
68 // ################ END SUMMARY #################
69 
70 #define NUM_OF_DWORDS_RX_REO_QUEUE 32
71 
72 struct rx_reo_queue {
73     struct            uniform_descriptor_header                       descriptor_header;
74              uint32_t receive_queue_number            : 16, //[15:0]
75                       reserved_1b                     : 16; //[31:16]
76              uint32_t vld                             :  1, //[0]
77                       associated_link_descriptor_counter:  2, //[2:1]
78                       disable_duplicate_detection     :  1, //[3]
79                       soft_reorder_enable             :  1, //[4]
80                       ac                              :  2, //[6:5]
81                       bar                             :  1, //[7]
82                       rty                             :  1, //[8]
83                       chk_2k_mode                     :  1, //[9]
84                       oor_mode                        :  1, //[10]
85                       ba_window_size                  :  8, //[18:11]
86                       pn_check_needed                 :  1, //[19]
87                       pn_shall_be_even                :  1, //[20]
88                       pn_shall_be_uneven              :  1, //[21]
89                       pn_handling_enable              :  1, //[22]
90                       pn_size                         :  2, //[24:23]
91                       ignore_ampdu_flag               :  1, //[25]
92                       reserved_2b                     :  6; //[31:26]
93              uint32_t svld                            :  1, //[0]
94                       ssn                             : 12, //[12:1]
95                       current_index                   :  8, //[20:13]
96                       seq_2k_error_detected_flag      :  1, //[21]
97                       pn_error_detected_flag          :  1, //[22]
98                       reserved_3a                     :  8, //[30:23]
99                       pn_valid                        :  1; //[31]
100              uint32_t pn_31_0                         : 32; //[31:0]
101              uint32_t pn_63_32                        : 32; //[31:0]
102              uint32_t pn_95_64                        : 32; //[31:0]
103              uint32_t pn_127_96                       : 32; //[31:0]
104              uint32_t last_rx_enqueue_timestamp       : 32; //[31:0]
105              uint32_t last_rx_dequeue_timestamp       : 32; //[31:0]
106              uint32_t ptr_to_next_aging_queue_31_0    : 32; //[31:0]
107              uint32_t ptr_to_next_aging_queue_39_32   :  8, //[7:0]
108                       reserved_11a                    : 24; //[31:8]
109              uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0]
110              uint32_t ptr_to_previous_aging_queue_39_32:  8, //[7:0]
111                       reserved_13a                    : 24; //[31:8]
112              uint32_t rx_bitmap_31_0                  : 32; //[31:0]
113              uint32_t rx_bitmap_63_32                 : 32; //[31:0]
114              uint32_t rx_bitmap_95_64                 : 32; //[31:0]
115              uint32_t rx_bitmap_127_96                : 32; //[31:0]
116              uint32_t rx_bitmap_159_128               : 32; //[31:0]
117              uint32_t rx_bitmap_191_160               : 32; //[31:0]
118              uint32_t rx_bitmap_223_192               : 32; //[31:0]
119              uint32_t rx_bitmap_255_224               : 32; //[31:0]
120              uint32_t current_mpdu_count              :  7, //[6:0]
121                       current_msdu_count              : 25; //[31:7]
122              uint32_t reserved_23                     :  4, //[3:0]
123                       timeout_count                   :  6, //[9:4]
124                       forward_due_to_bar_count        :  6, //[15:10]
125                       duplicate_count                 : 16; //[31:16]
126              uint32_t frames_in_order_count           : 24, //[23:0]
127                       bar_received_count              :  8; //[31:24]
128              uint32_t mpdu_frames_processed_count     : 32; //[31:0]
129              uint32_t msdu_frames_processed_count     : 32; //[31:0]
130              uint32_t total_processed_byte_count      : 32; //[31:0]
131              uint32_t late_receive_mpdu_count         : 12, //[11:0]
132                       window_jump_2k                  :  4, //[15:12]
133                       hole_count                      : 16; //[31:16]
134              uint32_t reserved_29                     : 32; //[31:0]
135              uint32_t reserved_30                     : 32; //[31:0]
136              uint32_t reserved_31                     : 32; //[31:0]
137 };
138 
139 /*
140 
141 struct uniform_descriptor_header descriptor_header
142 
143 			Details about which module owns this struct.
144 
145 			Note that sub field Buffer_type shall be set to
146 			Receive_REO_queue_descriptor
147 
148 receive_queue_number
149 
150 			Indicates the MPDU queue ID to which this MPDU link
151 			descriptor belongs
152 
153 			Used for tracking and debugging
154 
155 			<legal all>
156 
157 reserved_1b
158 
159 			<legal 0>
160 
161 vld
162 
163 			Valid bit indicating a session is established and the
164 			queue descriptor is valid(Filled by SW)
165 
166 			<legal all>
167 
168 associated_link_descriptor_counter
169 
170 			Indicates which of the 3 link descriptor counters shall
171 			be incremented or decremented when link descriptors are
172 			added or removed from this flow queue.
173 
174 			MSDU link descriptors related with MPDUs stored in the
175 			re-order buffer shall also be included in this count.
176 
177 
178 
179 			<legal 0-2>
180 
181 disable_duplicate_detection
182 
183 			When set, do not perform any duplicate detection.
184 
185 
186 
187 			<legal all>
188 
189 soft_reorder_enable
190 
191 			When set, REO has been instructed to not perform the
192 			actual re-ordering of frames for this queue, but just to
193 			insert the reorder opcodes.
194 
195 
196 
197 			Note that this implies that REO is also not going to
198 			perform any MSDU level operations, and the entire MPDU (and
199 			thus pointer to the MSDU link descriptor) will be pushed to
200 			a destination ring that SW has programmed in a SW
201 			programmable configuration register in REO
202 
203 
204 
205 			<legal all>
206 
207 ac
208 
209 			Indicates which access category the queue descriptor
210 			belongs to(filled by SW)
211 
212 			<legal all>
213 
214 bar
215 
216 			Indicates if  BAR has been received (mostly used for
217 			debug purpose and this is filled by REO)
218 
219 			<legal all>
220 
221 rty
222 
223 			Retry bit is checked if this bit is set.
224 
225 			<legal all>
226 
227 chk_2k_mode
228 
229 			Indicates what type of operation is expected from Reo
230 			when the received frame SN falls within the 2K window
231 
232 
233 
234 			See REO MLD document for programming details.
235 
236 			<legal all>
237 
238 oor_mode
239 
240 			Out of Order mode:
241 
242 			Indicates what type of operation is expected when the
243 			received frame falls within the OOR window.
244 
245 
246 
247 			See REO MLD document for programming details.
248 
249 			<legal all>
250 
251 ba_window_size
252 
253 			Indicates the negotiated (window size + 1).
254 
255 			it can go up to Max of 256bits.
256 
257 
258 
259 			A value 255 means 256 bitmap, 63 means 64 bitmap, 0
260 			(means non-BA session, with window size of 0). The 3 values
261 			here are the main values validated, but other values should
262 			work as well.
263 
264 
265 
266 			A BA window size of 0 (=> one frame entry bitmat), means
267 			that there is NO RX_REO_QUEUE_EXT descriptor following this
268 			RX_REO_QUEUE STRUCT in memory
269 
270 
271 
272 			A BA window size of 1 - 105, means that there is 1
273 			RX_REO_QUEUE_EXT descriptor directly following this
274 			RX_REO_QUEUE STRUCT in memory.
275 
276 
277 
278 			A BA window size of 106 - 210, means that there are 2
279 			RX_REO_QUEUE_EXT descriptors directly following this
280 			RX_REO_QUEUE STRUCT in memory
281 
282 
283 
284 			A BA window size of 211 - 256, means that there are 3
285 			RX_REO_QUEUE_EXT descriptors directly following this
286 			RX_REO_QUEUE STRUCT in memory
287 
288 
289 
290 			<legal 0 - 255>
291 
292 pn_check_needed
293 
294 			When set, REO shall perform the PN increment check
295 
296 			<legal all>
297 
298 pn_shall_be_even
299 
300 			Field only valid when 'pn_check_needed' is set.
301 
302 
303 
304 			When set, REO shall confirm that the received PN number
305 			is not only incremented, but also always an even number
306 
307 			<legal all>
308 
309 pn_shall_be_uneven
310 
311 			Field only valid when 'pn_check_needed' is set.
312 
313 
314 
315 			When set, REO shall confirm that the received PN number
316 			is not only incremented, but also always an uneven number
317 
318 			<legal all>
319 
320 pn_handling_enable
321 
322 			Field only valid when 'pn_check_needed' is set.
323 
324 
325 
326 			When set, and REO detected a PN error, HW shall set the
327 			'pn_error_detected_flag'.
328 
329 			<legal all>
330 
331 pn_size
332 
333 			Size of the PN field check.
334 
335 			Needed for wrap around handling...
336 
337 
338 
339 			<enum 0     pn_size_24>
340 
341 			<enum 1     pn_size_48>
342 
343 			<enum 2     pn_size_128>
344 
345 
346 
347 			<legal 0-2>
348 
349 ignore_ampdu_flag
350 
351 			When set, REO shall ignore the ampdu_flag on the
352 			entrance descriptor for this queue.
353 
354 			<legal all>
355 
356 reserved_2b
357 
358 			<legal 0>
359 
360 svld
361 
362 			Sequence number in next field is valid one. It can be
363 			filled by SW if the want to fill in the any negotiated SSN,
364 			otherwise REO will fill the sequence number of first
365 			received packet and set this bit to 1.
366 
367 			<legal all>
368 
369 ssn
370 
371 			Starting Sequence number of the session, this changes
372 			whenever window moves. (can be filled by SW then maintained
373 			by REO)
374 
375 			<legal all>
376 
377 current_index
378 
379 			Points to last forwarded packet
380 
381 			<legal all>
382 
383 seq_2k_error_detected_flag
384 
385 			Set by REO, can only be cleared by SW
386 
387 
388 
389 			When set, REO has detected a 2k error jump in the
390 			sequence number and from that moment forward, all new frames
391 			are forwarded directly to FW, without duplicate detect,
392 			reordering, etc.
393 
394 			<legal all>
395 
396 pn_error_detected_flag
397 
398 			Set by REO, can only be cleared by SW
399 
400 
401 
402 			When set, REO has detected a PN error and from that
403 			moment forward, all new frames are forwarded directly to FW,
404 			without duplicate detect, reordering, etc.
405 
406 			<legal all>
407 
408 reserved_3a
409 
410 			<legal 0>
411 
412 pn_valid
413 
414 			PN number in next fields are valid. It can be filled by
415 			SW if it wants to fill in the any negotiated SSN, otherwise
416 			REO will fill the pn based on the first received packet and
417 			set this bit to 1.
418 
419 			<legal all>
420 
421 pn_31_0
422 
423 
424 			<legal all>
425 
426 pn_63_32
427 
428 			Bits [63:32] of the PN number.
429 
430 			<legal all>
431 
432 pn_95_64
433 
434 			Bits [95:64] of the PN number.
435 
436 			<legal all>
437 
438 pn_127_96
439 
440 			Bits [127:96] of the PN number.
441 
442 			<legal all>
443 
444 last_rx_enqueue_timestamp
445 
446 			This timestamp is updated when an MPDU is received and
447 			accesses this Queue Descriptor. It does not include the
448 			access due to Command TLVs or Aging (which will be updated
449 			in Last_rx_dequeue_timestamp).
450 
451 			<legal all>
452 
453 last_rx_dequeue_timestamp
454 
455 			This timestamp is used for Aging. When an MPDU or
456 			multiple MPDUs are forwarded, either due to window movement,
457 			bar, aging or command flush, this timestamp is updated. Also
458 			when the bitmap is all zero and the first time an MPDU is
459 			queued (opcode=QCUR), this timestamp is updated for aging.
460 
461 			<legal all>
462 
463 ptr_to_next_aging_queue_31_0
464 
465 			Address  (address bits 31-0)of next RX_REO_QUEUE
466 			descriptor in the 'receive timestamp' ordered list.
467 
468 			From it the Position of this queue descriptor in the per
469 			AC aging waitlist  can be derived.
470 
471 			Value 0x0 indicates the 'NULL' pointer which implies
472 			that this is the last entry in the list.
473 
474 			<legal all>
475 
476 ptr_to_next_aging_queue_39_32
477 
478 			Address  (address bits 39-32)of next RX_REO_QUEUE
479 			descriptor in the 'receive timestamp' ordered list.
480 
481 			From it the Position of this queue descriptor in the per
482 			AC aging waitlist  can be derived.
483 
484 			Value 0x0 indicates the 'NULL' pointer which implies
485 			that this is the last entry in the list.
486 
487 			<legal all>
488 
489 reserved_11a
490 
491 			<legal 0>
492 
493 ptr_to_previous_aging_queue_31_0
494 
495 			Address  (address bits 31-0)of next RX_REO_QUEUE
496 			descriptor in the 'receive timestamp' ordered list.
497 
498 			From it the Position of this queue descriptor in the per
499 			AC aging waitlist  can be derived.
500 
501 			Value 0x0 indicates the 'NULL' pointer which implies
502 			that this is the first entry in the list.
503 
504 			<legal all>
505 
506 ptr_to_previous_aging_queue_39_32
507 
508 			Address  (address bits 39-32)of next RX_REO_QUEUE
509 			descriptor in the 'receive timestamp' ordered list.
510 
511 			From it the Position of this queue descriptor in the per
512 			AC aging waitlist  can be derived.
513 
514 			Value 0x0 indicates the 'NULL' pointer which implies
515 			that this is the first entry in the list.
516 
517 			<legal all>
518 
519 reserved_13a
520 
521 			<legal 0>
522 
523 rx_bitmap_31_0
524 
525 			When a bit is set, the corresponding frame is currently
526 			held in the re-order queue.
527 
528 			The bitmap  is Fully managed by HW.
529 
530 			SW shall init this to 0, and then never ever change it
531 
532 			<legal all>
533 
534 rx_bitmap_63_32
535 
536 			See Rx_bitmap_31_0 description
537 
538 			<legal all>
539 
540 rx_bitmap_95_64
541 
542 			See Rx_bitmap_31_0 description
543 
544 			<legal all>
545 
546 rx_bitmap_127_96
547 
548 			See Rx_bitmap_31_0 description
549 
550 			<legal all>
551 
552 rx_bitmap_159_128
553 
554 			See Rx_bitmap_31_0 description
555 
556 			<legal all>
557 
558 rx_bitmap_191_160
559 
560 			See Rx_bitmap_31_0 description
561 
562 			<legal all>
563 
564 rx_bitmap_223_192
565 
566 			See Rx_bitmap_31_0 description
567 
568 			<legal all>
569 
570 rx_bitmap_255_224
571 
572 			See Rx_bitmap_31_0 description
573 
574 			<legal all>
575 
576 current_mpdu_count
577 
578 			The number of MPDUs in the queue.
579 
580 
581 
582 			<legal all>
583 
584 current_msdu_count
585 
586 			The number of MSDUs in the queue.
587 
588 			<legal all>
589 
590 reserved_23
591 
592 			<legal 0>
593 
594 timeout_count
595 
596 			The number of times that REO started forwarding frames
597 			even though there is a hole in the bitmap. Forwarding reason
598 			is Timeout
599 
600 
601 
602 			The counter saturates and freezes at 0x3F
603 
604 
605 
606 			<legal all>
607 
608 forward_due_to_bar_count
609 
610 			The number of times that REO started forwarding frames
611 			even though there is a hole in the bitmap. Forwarding reason
612 			is reception of BAR frame.
613 
614 
615 
616 			The counter saturates and freezes at 0x3F
617 
618 
619 
620 			<legal all>
621 
622 duplicate_count
623 
624 			The number of duplicate frames that have been detected
625 
626 			<legal all>
627 
628 frames_in_order_count
629 
630 			The number of frames that have been received in order
631 			(without a hole that prevented them from being forwarded
632 			immediately)
633 
634 
635 
636 			This corresponds to the Reorder opcodes:
637 
638 			'FWDCUR' and 'FWD BUF'
639 
640 
641 
642 			<legal all>
643 
644 bar_received_count
645 
646 			The number of times a BAR frame is received.
647 
648 
649 
650 			This corresponds to the Reorder opcodes with 'DROP'
651 
652 
653 
654 			The counter saturates and freezes at 0xFF
655 
656 			<legal all>
657 
658 mpdu_frames_processed_count
659 
660 			The total number of MPDU frames that have been processed
661 			by REO. 'Processing' here means that REO has received them
662 			out of the entrance ring, and retrieved the corresponding
663 			RX_REO_QUEUE Descriptor.
664 
665 
666 
667 			Note that this count includes duplicates, frames that
668 			later had errors, etc.
669 
670 
671 
672 			Note that field 'Duplicate_count' indicates how many of
673 			these MPDUs were duplicates.
674 
675 
676 
677 			<legal all>
678 
679 msdu_frames_processed_count
680 
681 			The total number of MSDU frames that have been processed
682 			by REO. 'Processing' here means that REO has received them
683 			out of the entrance ring, and retrieved the corresponding
684 			RX_REO_QUEUE Descriptor.
685 
686 
687 
688 			Note that this count includes duplicates, frames that
689 			later had errors, etc.
690 
691 
692 
693 			<legal all>
694 
695 total_processed_byte_count
696 
697 			An approximation of the number of bytes processed for
698 			this queue.
699 
700 			'Processing' here means that REO has received them out
701 			of the entrance ring, and retrieved the corresponding
702 			RX_REO_QUEUE Descriptor.
703 
704 
705 
706 			Note that this count includes duplicates, frames that
707 			later had errors, etc.
708 
709 
710 
711 			In 64 byte units
712 
713 			<legal all>
714 
715 late_receive_mpdu_count
716 
717 			The number of MPDUs received after the window had
718 			already moved on. The 'late' sequence window is defined as
719 			(Window SSN - 256) - (Window SSN - 1)
720 
721 
722 
723 			This corresponds with Out of order detection in
724 			duplicate detect FSM
725 
726 
727 
728 			The counter saturates and freezes at 0xFFF
729 
730 
731 
732 			<legal all>
733 
734 window_jump_2k
735 
736 			The number of times the window moved more then 2K
737 
738 
739 
740 			The counter saturates and freezes at 0xF
741 
742 
743 
744 			(Note: field name can not start with number: previous
745 			2k_window_jump)
746 
747 
748 
749 			<legal all>
750 
751 hole_count
752 
753 			The number of times a hole was created in the receive
754 			bitmap.
755 
756 
757 
758 			This corresponds to the Reorder opcodes with 'QCUR'
759 
760 
761 
762 			<legal all>
763 
764 reserved_29
765 
766 			<legal 0>
767 
768 reserved_30
769 
770 			<legal 0>
771 
772 reserved_31
773 
774 			<legal 0>
775 */
776 
777 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
778 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
779 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
780 
781 /* Description		RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER
782 
783 			Indicates the MPDU queue ID to which this MPDU link
784 			descriptor belongs
785 
786 			Used for tracking and debugging
787 
788 			<legal all>
789 */
790 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET                   0x00000004
791 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB                      0
792 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
793 
794 /* Description		RX_REO_QUEUE_1_RESERVED_1B
795 
796 			<legal 0>
797 */
798 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET                            0x00000004
799 #define RX_REO_QUEUE_1_RESERVED_1B_LSB                               16
800 #define RX_REO_QUEUE_1_RESERVED_1B_MASK                              0xffff0000
801 
802 /* Description		RX_REO_QUEUE_2_VLD
803 
804 			Valid bit indicating a session is established and the
805 			queue descriptor is valid(Filled by SW)
806 
807 			<legal all>
808 */
809 #define RX_REO_QUEUE_2_VLD_OFFSET                                    0x00000008
810 #define RX_REO_QUEUE_2_VLD_LSB                                       0
811 #define RX_REO_QUEUE_2_VLD_MASK                                      0x00000001
812 
813 /* Description		RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
814 
815 			Indicates which of the 3 link descriptor counters shall
816 			be incremented or decremented when link descriptors are
817 			added or removed from this flow queue.
818 
819 			MSDU link descriptors related with MPDUs stored in the
820 			re-order buffer shall also be included in this count.
821 
822 
823 
824 			<legal 0-2>
825 */
826 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET     0x00000008
827 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB        1
828 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK       0x00000006
829 
830 /* Description		RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION
831 
832 			When set, do not perform any duplicate detection.
833 
834 
835 
836 			<legal all>
837 */
838 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET            0x00000008
839 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB               3
840 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK              0x00000008
841 
842 /* Description		RX_REO_QUEUE_2_SOFT_REORDER_ENABLE
843 
844 			When set, REO has been instructed to not perform the
845 			actual re-ordering of frames for this queue, but just to
846 			insert the reorder opcodes.
847 
848 
849 
850 			Note that this implies that REO is also not going to
851 			perform any MSDU level operations, and the entire MPDU (and
852 			thus pointer to the MSDU link descriptor) will be pushed to
853 			a destination ring that SW has programmed in a SW
854 			programmable configuration register in REO
855 
856 
857 
858 			<legal all>
859 */
860 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET                    0x00000008
861 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB                       4
862 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK                      0x00000010
863 
864 /* Description		RX_REO_QUEUE_2_AC
865 
866 			Indicates which access category the queue descriptor
867 			belongs to(filled by SW)
868 
869 			<legal all>
870 */
871 #define RX_REO_QUEUE_2_AC_OFFSET                                     0x00000008
872 #define RX_REO_QUEUE_2_AC_LSB                                        5
873 #define RX_REO_QUEUE_2_AC_MASK                                       0x00000060
874 
875 /* Description		RX_REO_QUEUE_2_BAR
876 
877 			Indicates if  BAR has been received (mostly used for
878 			debug purpose and this is filled by REO)
879 
880 			<legal all>
881 */
882 #define RX_REO_QUEUE_2_BAR_OFFSET                                    0x00000008
883 #define RX_REO_QUEUE_2_BAR_LSB                                       7
884 #define RX_REO_QUEUE_2_BAR_MASK                                      0x00000080
885 
886 /* Description		RX_REO_QUEUE_2_RTY
887 
888 			Retry bit is checked if this bit is set.
889 
890 			<legal all>
891 */
892 #define RX_REO_QUEUE_2_RTY_OFFSET                                    0x00000008
893 #define RX_REO_QUEUE_2_RTY_LSB                                       8
894 #define RX_REO_QUEUE_2_RTY_MASK                                      0x00000100
895 
896 /* Description		RX_REO_QUEUE_2_CHK_2K_MODE
897 
898 			Indicates what type of operation is expected from Reo
899 			when the received frame SN falls within the 2K window
900 
901 
902 
903 			See REO MLD document for programming details.
904 
905 			<legal all>
906 */
907 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET                            0x00000008
908 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB                               9
909 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK                              0x00000200
910 
911 /* Description		RX_REO_QUEUE_2_OOR_MODE
912 
913 			Out of Order mode:
914 
915 			Indicates what type of operation is expected when the
916 			received frame falls within the OOR window.
917 
918 
919 
920 			See REO MLD document for programming details.
921 
922 			<legal all>
923 */
924 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET                               0x00000008
925 #define RX_REO_QUEUE_2_OOR_MODE_LSB                                  10
926 #define RX_REO_QUEUE_2_OOR_MODE_MASK                                 0x00000400
927 
928 /* Description		RX_REO_QUEUE_2_BA_WINDOW_SIZE
929 
930 			Indicates the negotiated (window size + 1).
931 
932 			it can go up to Max of 256bits.
933 
934 
935 
936 			A value 255 means 256 bitmap, 63 means 64 bitmap, 0
937 			(means non-BA session, with window size of 0). The 3 values
938 			here are the main values validated, but other values should
939 			work as well.
940 
941 
942 
943 			A BA window size of 0 (=> one frame entry bitmat), means
944 			that there is NO RX_REO_QUEUE_EXT descriptor following this
945 			RX_REO_QUEUE STRUCT in memory
946 
947 
948 
949 			A BA window size of 1 - 105, means that there is 1
950 			RX_REO_QUEUE_EXT descriptor directly following this
951 			RX_REO_QUEUE STRUCT in memory.
952 
953 
954 
955 			A BA window size of 106 - 210, means that there are 2
956 			RX_REO_QUEUE_EXT descriptors directly following this
957 			RX_REO_QUEUE STRUCT in memory
958 
959 
960 
961 			A BA window size of 211 - 256, means that there are 3
962 			RX_REO_QUEUE_EXT descriptors directly following this
963 			RX_REO_QUEUE STRUCT in memory
964 
965 
966 
967 			<legal 0 - 255>
968 */
969 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET                         0x00000008
970 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB                            11
971 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK                           0x0007f800
972 
973 /* Description		RX_REO_QUEUE_2_PN_CHECK_NEEDED
974 
975 			When set, REO shall perform the PN increment check
976 
977 			<legal all>
978 */
979 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET                        0x00000008
980 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB                           19
981 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK                          0x00080000
982 
983 /* Description		RX_REO_QUEUE_2_PN_SHALL_BE_EVEN
984 
985 			Field only valid when 'pn_check_needed' is set.
986 
987 
988 
989 			When set, REO shall confirm that the received PN number
990 			is not only incremented, but also always an even number
991 
992 			<legal all>
993 */
994 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET                       0x00000008
995 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB                          20
996 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK                         0x00100000
997 
998 /* Description		RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN
999 
1000 			Field only valid when 'pn_check_needed' is set.
1001 
1002 
1003 
1004 			When set, REO shall confirm that the received PN number
1005 			is not only incremented, but also always an uneven number
1006 
1007 			<legal all>
1008 */
1009 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET                     0x00000008
1010 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB                        21
1011 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK                       0x00200000
1012 
1013 /* Description		RX_REO_QUEUE_2_PN_HANDLING_ENABLE
1014 
1015 			Field only valid when 'pn_check_needed' is set.
1016 
1017 
1018 
1019 			When set, and REO detected a PN error, HW shall set the
1020 			'pn_error_detected_flag'.
1021 
1022 			<legal all>
1023 */
1024 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET                     0x00000008
1025 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB                        22
1026 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK                       0x00400000
1027 
1028 /* Description		RX_REO_QUEUE_2_PN_SIZE
1029 
1030 			Size of the PN field check.
1031 
1032 			Needed for wrap around handling...
1033 
1034 
1035 
1036 			<enum 0     pn_size_24>
1037 
1038 			<enum 1     pn_size_48>
1039 
1040 			<enum 2     pn_size_128>
1041 
1042 
1043 
1044 			<legal 0-2>
1045 */
1046 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET                                0x00000008
1047 #define RX_REO_QUEUE_2_PN_SIZE_LSB                                   23
1048 #define RX_REO_QUEUE_2_PN_SIZE_MASK                                  0x01800000
1049 
1050 /* Description		RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG
1051 
1052 			When set, REO shall ignore the ampdu_flag on the
1053 			entrance descriptor for this queue.
1054 
1055 			<legal all>
1056 */
1057 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET                      0x00000008
1058 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB                         25
1059 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK                        0x02000000
1060 
1061 /* Description		RX_REO_QUEUE_2_RESERVED_2B
1062 
1063 			<legal 0>
1064 */
1065 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET                            0x00000008
1066 #define RX_REO_QUEUE_2_RESERVED_2B_LSB                               26
1067 #define RX_REO_QUEUE_2_RESERVED_2B_MASK                              0xfc000000
1068 
1069 /* Description		RX_REO_QUEUE_3_SVLD
1070 
1071 			Sequence number in next field is valid one. It can be
1072 			filled by SW if the want to fill in the any negotiated SSN,
1073 			otherwise REO will fill the sequence number of first
1074 			received packet and set this bit to 1.
1075 
1076 			<legal all>
1077 */
1078 #define RX_REO_QUEUE_3_SVLD_OFFSET                                   0x0000000c
1079 #define RX_REO_QUEUE_3_SVLD_LSB                                      0
1080 #define RX_REO_QUEUE_3_SVLD_MASK                                     0x00000001
1081 
1082 /* Description		RX_REO_QUEUE_3_SSN
1083 
1084 			Starting Sequence number of the session, this changes
1085 			whenever window moves. (can be filled by SW then maintained
1086 			by REO)
1087 
1088 			<legal all>
1089 */
1090 #define RX_REO_QUEUE_3_SSN_OFFSET                                    0x0000000c
1091 #define RX_REO_QUEUE_3_SSN_LSB                                       1
1092 #define RX_REO_QUEUE_3_SSN_MASK                                      0x00001ffe
1093 
1094 /* Description		RX_REO_QUEUE_3_CURRENT_INDEX
1095 
1096 			Points to last forwarded packet
1097 
1098 			<legal all>
1099 */
1100 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET                          0x0000000c
1101 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB                             13
1102 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK                            0x001fe000
1103 
1104 /* Description		RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG
1105 
1106 			Set by REO, can only be cleared by SW
1107 
1108 
1109 
1110 			When set, REO has detected a 2k error jump in the
1111 			sequence number and from that moment forward, all new frames
1112 			are forwarded directly to FW, without duplicate detect,
1113 			reordering, etc.
1114 
1115 			<legal all>
1116 */
1117 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET             0x0000000c
1118 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB                21
1119 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK               0x00200000
1120 
1121 /* Description		RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG
1122 
1123 			Set by REO, can only be cleared by SW
1124 
1125 
1126 
1127 			When set, REO has detected a PN error and from that
1128 			moment forward, all new frames are forwarded directly to FW,
1129 			without duplicate detect, reordering, etc.
1130 
1131 			<legal all>
1132 */
1133 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET                 0x0000000c
1134 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB                    22
1135 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK                   0x00400000
1136 
1137 /* Description		RX_REO_QUEUE_3_RESERVED_3A
1138 
1139 			<legal 0>
1140 */
1141 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET                            0x0000000c
1142 #define RX_REO_QUEUE_3_RESERVED_3A_LSB                               23
1143 #define RX_REO_QUEUE_3_RESERVED_3A_MASK                              0x7f800000
1144 
1145 /* Description		RX_REO_QUEUE_3_PN_VALID
1146 
1147 			PN number in next fields are valid. It can be filled by
1148 			SW if it wants to fill in the any negotiated SSN, otherwise
1149 			REO will fill the pn based on the first received packet and
1150 			set this bit to 1.
1151 
1152 			<legal all>
1153 */
1154 #define RX_REO_QUEUE_3_PN_VALID_OFFSET                               0x0000000c
1155 #define RX_REO_QUEUE_3_PN_VALID_LSB                                  31
1156 #define RX_REO_QUEUE_3_PN_VALID_MASK                                 0x80000000
1157 
1158 /* Description		RX_REO_QUEUE_4_PN_31_0
1159 
1160 
1161 			<legal all>
1162 */
1163 #define RX_REO_QUEUE_4_PN_31_0_OFFSET                                0x00000010
1164 #define RX_REO_QUEUE_4_PN_31_0_LSB                                   0
1165 #define RX_REO_QUEUE_4_PN_31_0_MASK                                  0xffffffff
1166 
1167 /* Description		RX_REO_QUEUE_5_PN_63_32
1168 
1169 			Bits [63:32] of the PN number.
1170 
1171 			<legal all>
1172 */
1173 #define RX_REO_QUEUE_5_PN_63_32_OFFSET                               0x00000014
1174 #define RX_REO_QUEUE_5_PN_63_32_LSB                                  0
1175 #define RX_REO_QUEUE_5_PN_63_32_MASK                                 0xffffffff
1176 
1177 /* Description		RX_REO_QUEUE_6_PN_95_64
1178 
1179 			Bits [95:64] of the PN number.
1180 
1181 			<legal all>
1182 */
1183 #define RX_REO_QUEUE_6_PN_95_64_OFFSET                               0x00000018
1184 #define RX_REO_QUEUE_6_PN_95_64_LSB                                  0
1185 #define RX_REO_QUEUE_6_PN_95_64_MASK                                 0xffffffff
1186 
1187 /* Description		RX_REO_QUEUE_7_PN_127_96
1188 
1189 			Bits [127:96] of the PN number.
1190 
1191 			<legal all>
1192 */
1193 #define RX_REO_QUEUE_7_PN_127_96_OFFSET                              0x0000001c
1194 #define RX_REO_QUEUE_7_PN_127_96_LSB                                 0
1195 #define RX_REO_QUEUE_7_PN_127_96_MASK                                0xffffffff
1196 
1197 /* Description		RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP
1198 
1199 			This timestamp is updated when an MPDU is received and
1200 			accesses this Queue Descriptor. It does not include the
1201 			access due to Command TLVs or Aging (which will be updated
1202 			in Last_rx_dequeue_timestamp).
1203 
1204 			<legal all>
1205 */
1206 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET              0x00000020
1207 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB                 0
1208 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK                0xffffffff
1209 
1210 /* Description		RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP
1211 
1212 			This timestamp is used for Aging. When an MPDU or
1213 			multiple MPDUs are forwarded, either due to window movement,
1214 			bar, aging or command flush, this timestamp is updated. Also
1215 			when the bitmap is all zero and the first time an MPDU is
1216 			queued (opcode=QCUR), this timestamp is updated for aging.
1217 
1218 			<legal all>
1219 */
1220 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET              0x00000024
1221 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB                 0
1222 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK                0xffffffff
1223 
1224 /* Description		RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0
1225 
1226 			Address  (address bits 31-0)of next RX_REO_QUEUE
1227 			descriptor in the 'receive timestamp' ordered list.
1228 
1229 			From it the Position of this queue descriptor in the per
1230 			AC aging waitlist  can be derived.
1231 
1232 			Value 0x0 indicates the 'NULL' pointer which implies
1233 			that this is the last entry in the list.
1234 
1235 			<legal all>
1236 */
1237 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET          0x00000028
1238 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB             0
1239 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK            0xffffffff
1240 
1241 /* Description		RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32
1242 
1243 			Address  (address bits 39-32)of next RX_REO_QUEUE
1244 			descriptor in the 'receive timestamp' ordered list.
1245 
1246 			From it the Position of this queue descriptor in the per
1247 			AC aging waitlist  can be derived.
1248 
1249 			Value 0x0 indicates the 'NULL' pointer which implies
1250 			that this is the last entry in the list.
1251 
1252 			<legal all>
1253 */
1254 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET         0x0000002c
1255 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB            0
1256 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK           0x000000ff
1257 
1258 /* Description		RX_REO_QUEUE_11_RESERVED_11A
1259 
1260 			<legal 0>
1261 */
1262 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET                          0x0000002c
1263 #define RX_REO_QUEUE_11_RESERVED_11A_LSB                             8
1264 #define RX_REO_QUEUE_11_RESERVED_11A_MASK                            0xffffff00
1265 
1266 /* Description		RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0
1267 
1268 			Address  (address bits 31-0)of next RX_REO_QUEUE
1269 			descriptor in the 'receive timestamp' ordered list.
1270 
1271 			From it the Position of this queue descriptor in the per
1272 			AC aging waitlist  can be derived.
1273 
1274 			Value 0x0 indicates the 'NULL' pointer which implies
1275 			that this is the first entry in the list.
1276 
1277 			<legal all>
1278 */
1279 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET      0x00000030
1280 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB         0
1281 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK        0xffffffff
1282 
1283 /* Description		RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32
1284 
1285 			Address  (address bits 39-32)of next RX_REO_QUEUE
1286 			descriptor in the 'receive timestamp' ordered list.
1287 
1288 			From it the Position of this queue descriptor in the per
1289 			AC aging waitlist  can be derived.
1290 
1291 			Value 0x0 indicates the 'NULL' pointer which implies
1292 			that this is the first entry in the list.
1293 
1294 			<legal all>
1295 */
1296 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET     0x00000034
1297 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB        0
1298 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK       0x000000ff
1299 
1300 /* Description		RX_REO_QUEUE_13_RESERVED_13A
1301 
1302 			<legal 0>
1303 */
1304 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET                          0x00000034
1305 #define RX_REO_QUEUE_13_RESERVED_13A_LSB                             8
1306 #define RX_REO_QUEUE_13_RESERVED_13A_MASK                            0xffffff00
1307 
1308 /* Description		RX_REO_QUEUE_14_RX_BITMAP_31_0
1309 
1310 			When a bit is set, the corresponding frame is currently
1311 			held in the re-order queue.
1312 
1313 			The bitmap  is Fully managed by HW.
1314 
1315 			SW shall init this to 0, and then never ever change it
1316 
1317 			<legal all>
1318 */
1319 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET                        0x00000038
1320 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB                           0
1321 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK                          0xffffffff
1322 
1323 /* Description		RX_REO_QUEUE_15_RX_BITMAP_63_32
1324 
1325 			See Rx_bitmap_31_0 description
1326 
1327 			<legal all>
1328 */
1329 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET                       0x0000003c
1330 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB                          0
1331 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK                         0xffffffff
1332 
1333 /* Description		RX_REO_QUEUE_16_RX_BITMAP_95_64
1334 
1335 			See Rx_bitmap_31_0 description
1336 
1337 			<legal all>
1338 */
1339 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET                       0x00000040
1340 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB                          0
1341 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK                         0xffffffff
1342 
1343 /* Description		RX_REO_QUEUE_17_RX_BITMAP_127_96
1344 
1345 			See Rx_bitmap_31_0 description
1346 
1347 			<legal all>
1348 */
1349 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET                      0x00000044
1350 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB                         0
1351 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK                        0xffffffff
1352 
1353 /* Description		RX_REO_QUEUE_18_RX_BITMAP_159_128
1354 
1355 			See Rx_bitmap_31_0 description
1356 
1357 			<legal all>
1358 */
1359 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET                     0x00000048
1360 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB                        0
1361 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK                       0xffffffff
1362 
1363 /* Description		RX_REO_QUEUE_19_RX_BITMAP_191_160
1364 
1365 			See Rx_bitmap_31_0 description
1366 
1367 			<legal all>
1368 */
1369 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET                     0x0000004c
1370 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB                        0
1371 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK                       0xffffffff
1372 
1373 /* Description		RX_REO_QUEUE_20_RX_BITMAP_223_192
1374 
1375 			See Rx_bitmap_31_0 description
1376 
1377 			<legal all>
1378 */
1379 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET                     0x00000050
1380 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB                        0
1381 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK                       0xffffffff
1382 
1383 /* Description		RX_REO_QUEUE_21_RX_BITMAP_255_224
1384 
1385 			See Rx_bitmap_31_0 description
1386 
1387 			<legal all>
1388 */
1389 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET                     0x00000054
1390 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB                        0
1391 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK                       0xffffffff
1392 
1393 /* Description		RX_REO_QUEUE_22_CURRENT_MPDU_COUNT
1394 
1395 			The number of MPDUs in the queue.
1396 
1397 
1398 
1399 			<legal all>
1400 */
1401 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET                    0x00000058
1402 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB                       0
1403 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK                      0x0000007f
1404 
1405 /* Description		RX_REO_QUEUE_22_CURRENT_MSDU_COUNT
1406 
1407 			The number of MSDUs in the queue.
1408 
1409 			<legal all>
1410 */
1411 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET                    0x00000058
1412 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB                       7
1413 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK                      0xffffff80
1414 
1415 /* Description		RX_REO_QUEUE_23_RESERVED_23
1416 
1417 			<legal 0>
1418 */
1419 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET                           0x0000005c
1420 #define RX_REO_QUEUE_23_RESERVED_23_LSB                              0
1421 #define RX_REO_QUEUE_23_RESERVED_23_MASK                             0x0000000f
1422 
1423 /* Description		RX_REO_QUEUE_23_TIMEOUT_COUNT
1424 
1425 			The number of times that REO started forwarding frames
1426 			even though there is a hole in the bitmap. Forwarding reason
1427 			is Timeout
1428 
1429 
1430 
1431 			The counter saturates and freezes at 0x3F
1432 
1433 
1434 
1435 			<legal all>
1436 */
1437 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET                         0x0000005c
1438 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB                            4
1439 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK                           0x000003f0
1440 
1441 /* Description		RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT
1442 
1443 			The number of times that REO started forwarding frames
1444 			even though there is a hole in the bitmap. Forwarding reason
1445 			is reception of BAR frame.
1446 
1447 
1448 
1449 			The counter saturates and freezes at 0x3F
1450 
1451 
1452 
1453 			<legal all>
1454 */
1455 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET              0x0000005c
1456 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB                 10
1457 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK                0x0000fc00
1458 
1459 /* Description		RX_REO_QUEUE_23_DUPLICATE_COUNT
1460 
1461 			The number of duplicate frames that have been detected
1462 
1463 			<legal all>
1464 */
1465 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET                       0x0000005c
1466 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB                          16
1467 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK                         0xffff0000
1468 
1469 /* Description		RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT
1470 
1471 			The number of frames that have been received in order
1472 			(without a hole that prevented them from being forwarded
1473 			immediately)
1474 
1475 
1476 
1477 			This corresponds to the Reorder opcodes:
1478 
1479 			'FWDCUR' and 'FWD BUF'
1480 
1481 
1482 
1483 			<legal all>
1484 */
1485 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET                 0x00000060
1486 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB                    0
1487 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK                   0x00ffffff
1488 
1489 /* Description		RX_REO_QUEUE_24_BAR_RECEIVED_COUNT
1490 
1491 			The number of times a BAR frame is received.
1492 
1493 
1494 
1495 			This corresponds to the Reorder opcodes with 'DROP'
1496 
1497 
1498 
1499 			The counter saturates and freezes at 0xFF
1500 
1501 			<legal all>
1502 */
1503 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET                    0x00000060
1504 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB                       24
1505 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK                      0xff000000
1506 
1507 /* Description		RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT
1508 
1509 			The total number of MPDU frames that have been processed
1510 			by REO. 'Processing' here means that REO has received them
1511 			out of the entrance ring, and retrieved the corresponding
1512 			RX_REO_QUEUE Descriptor.
1513 
1514 
1515 
1516 			Note that this count includes duplicates, frames that
1517 			later had errors, etc.
1518 
1519 
1520 
1521 			Note that field 'Duplicate_count' indicates how many of
1522 			these MPDUs were duplicates.
1523 
1524 
1525 
1526 			<legal all>
1527 */
1528 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000064
1529 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB              0
1530 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
1531 
1532 /* Description		RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT
1533 
1534 			The total number of MSDU frames that have been processed
1535 			by REO. 'Processing' here means that REO has received them
1536 			out of the entrance ring, and retrieved the corresponding
1537 			RX_REO_QUEUE Descriptor.
1538 
1539 
1540 
1541 			Note that this count includes duplicates, frames that
1542 			later had errors, etc.
1543 
1544 
1545 
1546 			<legal all>
1547 */
1548 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000068
1549 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB              0
1550 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
1551 
1552 /* Description		RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT
1553 
1554 			An approximation of the number of bytes processed for
1555 			this queue.
1556 
1557 			'Processing' here means that REO has received them out
1558 			of the entrance ring, and retrieved the corresponding
1559 			RX_REO_QUEUE Descriptor.
1560 
1561 
1562 
1563 			Note that this count includes duplicates, frames that
1564 			later had errors, etc.
1565 
1566 
1567 
1568 			In 64 byte units
1569 
1570 			<legal all>
1571 */
1572 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET            0x0000006c
1573 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB               0
1574 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK              0xffffffff
1575 
1576 /* Description		RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT
1577 
1578 			The number of MPDUs received after the window had
1579 			already moved on. The 'late' sequence window is defined as
1580 			(Window SSN - 256) - (Window SSN - 1)
1581 
1582 
1583 
1584 			This corresponds with Out of order detection in
1585 			duplicate detect FSM
1586 
1587 
1588 
1589 			The counter saturates and freezes at 0xFFF
1590 
1591 
1592 
1593 			<legal all>
1594 */
1595 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET               0x00000070
1596 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB                  0
1597 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK                 0x00000fff
1598 
1599 /* Description		RX_REO_QUEUE_28_WINDOW_JUMP_2K
1600 
1601 			The number of times the window moved more then 2K
1602 
1603 
1604 
1605 			The counter saturates and freezes at 0xF
1606 
1607 
1608 
1609 			(Note: field name can not start with number: previous
1610 			2k_window_jump)
1611 
1612 
1613 
1614 			<legal all>
1615 */
1616 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET                        0x00000070
1617 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB                           12
1618 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK                          0x0000f000
1619 
1620 /* Description		RX_REO_QUEUE_28_HOLE_COUNT
1621 
1622 			The number of times a hole was created in the receive
1623 			bitmap.
1624 
1625 
1626 
1627 			This corresponds to the Reorder opcodes with 'QCUR'
1628 
1629 
1630 
1631 			<legal all>
1632 */
1633 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET                            0x00000070
1634 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB                               16
1635 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK                              0xffff0000
1636 
1637 /* Description		RX_REO_QUEUE_29_RESERVED_29
1638 
1639 			<legal 0>
1640 */
1641 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET                           0x00000074
1642 #define RX_REO_QUEUE_29_RESERVED_29_LSB                              0
1643 #define RX_REO_QUEUE_29_RESERVED_29_MASK                             0xffffffff
1644 
1645 /* Description		RX_REO_QUEUE_30_RESERVED_30
1646 
1647 			<legal 0>
1648 */
1649 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET                           0x00000078
1650 #define RX_REO_QUEUE_30_RESERVED_30_LSB                              0
1651 #define RX_REO_QUEUE_30_RESERVED_30_MASK                             0xffffffff
1652 
1653 /* Description		RX_REO_QUEUE_31_RESERVED_31
1654 
1655 			<legal 0>
1656 */
1657 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET                           0x0000007c
1658 #define RX_REO_QUEUE_31_RESERVED_31_LSB                              0
1659 #define RX_REO_QUEUE_31_RESERVED_31_MASK                             0xffffffff
1660 
1661 
1662 #endif // _RX_REO_QUEUE_H_
1663