1 /* 2 * Copyright (c) 2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _RX_MPDU_INFO_H_ 26 #define _RX_MPDU_INFO_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 #include "rxpt_classify_info.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 36 // 1 ast_index[15:0], sw_peer_id[31:16] 37 // 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 38 // 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16] 39 // 4 pn_31_0[31:0] 40 // 5 pn_63_32[31:0] 41 // 6 pn_95_64[31:0] 42 // 7 pn_127_96[31:0] 43 // 8 peer_meta_data[31:0] 44 // 9 struct rxpt_classify_info rxpt_classify_info_details; 45 // 10 rx_reo_queue_desc_addr_31_0[31:0] 46 // 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 47 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] 48 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30] 49 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 50 // 15 mac_addr_ad1_31_0[31:0] 51 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 52 // 17 mac_addr_ad2_47_16[31:0] 53 // 18 mac_addr_ad3_31_0[31:0] 54 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 55 // 20 mac_addr_ad4_31_0[31:0] 56 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 57 // 22 mpdu_ht_control_field[31:0] 58 // 59 // ################ END SUMMARY ################# 60 61 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 62 63 struct rx_mpdu_info { 64 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 65 sw_frame_group_id : 7, //[8:2] 66 ndp_frame : 1, //[9] 67 phy_err : 1, //[10] 68 phy_err_during_mpdu_header : 1, //[11] 69 protocol_version_err : 1, //[12] 70 ast_based_lookup_valid : 1, //[13] 71 reserved_0a : 2, //[15:14] 72 phy_ppdu_id : 16; //[31:16] 73 uint32_t ast_index : 16, //[15:0] 74 sw_peer_id : 16; //[31:16] 75 uint32_t mpdu_frame_control_valid : 1, //[0] 76 mpdu_duration_valid : 1, //[1] 77 mac_addr_ad1_valid : 1, //[2] 78 mac_addr_ad2_valid : 1, //[3] 79 mac_addr_ad3_valid : 1, //[4] 80 mac_addr_ad4_valid : 1, //[5] 81 mpdu_sequence_control_valid : 1, //[6] 82 mpdu_qos_control_valid : 1, //[7] 83 mpdu_ht_control_valid : 1, //[8] 84 frame_encryption_info_valid : 1, //[9] 85 reserved_2a : 6, //[15:10] 86 fr_ds : 1, //[16] 87 to_ds : 1, //[17] 88 encrypted : 1, //[18] 89 mpdu_retry : 1, //[19] 90 mpdu_sequence_number : 12; //[31:20] 91 uint32_t epd_en : 1, //[0] 92 all_frames_shall_be_encrypted : 1, //[1] 93 encrypt_type : 4, //[5:2] 94 mesh_sta : 1, //[6] 95 bssid_hit : 1, //[7] 96 bssid_number : 4, //[11:8] 97 tid : 4, //[15:12] 98 reserved_3a : 16; //[31:16] 99 uint32_t pn_31_0 : 32; //[31:0] 100 uint32_t pn_63_32 : 32; //[31:0] 101 uint32_t pn_95_64 : 32; //[31:0] 102 uint32_t pn_127_96 : 32; //[31:0] 103 uint32_t peer_meta_data : 32; //[31:0] 104 struct rxpt_classify_info rxpt_classify_info_details; 105 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 106 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 107 receive_queue_number : 16, //[23:8] 108 pre_delim_err_warning : 1, //[24] 109 first_delim_err : 1, //[25] 110 reserved_11 : 6; //[31:26] 111 uint32_t key_id_octet : 8, //[7:0] 112 new_peer_entry : 1, //[8] 113 decrypt_needed : 1, //[9] 114 decap_type : 2, //[11:10] 115 rx_insert_vlan_c_tag_padding : 1, //[12] 116 rx_insert_vlan_s_tag_padding : 1, //[13] 117 strip_vlan_c_tag_decap : 1, //[14] 118 strip_vlan_s_tag_decap : 1, //[15] 119 pre_delim_count : 12, //[27:16] 120 ampdu_flag : 1, //[28] 121 bar_frame : 1, //[29] 122 reserved_12 : 2; //[31:30] 123 uint32_t mpdu_length : 14, //[13:0] 124 first_mpdu : 1, //[14] 125 mcast_bcast : 1, //[15] 126 ast_index_not_found : 1, //[16] 127 ast_index_timeout : 1, //[17] 128 power_mgmt : 1, //[18] 129 non_qos : 1, //[19] 130 null_data : 1, //[20] 131 mgmt_type : 1, //[21] 132 ctrl_type : 1, //[22] 133 more_data : 1, //[23] 134 eosp : 1, //[24] 135 fragment_flag : 1, //[25] 136 order : 1, //[26] 137 u_apsd_trigger : 1, //[27] 138 encrypt_required : 1, //[28] 139 directed : 1, //[29] 140 reserved_13 : 2; //[31:30] 141 uint32_t mpdu_frame_control_field : 16, //[15:0] 142 mpdu_duration_field : 16; //[31:16] 143 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 144 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 145 mac_addr_ad2_15_0 : 16; //[31:16] 146 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 147 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 148 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 149 mpdu_sequence_control_field : 16; //[31:16] 150 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 151 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 152 mpdu_qos_control_field : 16; //[31:16] 153 uint32_t mpdu_ht_control_field : 32; //[31:0] 154 }; 155 156 /* 157 158 rxpcu_mpdu_filter_in_category 159 160 Field indicates what the reason was that this MPDU frame 161 was allowed to come into the receive path by RXPCU 162 163 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 164 frame filter programming of rxpcu 165 166 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 167 regular frame filter and would have been dropped, were it 168 not for the frame fitting into the 'monitor_client' 169 category. 170 171 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 172 regular frame filter and also did not pass the 173 rxpcu_monitor_client filter. It would have been dropped 174 accept that it did pass the 'monitor_other' category. 175 176 177 178 Note: for ndp frame, if it was expected because the 179 preceding NDPA was filter_pass, the setting 180 rxpcu_filter_pass will be used. This setting will also be 181 used for every ndp frame in case Promiscuous mode is 182 enabled. 183 184 185 186 In case promiscuous is not enabled, and an NDP is not 187 preceded by a NPDA filter pass frame, the only other setting 188 that could appear here for the NDP is rxpcu_monitor_other. 189 190 (rxpcu has a configuration bit specifically for this 191 scenario) 192 193 194 195 Note: for 196 197 <legal 0-2> 198 199 sw_frame_group_id 200 201 SW processes frames based on certain classifications. 202 This field indicates to what sw classification this MPDU is 203 mapped. 204 205 The classification is given in priority order 206 207 208 209 <enum 0 sw_frame_group_NDP_frame> Note: The 210 corresponding Rxpcu_Mpdu_filter_in_category can be 211 rxpcu_filter_pass or rxpcu_monitor_other 212 213 214 215 <enum 1 sw_frame_group_Multicast_data> 216 217 <enum 2 sw_frame_group_Unicast_data> 218 219 <enum 3 sw_frame_group_Null_data > This includes mpdus 220 of type Data Null as well as QoS Data Null 221 222 223 224 <enum 4 sw_frame_group_mgmt_0000 > 225 226 <enum 5 sw_frame_group_mgmt_0001 > 227 228 <enum 6 sw_frame_group_mgmt_0010 > 229 230 <enum 7 sw_frame_group_mgmt_0011 > 231 232 <enum 8 sw_frame_group_mgmt_0100 > 233 234 <enum 9 sw_frame_group_mgmt_0101 > 235 236 <enum 10 sw_frame_group_mgmt_0110 > 237 238 <enum 11 sw_frame_group_mgmt_0111 > 239 240 <enum 12 sw_frame_group_mgmt_1000 > 241 242 <enum 13 sw_frame_group_mgmt_1001 > 243 244 <enum 14 sw_frame_group_mgmt_1010 > 245 246 <enum 15 sw_frame_group_mgmt_1011 > 247 248 <enum 16 sw_frame_group_mgmt_1100 > 249 250 <enum 17 sw_frame_group_mgmt_1101 > 251 252 <enum 18 sw_frame_group_mgmt_1110 > 253 254 <enum 19 sw_frame_group_mgmt_1111 > 255 256 257 258 <enum 20 sw_frame_group_ctrl_0000 > 259 260 <enum 21 sw_frame_group_ctrl_0001 > 261 262 <enum 22 sw_frame_group_ctrl_0010 > 263 264 <enum 23 sw_frame_group_ctrl_0011 > 265 266 <enum 24 sw_frame_group_ctrl_0100 > 267 268 <enum 25 sw_frame_group_ctrl_0101 > 269 270 <enum 26 sw_frame_group_ctrl_0110 > 271 272 <enum 27 sw_frame_group_ctrl_0111 > 273 274 <enum 28 sw_frame_group_ctrl_1000 > 275 276 <enum 29 sw_frame_group_ctrl_1001 > 277 278 <enum 30 sw_frame_group_ctrl_1010 > 279 280 <enum 31 sw_frame_group_ctrl_1011 > 281 282 <enum 32 sw_frame_group_ctrl_1100 > 283 284 <enum 33 sw_frame_group_ctrl_1101 > 285 286 <enum 34 sw_frame_group_ctrl_1110 > 287 288 <enum 35 sw_frame_group_ctrl_1111 > 289 290 291 292 <enum 36 sw_frame_group_unsupported> This covers type 3 293 and protocol version != 0 294 295 Note: The corresponding Rxpcu_Mpdu_filter_in_category 296 can only be rxpcu_monitor_other 297 298 299 300 301 Note: The corresponding Rxpcu_Mpdu_filter_in_category 302 can be rxpcu_filter_pass 303 304 305 306 <legal 0-37> 307 308 ndp_frame 309 310 When set, the received frame was an NDP frame, and thus 311 there will be no MPDU data. 312 313 <legal all> 314 315 phy_err 316 317 When set, a PHY error was received before MAC received 318 any data, and thus there will be no MPDU data. 319 320 <legal all> 321 322 phy_err_during_mpdu_header 323 324 When set, a PHY error was received before MAC received 325 the complete MPDU header which was needed for proper 326 decoding 327 328 <legal all> 329 330 protocol_version_err 331 332 Set when RXPCU detected a version error in the Frame 333 control field 334 335 <legal all> 336 337 ast_based_lookup_valid 338 339 When set, AST based lookup for this frame has found a 340 valid result. 341 342 343 344 Note that for NDP frame this will never be set 345 346 <legal all> 347 348 reserved_0a 349 350 <legal 0> 351 352 phy_ppdu_id 353 354 A ppdu counter value that PHY increments for every PPDU 355 received. The counter value wraps around 356 357 <legal all> 358 359 ast_index 360 361 This field indicates the index of the AST entry 362 corresponding to this MPDU. It is provided by the GSE module 363 instantiated in RXPCU. 364 365 A value of 0xFFFF indicates an invalid AST index, 366 meaning that No AST entry was found or NO AST search was 367 performed 368 369 370 371 In case of ndp or phy_err, this field will be set to 372 0xFFFF 373 374 <legal all> 375 376 sw_peer_id 377 378 In case of ndp or phy_err or AST_based_lookup_valid == 379 0, this field will be set to 0 380 381 382 383 This field indicates a unique peer identifier. It is set 384 equal to field 'sw_peer_id' from the AST entry 385 386 387 388 <legal all> 389 390 mpdu_frame_control_valid 391 392 When set, the field Mpdu_Frame_control_field has valid 393 information 394 395 396 397 398 <legal all> 399 400 mpdu_duration_valid 401 402 When set, the field Mpdu_duration_field has valid 403 information 404 405 406 407 408 <legal all> 409 410 mac_addr_ad1_valid 411 412 When set, the fields mac_addr_ad1_..... have valid 413 information 414 415 416 417 418 <legal all> 419 420 mac_addr_ad2_valid 421 422 When set, the fields mac_addr_ad2_..... have valid 423 information 424 425 426 427 428 429 430 431 <legal all> 432 433 mac_addr_ad3_valid 434 435 When set, the fields mac_addr_ad3_..... have valid 436 information 437 438 439 440 441 442 443 444 <legal all> 445 446 mac_addr_ad4_valid 447 448 When set, the fields mac_addr_ad4_..... have valid 449 information 450 451 452 453 454 455 456 457 <legal all> 458 459 mpdu_sequence_control_valid 460 461 When set, the fields mpdu_sequence_control_field and 462 mpdu_sequence_number have valid information as well as field 463 464 465 466 For MPDUs without a sequence control field, this field 467 will not be set. 468 469 470 471 472 <legal all> 473 474 mpdu_qos_control_valid 475 476 When set, the field mpdu_qos_control_field has valid 477 information 478 479 480 481 For MPDUs without a QoS control field, this field will 482 not be set. 483 484 485 486 487 <legal all> 488 489 mpdu_ht_control_valid 490 491 When set, the field mpdu_HT_control_field has valid 492 information 493 494 495 496 For MPDUs without a HT control field, this field will 497 not be set. 498 499 500 501 502 <legal all> 503 504 frame_encryption_info_valid 505 506 When set, the encryption related info fields, like IV 507 and PN are valid 508 509 510 511 For MPDUs that are not encrypted, this will not be set. 512 513 514 515 516 <legal all> 517 518 reserved_2a 519 520 <legal 0> 521 522 fr_ds 523 524 Field only valid when Mpdu_frame_control_valid is set 525 526 527 528 Set if the from DS bit is set in the frame control. 529 530 <legal all> 531 532 to_ds 533 534 Field only valid when Mpdu_frame_control_valid is set 535 536 537 538 Set if the to DS bit is set in the frame control. 539 540 <legal all> 541 542 encrypted 543 544 Field only valid when Mpdu_frame_control_valid is set. 545 546 547 548 Protected bit from the frame control. 549 550 <legal all> 551 552 mpdu_retry 553 554 Field only valid when Mpdu_frame_control_valid is set. 555 556 557 558 Retry bit from the frame control. Only valid when 559 first_msdu is set. 560 561 <legal all> 562 563 mpdu_sequence_number 564 565 Field only valid when Mpdu_sequence_control_valid is 566 set. 567 568 569 570 The sequence number from the 802.11 header. 571 572 <legal all> 573 574 epd_en 575 576 Field only valid when AST_based_lookup_valid == 1. 577 578 579 580 581 582 In case of ndp or phy_err or AST_based_lookup_valid == 583 0, this field will be set to 0 584 585 586 587 If set to one use EPD instead of LPD 588 589 590 591 592 <legal all> 593 594 all_frames_shall_be_encrypted 595 596 In case of ndp or phy_err or AST_based_lookup_valid == 597 0, this field will be set to 0 598 599 600 601 When set, all frames (data only ?) shall be encrypted. 602 If not, RX CRYPTO shall set an error flag. 603 604 <legal all> 605 606 encrypt_type 607 608 In case of ndp or phy_err or AST_based_lookup_valid == 609 0, this field will be set to 0 610 611 612 613 Indicates type of decrypt cipher used (as defined in the 614 peer entry) 615 616 617 618 <enum 0 wep_40> WEP 40-bit 619 620 <enum 1 wep_104> WEP 104-bit 621 622 <enum 2 tkip_no_mic> TKIP without MIC 623 624 <enum 3 wep_128> WEP 128-bit 625 626 <enum 4 tkip_with_mic> TKIP with MIC 627 628 <enum 5 wapi> WAPI 629 630 <enum 6 aes_ccmp_128> AES CCMP 128 631 632 <enum 7 no_cipher> No crypto 633 634 <enum 8 aes_ccmp_256> AES CCMP 256 635 636 <enum 9 aes_gcmp_128> AES CCMP 128 637 638 <enum 10 aes_gcmp_256> AES CCMP 256 639 640 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 641 642 643 644 645 <legal 0-11> 646 647 mesh_sta 648 649 In case of ndp or phy_err or AST_based_lookup_valid == 650 0, this field will be set to 0 651 652 653 654 When set, this is a Mesh (11s) STA 655 656 <legal all> 657 658 bssid_hit 659 660 In case of ndp or phy_err or AST_based_lookup_valid == 661 0, this field will be set to 0 662 663 664 665 When set, the BSSID of the incoming frame matched one of 666 the 8 BSSID register values 667 668 669 670 <legal all> 671 672 bssid_number 673 674 Field only valid when bssid_hit is set. 675 676 677 678 This number indicates which one out of the 8 BSSID 679 register values matched the incoming frame 680 681 <legal all> 682 683 tid 684 685 Field only valid when mpdu_qos_control_valid is set 686 687 688 689 The TID field in the QoS control field 690 691 <legal all> 692 693 reserved_3a 694 695 <legal 0> 696 697 pn_31_0 698 699 700 701 702 703 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 704 is valid. 705 706 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 707 WEPSeed[1], pn1}. Only pn[47:0] is valid. 708 709 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 710 pn1, pn0}. Only pn[47:0] is valid. 711 712 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 713 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 714 pn0}. pn[127:0] are valid. 715 716 717 718 719 pn_63_32 720 721 722 723 724 Bits [63:32] of the PN number. See description for 725 pn_31_0. 726 727 728 729 730 pn_95_64 731 732 733 734 735 Bits [95:64] of the PN number. See description for 736 pn_31_0. 737 738 739 740 741 pn_127_96 742 743 744 745 746 Bits [127:96] of the PN number. See description for 747 pn_31_0. 748 749 750 751 752 peer_meta_data 753 754 In case of ndp or phy_err or AST_based_lookup_valid == 755 0, this field will be set to 0 756 757 758 759 Meta data that SW has programmed in the Peer table entry 760 of the transmitting STA. 761 762 <legal all> 763 764 struct rxpt_classify_info rxpt_classify_info_details 765 766 In case of ndp or phy_err or AST_based_lookup_valid == 767 0, this field will be set to 0 768 769 770 771 RXOLE related classification info 772 773 <legal all 774 775 rx_reo_queue_desc_addr_31_0 776 777 In case of ndp or phy_err or AST_based_lookup_valid == 778 0, this field will be set to 0 779 780 781 782 Address (lower 32 bits) of the REO queue descriptor. 783 784 785 786 If no Peer entry lookup happened for this frame, the 787 value wil be set to 0, and the frame shall never be pushed 788 to REO entrance ring. 789 790 <legal all> 791 792 rx_reo_queue_desc_addr_39_32 793 794 In case of ndp or phy_err or AST_based_lookup_valid == 795 0, this field will be set to 0 796 797 798 799 Address (upper 8 bits) of the REO queue descriptor. 800 801 802 803 If no Peer entry lookup happened for this frame, the 804 value wil be set to 0, and the frame shall never be pushed 805 to REO entrance ring. 806 807 <legal all> 808 809 receive_queue_number 810 811 In case of ndp or phy_err or AST_based_lookup_valid == 812 0, this field will be set to 0 813 814 815 816 Indicates the MPDU queue ID to which this MPDU link 817 descriptor belongs 818 819 Used for tracking and debugging 820 821 <legal all> 822 823 pre_delim_err_warning 824 825 Indicates that a delimiter FCS error was found in 826 between the Previous MPDU and this MPDU. 827 828 829 830 Note that this is just a warning, and does not mean that 831 this MPDU is corrupted in any way. If it is, there will be 832 other errors indicated such as FCS or decrypt errors 833 834 835 836 837 first_delim_err 838 839 Indicates that the first delimiter had a FCS failure. 840 Only valid when first_mpdu and first_msdu are set. 841 842 843 844 845 reserved_11 846 847 <legal 0> 848 849 key_id_octet 850 851 852 853 854 The key ID octet from the IV. 855 856 857 858 In case of ndp or phy_err or AST_based_lookup_valid == 859 0, this field will be set to 0 860 861 <legal all> 862 863 new_peer_entry 864 865 In case of ndp or phy_err or AST_based_lookup_valid == 866 0, this field will be set to 0 867 868 869 870 Set if new RX_PEER_ENTRY TLV follows. If clear, 871 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 872 uses old peer entry or not decrypt. 873 874 <legal all> 875 876 decrypt_needed 877 878 In case of ndp or phy_err or AST_based_lookup_valid == 879 0, this field will be set to 0 880 881 882 883 Set if decryption is needed. 884 885 886 887 Note: 888 889 When RXPCU sets bit 'ast_index_not_found' and/or 890 ast_index_timeout', RXPCU will also ensure that this bit is 891 NOT set 892 893 CRYPTO for that reason only needs to evaluate this bit 894 and non of the other ones. 895 896 <legal all> 897 898 decap_type 899 900 In case of ndp or phy_err or AST_based_lookup_valid == 901 0, this field will be set to 0 902 903 904 905 Used by the OLE during decapsulation. 906 907 908 909 Indicates the decapsulation that HW will perform: 910 911 912 913 <enum 0 PTE_DECAP_RAW> No encapsulation 914 915 <enum 1 PTE_DECAP_Native_WiFi> 916 917 <enum 2 PTE_DECAP_Ethernet_802_3> Ethernet 2 (DIX) or 918 802.3 (uses SNAP/LLC) 919 920 <legal 0-2> 921 922 rx_insert_vlan_c_tag_padding 923 924 In case of ndp or phy_err or AST_based_lookup_valid == 925 0, this field will be set to 0 926 927 928 929 Insert 4 byte of all zeros as VLAN tag if the rx payload 930 does not have VLAN. Used during decapsulation. 931 932 <legal all> 933 934 rx_insert_vlan_s_tag_padding 935 936 In case of ndp or phy_err or AST_based_lookup_valid == 937 0, this field will be set to 0 938 939 940 941 Insert 4 byte of all zeros as double VLAN tag if the rx 942 payload does not have VLAN. Used during 943 944 <legal all> 945 946 strip_vlan_c_tag_decap 947 948 In case of ndp or phy_err or AST_based_lookup_valid == 949 0, this field will be set to 0 950 951 952 953 Strip the VLAN during decapsulation. Used by the OLE. 954 955 <legal all> 956 957 strip_vlan_s_tag_decap 958 959 In case of ndp or phy_err or AST_based_lookup_valid == 960 0, this field will be set to 0 961 962 963 964 Strip the double VLAN during decapsulation. Used by 965 the OLE. 966 967 <legal all> 968 969 pre_delim_count 970 971 The number of delimiters before this MPDU. 972 973 974 975 In case of ndp or phy_err, this field will be set to 0 976 977 ampdu_flag 978 979 When set, received frame was part of an A-MPDU. 980 981 982 983 984 <legal all> 985 986 bar_frame 987 988 In case of ndp or phy_err or AST_based_lookup_valid == 989 0, this field will be set to 0 990 991 992 993 When set, received frame is a BAR frame 994 995 <legal all> 996 997 reserved_12 998 999 <legal 0>. 1000 1001 mpdu_length 1002 1003 In case of ndp or phy_err this field will be set to 0 1004 1005 1006 1007 MPDU length before decapsulation. 1008 1009 <legal all> 1010 1011 first_mpdu 1012 1013 See definition in RX attention descriptor 1014 1015 1016 1017 In case of ndp or phy_err, this field will be set. Note 1018 however that there will not actually be any data contents in 1019 the MPDU. 1020 1021 <legal all> 1022 1023 mcast_bcast 1024 1025 In case of ndp or phy_err or Phy_err_during_mpdu_header 1026 this field will be set to 0 1027 1028 1029 1030 See definition in RX attention descriptor 1031 1032 <legal all> 1033 1034 ast_index_not_found 1035 1036 In case of ndp or phy_err or Phy_err_during_mpdu_header 1037 this field will be set to 0 1038 1039 1040 1041 See definition in RX attention descriptor 1042 1043 <legal all> 1044 1045 ast_index_timeout 1046 1047 In case of ndp or phy_err or Phy_err_during_mpdu_header 1048 this field will be set to 0 1049 1050 1051 1052 See definition in RX attention descriptor 1053 1054 <legal all> 1055 1056 power_mgmt 1057 1058 In case of ndp or phy_err or Phy_err_during_mpdu_header 1059 this field will be set to 0 1060 1061 1062 1063 See definition in RX attention descriptor 1064 1065 <legal all> 1066 1067 non_qos 1068 1069 In case of ndp or phy_err or Phy_err_during_mpdu_header 1070 this field will be set to 1 1071 1072 1073 1074 See definition in RX attention descriptor 1075 1076 <legal all> 1077 1078 null_data 1079 1080 In case of ndp or phy_err or Phy_err_during_mpdu_header 1081 this field will be set to 0 1082 1083 1084 1085 See definition in RX attention descriptor 1086 1087 <legal all> 1088 1089 mgmt_type 1090 1091 In case of ndp or phy_err or Phy_err_during_mpdu_header 1092 this field will be set to 0 1093 1094 1095 1096 See definition in RX attention descriptor 1097 1098 <legal all> 1099 1100 ctrl_type 1101 1102 In case of ndp or phy_err or Phy_err_during_mpdu_header 1103 this field will be set to 0 1104 1105 1106 1107 See definition in RX attention descriptor 1108 1109 <legal all> 1110 1111 more_data 1112 1113 In case of ndp or phy_err or Phy_err_during_mpdu_header 1114 this field will be set to 0 1115 1116 1117 1118 See definition in RX attention descriptor 1119 1120 <legal all> 1121 1122 eosp 1123 1124 In case of ndp or phy_err or Phy_err_during_mpdu_header 1125 this field will be set to 0 1126 1127 1128 1129 See definition in RX attention descriptor 1130 1131 <legal all> 1132 1133 fragment_flag 1134 1135 In case of ndp or phy_err or Phy_err_during_mpdu_header 1136 this field will be set to 0 1137 1138 1139 1140 See definition in RX attention descriptor 1141 1142 <legal all> 1143 1144 order 1145 1146 In case of ndp or phy_err or Phy_err_during_mpdu_header 1147 this field will be set to 0 1148 1149 1150 1151 See definition in RX attention descriptor 1152 1153 1154 1155 <legal all> 1156 1157 u_apsd_trigger 1158 1159 In case of ndp or phy_err or Phy_err_during_mpdu_header 1160 this field will be set to 0 1161 1162 1163 1164 See definition in RX attention descriptor 1165 1166 <legal all> 1167 1168 encrypt_required 1169 1170 In case of ndp or phy_err or Phy_err_during_mpdu_header 1171 this field will be set to 0 1172 1173 1174 1175 See definition in RX attention descriptor 1176 1177 <legal all> 1178 1179 directed 1180 1181 In case of ndp or phy_err or Phy_err_during_mpdu_header 1182 this field will be set to 0 1183 1184 1185 1186 See definition in RX attention descriptor 1187 1188 <legal all> 1189 1190 reserved_13 1191 1192 <legal 0> 1193 1194 mpdu_frame_control_field 1195 1196 Field only valid when Mpdu_frame_control_valid is set 1197 1198 1199 1200 The frame control field of this received MPDU. 1201 1202 1203 1204 Field only valid when Ndp_frame and phy_err are NOT set 1205 1206 1207 1208 Bytes 0 + 1 of the received MPDU 1209 1210 <legal all> 1211 1212 mpdu_duration_field 1213 1214 Field only valid when Mpdu_duration_valid is set 1215 1216 1217 1218 The duration field of this received MPDU. 1219 1220 <legal all> 1221 1222 mac_addr_ad1_31_0 1223 1224 Field only valid when mac_addr_ad1_valid is set 1225 1226 1227 1228 The Least Significant 4 bytes of the Received Frames MAC 1229 Address AD1 1230 1231 <legal all> 1232 1233 mac_addr_ad1_47_32 1234 1235 Field only valid when mac_addr_ad1_valid is set 1236 1237 1238 1239 The 2 most significant bytes of the Received Frames MAC 1240 Address AD1 1241 1242 <legal all> 1243 1244 mac_addr_ad2_15_0 1245 1246 Field only valid when mac_addr_ad2_valid is set 1247 1248 1249 1250 The Least Significant 2 bytes of the Received Frames MAC 1251 Address AD2 1252 1253 <legal all> 1254 1255 mac_addr_ad2_47_16 1256 1257 Field only valid when mac_addr_ad2_valid is set 1258 1259 1260 1261 The 4 most significant bytes of the Received Frames MAC 1262 Address AD2 1263 1264 <legal all> 1265 1266 mac_addr_ad3_31_0 1267 1268 Field only valid when mac_addr_ad3_valid is set 1269 1270 1271 1272 The Least Significant 4 bytes of the Received Frames MAC 1273 Address AD3 1274 1275 <legal all> 1276 1277 mac_addr_ad3_47_32 1278 1279 Field only valid when mac_addr_ad3_valid is set 1280 1281 1282 1283 The 2 most significant bytes of the Received Frames MAC 1284 Address AD3 1285 1286 <legal all> 1287 1288 mpdu_sequence_control_field 1289 1290 1291 1292 1293 The sequence control field of the MPDU 1294 1295 <legal all> 1296 1297 mac_addr_ad4_31_0 1298 1299 Field only valid when mac_addr_ad4_valid is set 1300 1301 1302 1303 The Least Significant 4 bytes of the Received Frames MAC 1304 Address AD4 1305 1306 <legal all> 1307 1308 mac_addr_ad4_47_32 1309 1310 Field only valid when mac_addr_ad4_valid is set 1311 1312 1313 1314 The 2 most significant bytes of the Received Frames MAC 1315 Address AD4 1316 1317 <legal all> 1318 1319 mpdu_qos_control_field 1320 1321 Field only valid when mpdu_qos_control_valid is set 1322 1323 1324 1325 The sequence control field of the MPDU 1326 1327 <legal all> 1328 1329 mpdu_ht_control_field 1330 1331 Field only valid when mpdu_qos_control_valid is set 1332 1333 1334 1335 The HT control field of the MPDU 1336 1337 <legal all> 1338 */ 1339 1340 1341 /* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY 1342 1343 Field indicates what the reason was that this MPDU frame 1344 was allowed to come into the receive path by RXPCU 1345 1346 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 1347 frame filter programming of rxpcu 1348 1349 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 1350 regular frame filter and would have been dropped, were it 1351 not for the frame fitting into the 'monitor_client' 1352 category. 1353 1354 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 1355 regular frame filter and also did not pass the 1356 rxpcu_monitor_client filter. It would have been dropped 1357 accept that it did pass the 'monitor_other' category. 1358 1359 1360 1361 Note: for ndp frame, if it was expected because the 1362 preceding NDPA was filter_pass, the setting 1363 rxpcu_filter_pass will be used. This setting will also be 1364 used for every ndp frame in case Promiscuous mode is 1365 enabled. 1366 1367 1368 1369 In case promiscuous is not enabled, and an NDP is not 1370 preceded by a NPDA filter pass frame, the only other setting 1371 that could appear here for the NDP is rxpcu_monitor_other. 1372 1373 (rxpcu has a configuration bit specifically for this 1374 scenario) 1375 1376 1377 1378 Note: for 1379 1380 <legal 0-2> 1381 */ 1382 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 1383 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1384 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1385 1386 /* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID 1387 1388 SW processes frames based on certain classifications. 1389 This field indicates to what sw classification this MPDU is 1390 mapped. 1391 1392 The classification is given in priority order 1393 1394 1395 1396 <enum 0 sw_frame_group_NDP_frame> Note: The 1397 corresponding Rxpcu_Mpdu_filter_in_category can be 1398 rxpcu_filter_pass or rxpcu_monitor_other 1399 1400 1401 1402 <enum 1 sw_frame_group_Multicast_data> 1403 1404 <enum 2 sw_frame_group_Unicast_data> 1405 1406 <enum 3 sw_frame_group_Null_data > This includes mpdus 1407 of type Data Null as well as QoS Data Null 1408 1409 1410 1411 <enum 4 sw_frame_group_mgmt_0000 > 1412 1413 <enum 5 sw_frame_group_mgmt_0001 > 1414 1415 <enum 6 sw_frame_group_mgmt_0010 > 1416 1417 <enum 7 sw_frame_group_mgmt_0011 > 1418 1419 <enum 8 sw_frame_group_mgmt_0100 > 1420 1421 <enum 9 sw_frame_group_mgmt_0101 > 1422 1423 <enum 10 sw_frame_group_mgmt_0110 > 1424 1425 <enum 11 sw_frame_group_mgmt_0111 > 1426 1427 <enum 12 sw_frame_group_mgmt_1000 > 1428 1429 <enum 13 sw_frame_group_mgmt_1001 > 1430 1431 <enum 14 sw_frame_group_mgmt_1010 > 1432 1433 <enum 15 sw_frame_group_mgmt_1011 > 1434 1435 <enum 16 sw_frame_group_mgmt_1100 > 1436 1437 <enum 17 sw_frame_group_mgmt_1101 > 1438 1439 <enum 18 sw_frame_group_mgmt_1110 > 1440 1441 <enum 19 sw_frame_group_mgmt_1111 > 1442 1443 1444 1445 <enum 20 sw_frame_group_ctrl_0000 > 1446 1447 <enum 21 sw_frame_group_ctrl_0001 > 1448 1449 <enum 22 sw_frame_group_ctrl_0010 > 1450 1451 <enum 23 sw_frame_group_ctrl_0011 > 1452 1453 <enum 24 sw_frame_group_ctrl_0100 > 1454 1455 <enum 25 sw_frame_group_ctrl_0101 > 1456 1457 <enum 26 sw_frame_group_ctrl_0110 > 1458 1459 <enum 27 sw_frame_group_ctrl_0111 > 1460 1461 <enum 28 sw_frame_group_ctrl_1000 > 1462 1463 <enum 29 sw_frame_group_ctrl_1001 > 1464 1465 <enum 30 sw_frame_group_ctrl_1010 > 1466 1467 <enum 31 sw_frame_group_ctrl_1011 > 1468 1469 <enum 32 sw_frame_group_ctrl_1100 > 1470 1471 <enum 33 sw_frame_group_ctrl_1101 > 1472 1473 <enum 34 sw_frame_group_ctrl_1110 > 1474 1475 <enum 35 sw_frame_group_ctrl_1111 > 1476 1477 1478 1479 <enum 36 sw_frame_group_unsupported> This covers type 3 1480 and protocol version != 0 1481 1482 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1483 can only be rxpcu_monitor_other 1484 1485 1486 1487 1488 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1489 can be rxpcu_filter_pass 1490 1491 1492 1493 <legal 0-37> 1494 */ 1495 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 1496 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 1497 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 1498 1499 /* Description RX_MPDU_INFO_0_NDP_FRAME 1500 1501 When set, the received frame was an NDP frame, and thus 1502 there will be no MPDU data. 1503 1504 <legal all> 1505 */ 1506 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 1507 #define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 1508 #define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 1509 1510 /* Description RX_MPDU_INFO_0_PHY_ERR 1511 1512 When set, a PHY error was received before MAC received 1513 any data, and thus there will be no MPDU data. 1514 1515 <legal all> 1516 */ 1517 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 1518 #define RX_MPDU_INFO_0_PHY_ERR_LSB 10 1519 #define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 1520 1521 /* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER 1522 1523 When set, a PHY error was received before MAC received 1524 the complete MPDU header which was needed for proper 1525 decoding 1526 1527 <legal all> 1528 */ 1529 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 1530 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1531 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1532 1533 /* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR 1534 1535 Set when RXPCU detected a version error in the Frame 1536 control field 1537 1538 <legal all> 1539 */ 1540 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 1541 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 1542 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 1543 1544 /* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID 1545 1546 When set, AST based lookup for this frame has found a 1547 valid result. 1548 1549 1550 1551 Note that for NDP frame this will never be set 1552 1553 <legal all> 1554 */ 1555 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 1556 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 1557 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1558 1559 /* Description RX_MPDU_INFO_0_RESERVED_0A 1560 1561 <legal 0> 1562 */ 1563 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 1564 #define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 1565 #define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 1566 1567 /* Description RX_MPDU_INFO_0_PHY_PPDU_ID 1568 1569 A ppdu counter value that PHY increments for every PPDU 1570 received. The counter value wraps around 1571 1572 <legal all> 1573 */ 1574 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 1575 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 1576 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 1577 1578 /* Description RX_MPDU_INFO_1_AST_INDEX 1579 1580 This field indicates the index of the AST entry 1581 corresponding to this MPDU. It is provided by the GSE module 1582 instantiated in RXPCU. 1583 1584 A value of 0xFFFF indicates an invalid AST index, 1585 meaning that No AST entry was found or NO AST search was 1586 performed 1587 1588 1589 1590 In case of ndp or phy_err, this field will be set to 1591 0xFFFF 1592 1593 <legal all> 1594 */ 1595 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 1596 #define RX_MPDU_INFO_1_AST_INDEX_LSB 0 1597 #define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff 1598 1599 /* Description RX_MPDU_INFO_1_SW_PEER_ID 1600 1601 In case of ndp or phy_err or AST_based_lookup_valid == 1602 0, this field will be set to 0 1603 1604 1605 1606 This field indicates a unique peer identifier. It is set 1607 equal to field 'sw_peer_id' from the AST entry 1608 1609 1610 1611 <legal all> 1612 */ 1613 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 1614 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 1615 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 1616 1617 /* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID 1618 1619 When set, the field Mpdu_Frame_control_field has valid 1620 information 1621 1622 1623 1624 1625 <legal all> 1626 */ 1627 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 1628 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 1629 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1630 1631 /* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID 1632 1633 When set, the field Mpdu_duration_field has valid 1634 information 1635 1636 1637 1638 1639 <legal all> 1640 */ 1641 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 1642 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 1643 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 1644 1645 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID 1646 1647 When set, the fields mac_addr_ad1_..... have valid 1648 information 1649 1650 1651 1652 1653 <legal all> 1654 */ 1655 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 1656 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 1657 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 1658 1659 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID 1660 1661 When set, the fields mac_addr_ad2_..... have valid 1662 information 1663 1664 1665 1666 1667 1668 1669 1670 <legal all> 1671 */ 1672 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 1673 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 1674 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 1675 1676 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID 1677 1678 When set, the fields mac_addr_ad3_..... have valid 1679 information 1680 1681 1682 1683 1684 1685 1686 1687 <legal all> 1688 */ 1689 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 1690 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 1691 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 1692 1693 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID 1694 1695 When set, the fields mac_addr_ad4_..... have valid 1696 information 1697 1698 1699 1700 1701 1702 1703 1704 <legal all> 1705 */ 1706 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 1707 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 1708 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 1709 1710 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID 1711 1712 When set, the fields mpdu_sequence_control_field and 1713 mpdu_sequence_number have valid information as well as field 1714 1715 1716 1717 For MPDUs without a sequence control field, this field 1718 will not be set. 1719 1720 1721 1722 1723 <legal all> 1724 */ 1725 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 1726 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1727 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1728 1729 /* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID 1730 1731 When set, the field mpdu_qos_control_field has valid 1732 information 1733 1734 1735 1736 For MPDUs without a QoS control field, this field will 1737 not be set. 1738 1739 1740 1741 1742 <legal all> 1743 */ 1744 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 1745 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 1746 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1747 1748 /* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID 1749 1750 When set, the field mpdu_HT_control_field has valid 1751 information 1752 1753 1754 1755 For MPDUs without a HT control field, this field will 1756 not be set. 1757 1758 1759 1760 1761 <legal all> 1762 */ 1763 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 1764 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 1765 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1766 1767 /* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID 1768 1769 When set, the encryption related info fields, like IV 1770 and PN are valid 1771 1772 1773 1774 For MPDUs that are not encrypted, this will not be set. 1775 1776 1777 1778 1779 <legal all> 1780 */ 1781 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 1782 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1783 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1784 1785 /* Description RX_MPDU_INFO_2_RESERVED_2A 1786 1787 <legal 0> 1788 */ 1789 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1790 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 10 1791 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x0000fc00 1792 1793 /* Description RX_MPDU_INFO_2_FR_DS 1794 1795 Field only valid when Mpdu_frame_control_valid is set 1796 1797 1798 1799 Set if the from DS bit is set in the frame control. 1800 1801 <legal all> 1802 */ 1803 #define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 1804 #define RX_MPDU_INFO_2_FR_DS_LSB 16 1805 #define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 1806 1807 /* Description RX_MPDU_INFO_2_TO_DS 1808 1809 Field only valid when Mpdu_frame_control_valid is set 1810 1811 1812 1813 Set if the to DS bit is set in the frame control. 1814 1815 <legal all> 1816 */ 1817 #define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 1818 #define RX_MPDU_INFO_2_TO_DS_LSB 17 1819 #define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 1820 1821 /* Description RX_MPDU_INFO_2_ENCRYPTED 1822 1823 Field only valid when Mpdu_frame_control_valid is set. 1824 1825 1826 1827 Protected bit from the frame control. 1828 1829 <legal all> 1830 */ 1831 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 1832 #define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 1833 #define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 1834 1835 /* Description RX_MPDU_INFO_2_MPDU_RETRY 1836 1837 Field only valid when Mpdu_frame_control_valid is set. 1838 1839 1840 1841 Retry bit from the frame control. Only valid when 1842 first_msdu is set. 1843 1844 <legal all> 1845 */ 1846 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 1847 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 1848 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 1849 1850 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER 1851 1852 Field only valid when Mpdu_sequence_control_valid is 1853 set. 1854 1855 1856 1857 The sequence number from the 802.11 header. 1858 1859 <legal all> 1860 */ 1861 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 1862 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 1863 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1864 1865 /* Description RX_MPDU_INFO_3_EPD_EN 1866 1867 Field only valid when AST_based_lookup_valid == 1. 1868 1869 1870 1871 1872 1873 In case of ndp or phy_err or AST_based_lookup_valid == 1874 0, this field will be set to 0 1875 1876 1877 1878 If set to one use EPD instead of LPD 1879 1880 1881 1882 1883 <legal all> 1884 */ 1885 #define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c 1886 #define RX_MPDU_INFO_3_EPD_EN_LSB 0 1887 #define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 1888 1889 /* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED 1890 1891 In case of ndp or phy_err or AST_based_lookup_valid == 1892 0, this field will be set to 0 1893 1894 1895 1896 When set, all frames (data only ?) shall be encrypted. 1897 If not, RX CRYPTO shall set an error flag. 1898 1899 <legal all> 1900 */ 1901 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 1902 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 1903 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 1904 1905 /* Description RX_MPDU_INFO_3_ENCRYPT_TYPE 1906 1907 In case of ndp or phy_err or AST_based_lookup_valid == 1908 0, this field will be set to 0 1909 1910 1911 1912 Indicates type of decrypt cipher used (as defined in the 1913 peer entry) 1914 1915 1916 1917 <enum 0 wep_40> WEP 40-bit 1918 1919 <enum 1 wep_104> WEP 104-bit 1920 1921 <enum 2 tkip_no_mic> TKIP without MIC 1922 1923 <enum 3 wep_128> WEP 128-bit 1924 1925 <enum 4 tkip_with_mic> TKIP with MIC 1926 1927 <enum 5 wapi> WAPI 1928 1929 <enum 6 aes_ccmp_128> AES CCMP 128 1930 1931 <enum 7 no_cipher> No crypto 1932 1933 <enum 8 aes_ccmp_256> AES CCMP 256 1934 1935 <enum 9 aes_gcmp_128> AES CCMP 128 1936 1937 <enum 10 aes_gcmp_256> AES CCMP 256 1938 1939 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 1940 1941 1942 1943 1944 <legal 0-11> 1945 */ 1946 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c 1947 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 1948 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c 1949 1950 /* Description RX_MPDU_INFO_3_MESH_STA 1951 1952 In case of ndp or phy_err or AST_based_lookup_valid == 1953 0, this field will be set to 0 1954 1955 1956 1957 When set, this is a Mesh (11s) STA 1958 1959 <legal all> 1960 */ 1961 #define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c 1962 #define RX_MPDU_INFO_3_MESH_STA_LSB 6 1963 #define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000040 1964 1965 /* Description RX_MPDU_INFO_3_BSSID_HIT 1966 1967 In case of ndp or phy_err or AST_based_lookup_valid == 1968 0, this field will be set to 0 1969 1970 1971 1972 When set, the BSSID of the incoming frame matched one of 1973 the 8 BSSID register values 1974 1975 1976 1977 <legal all> 1978 */ 1979 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c 1980 #define RX_MPDU_INFO_3_BSSID_HIT_LSB 7 1981 #define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000080 1982 1983 /* Description RX_MPDU_INFO_3_BSSID_NUMBER 1984 1985 Field only valid when bssid_hit is set. 1986 1987 1988 1989 This number indicates which one out of the 8 BSSID 1990 register values matched the incoming frame 1991 1992 <legal all> 1993 */ 1994 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c 1995 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 8 1996 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00000f00 1997 1998 /* Description RX_MPDU_INFO_3_TID 1999 2000 Field only valid when mpdu_qos_control_valid is set 2001 2002 2003 2004 The TID field in the QoS control field 2005 2006 <legal all> 2007 */ 2008 #define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c 2009 #define RX_MPDU_INFO_3_TID_LSB 12 2010 #define RX_MPDU_INFO_3_TID_MASK 0x0000f000 2011 2012 /* Description RX_MPDU_INFO_3_RESERVED_3A 2013 2014 <legal 0> 2015 */ 2016 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c 2017 #define RX_MPDU_INFO_3_RESERVED_3A_LSB 16 2018 #define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xffff0000 2019 2020 /* Description RX_MPDU_INFO_4_PN_31_0 2021 2022 2023 2024 2025 2026 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 2027 is valid. 2028 2029 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 2030 WEPSeed[1], pn1}. Only pn[47:0] is valid. 2031 2032 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 2033 pn1, pn0}. Only pn[47:0] is valid. 2034 2035 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 2036 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 2037 pn0}. pn[127:0] are valid. 2038 2039 2040 2041 */ 2042 #define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 2043 #define RX_MPDU_INFO_4_PN_31_0_LSB 0 2044 #define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff 2045 2046 /* Description RX_MPDU_INFO_5_PN_63_32 2047 2048 2049 2050 2051 Bits [63:32] of the PN number. See description for 2052 pn_31_0. 2053 2054 2055 2056 */ 2057 #define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 2058 #define RX_MPDU_INFO_5_PN_63_32_LSB 0 2059 #define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff 2060 2061 /* Description RX_MPDU_INFO_6_PN_95_64 2062 2063 2064 2065 2066 Bits [95:64] of the PN number. See description for 2067 pn_31_0. 2068 2069 2070 2071 */ 2072 #define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 2073 #define RX_MPDU_INFO_6_PN_95_64_LSB 0 2074 #define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff 2075 2076 /* Description RX_MPDU_INFO_7_PN_127_96 2077 2078 2079 2080 2081 Bits [127:96] of the PN number. See description for 2082 pn_31_0. 2083 2084 2085 2086 */ 2087 #define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c 2088 #define RX_MPDU_INFO_7_PN_127_96_LSB 0 2089 #define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff 2090 2091 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2092 2093 In case of ndp or phy_err or AST_based_lookup_valid == 2094 0, this field will be set to 0 2095 2096 2097 2098 Meta data that SW has programmed in the Peer table entry 2099 of the transmitting STA. 2100 2101 <legal all> 2102 */ 2103 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2104 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2105 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2106 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 2107 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 2108 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff 2109 2110 /* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 2111 2112 In case of ndp or phy_err or AST_based_lookup_valid == 2113 0, this field will be set to 0 2114 2115 2116 2117 Address (lower 32 bits) of the REO queue descriptor. 2118 2119 2120 2121 If no Peer entry lookup happened for this frame, the 2122 value wil be set to 0, and the frame shall never be pushed 2123 to REO entrance ring. 2124 2125 <legal all> 2126 */ 2127 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 2128 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 2129 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 2130 2131 /* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 2132 2133 In case of ndp or phy_err or AST_based_lookup_valid == 2134 0, this field will be set to 0 2135 2136 2137 2138 Address (upper 8 bits) of the REO queue descriptor. 2139 2140 2141 2142 If no Peer entry lookup happened for this frame, the 2143 value wil be set to 0, and the frame shall never be pushed 2144 to REO entrance ring. 2145 2146 <legal all> 2147 */ 2148 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 2149 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 2150 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 2151 2152 /* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER 2153 2154 In case of ndp or phy_err or AST_based_lookup_valid == 2155 0, this field will be set to 0 2156 2157 2158 2159 Indicates the MPDU queue ID to which this MPDU link 2160 descriptor belongs 2161 2162 Used for tracking and debugging 2163 2164 <legal all> 2165 */ 2166 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 2167 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 2168 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 2169 2170 /* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING 2171 2172 Indicates that a delimiter FCS error was found in 2173 between the Previous MPDU and this MPDU. 2174 2175 2176 2177 Note that this is just a warning, and does not mean that 2178 this MPDU is corrupted in any way. If it is, there will be 2179 other errors indicated such as FCS or decrypt errors 2180 2181 2182 2183 */ 2184 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 2185 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 2186 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 2187 2188 /* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR 2189 2190 Indicates that the first delimiter had a FCS failure. 2191 Only valid when first_mpdu and first_msdu are set. 2192 2193 2194 2195 */ 2196 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c 2197 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 2198 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 2199 2200 /* Description RX_MPDU_INFO_11_RESERVED_11 2201 2202 <legal 0> 2203 */ 2204 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c 2205 #define RX_MPDU_INFO_11_RESERVED_11_LSB 26 2206 #define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 2207 2208 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2209 2210 2211 2212 2213 The key ID octet from the IV. 2214 2215 2216 2217 In case of ndp or phy_err or AST_based_lookup_valid == 2218 0, this field will be set to 0 2219 2220 <legal all> 2221 */ 2222 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2223 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2224 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2225 2226 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2227 2228 In case of ndp or phy_err or AST_based_lookup_valid == 2229 0, this field will be set to 0 2230 2231 2232 2233 Set if new RX_PEER_ENTRY TLV follows. If clear, 2234 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2235 uses old peer entry or not decrypt. 2236 2237 <legal all> 2238 */ 2239 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2240 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2241 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2242 2243 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2244 2245 In case of ndp or phy_err or AST_based_lookup_valid == 2246 0, this field will be set to 0 2247 2248 2249 2250 Set if decryption is needed. 2251 2252 2253 2254 Note: 2255 2256 When RXPCU sets bit 'ast_index_not_found' and/or 2257 ast_index_timeout', RXPCU will also ensure that this bit is 2258 NOT set 2259 2260 CRYPTO for that reason only needs to evaluate this bit 2261 and non of the other ones. 2262 2263 <legal all> 2264 */ 2265 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2266 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2267 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2268 2269 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2270 2271 In case of ndp or phy_err or AST_based_lookup_valid == 2272 0, this field will be set to 0 2273 2274 2275 2276 Used by the OLE during decapsulation. 2277 2278 2279 2280 Indicates the decapsulation that HW will perform: 2281 2282 2283 2284 <enum 0 PTE_DECAP_RAW> No encapsulation 2285 2286 <enum 1 PTE_DECAP_Native_WiFi> 2287 2288 <enum 2 PTE_DECAP_Ethernet_802_3> Ethernet 2 (DIX) or 2289 802.3 (uses SNAP/LLC) 2290 2291 <legal 0-2> 2292 */ 2293 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2294 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2295 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2296 2297 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2298 2299 In case of ndp or phy_err or AST_based_lookup_valid == 2300 0, this field will be set to 0 2301 2302 2303 2304 Insert 4 byte of all zeros as VLAN tag if the rx payload 2305 does not have VLAN. Used during decapsulation. 2306 2307 <legal all> 2308 */ 2309 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2310 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2311 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2312 2313 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2314 2315 In case of ndp or phy_err or AST_based_lookup_valid == 2316 0, this field will be set to 0 2317 2318 2319 2320 Insert 4 byte of all zeros as double VLAN tag if the rx 2321 payload does not have VLAN. Used during 2322 2323 <legal all> 2324 */ 2325 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2326 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2327 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2328 2329 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2330 2331 In case of ndp or phy_err or AST_based_lookup_valid == 2332 0, this field will be set to 0 2333 2334 2335 2336 Strip the VLAN during decapsulation. Used by the OLE. 2337 2338 <legal all> 2339 */ 2340 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2341 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2342 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2343 2344 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2345 2346 In case of ndp or phy_err or AST_based_lookup_valid == 2347 0, this field will be set to 0 2348 2349 2350 2351 Strip the double VLAN during decapsulation. Used by 2352 the OLE. 2353 2354 <legal all> 2355 */ 2356 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2357 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2358 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2359 2360 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2361 2362 The number of delimiters before this MPDU. 2363 2364 2365 2366 In case of ndp or phy_err, this field will be set to 0 2367 */ 2368 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2369 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2370 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2371 2372 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2373 2374 When set, received frame was part of an A-MPDU. 2375 2376 2377 2378 2379 <legal all> 2380 */ 2381 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2382 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2383 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2384 2385 /* Description RX_MPDU_INFO_12_BAR_FRAME 2386 2387 In case of ndp or phy_err or AST_based_lookup_valid == 2388 0, this field will be set to 0 2389 2390 2391 2392 When set, received frame is a BAR frame 2393 2394 <legal all> 2395 */ 2396 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2397 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2398 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2399 2400 /* Description RX_MPDU_INFO_12_RESERVED_12 2401 2402 <legal 0>. 2403 */ 2404 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2405 #define RX_MPDU_INFO_12_RESERVED_12_LSB 30 2406 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 2407 2408 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2409 2410 In case of ndp or phy_err this field will be set to 0 2411 2412 2413 2414 MPDU length before decapsulation. 2415 2416 <legal all> 2417 */ 2418 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2419 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2420 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2421 2422 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2423 2424 See definition in RX attention descriptor 2425 2426 2427 2428 In case of ndp or phy_err, this field will be set. Note 2429 however that there will not actually be any data contents in 2430 the MPDU. 2431 2432 <legal all> 2433 */ 2434 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2435 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2436 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2437 2438 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2439 2440 In case of ndp or phy_err or Phy_err_during_mpdu_header 2441 this field will be set to 0 2442 2443 2444 2445 See definition in RX attention descriptor 2446 2447 <legal all> 2448 */ 2449 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2450 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2451 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2452 2453 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2454 2455 In case of ndp or phy_err or Phy_err_during_mpdu_header 2456 this field will be set to 0 2457 2458 2459 2460 See definition in RX attention descriptor 2461 2462 <legal all> 2463 */ 2464 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2465 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2466 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2467 2468 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2469 2470 In case of ndp or phy_err or Phy_err_during_mpdu_header 2471 this field will be set to 0 2472 2473 2474 2475 See definition in RX attention descriptor 2476 2477 <legal all> 2478 */ 2479 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2480 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2481 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2482 2483 /* Description RX_MPDU_INFO_13_POWER_MGMT 2484 2485 In case of ndp or phy_err or Phy_err_during_mpdu_header 2486 this field will be set to 0 2487 2488 2489 2490 See definition in RX attention descriptor 2491 2492 <legal all> 2493 */ 2494 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2495 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2496 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2497 2498 /* Description RX_MPDU_INFO_13_NON_QOS 2499 2500 In case of ndp or phy_err or Phy_err_during_mpdu_header 2501 this field will be set to 1 2502 2503 2504 2505 See definition in RX attention descriptor 2506 2507 <legal all> 2508 */ 2509 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 2510 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 2511 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 2512 2513 /* Description RX_MPDU_INFO_13_NULL_DATA 2514 2515 In case of ndp or phy_err or Phy_err_during_mpdu_header 2516 this field will be set to 0 2517 2518 2519 2520 See definition in RX attention descriptor 2521 2522 <legal all> 2523 */ 2524 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 2525 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 2526 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 2527 2528 /* Description RX_MPDU_INFO_13_MGMT_TYPE 2529 2530 In case of ndp or phy_err or Phy_err_during_mpdu_header 2531 this field will be set to 0 2532 2533 2534 2535 See definition in RX attention descriptor 2536 2537 <legal all> 2538 */ 2539 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 2540 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 2541 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 2542 2543 /* Description RX_MPDU_INFO_13_CTRL_TYPE 2544 2545 In case of ndp or phy_err or Phy_err_during_mpdu_header 2546 this field will be set to 0 2547 2548 2549 2550 See definition in RX attention descriptor 2551 2552 <legal all> 2553 */ 2554 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 2555 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 2556 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 2557 2558 /* Description RX_MPDU_INFO_13_MORE_DATA 2559 2560 In case of ndp or phy_err or Phy_err_during_mpdu_header 2561 this field will be set to 0 2562 2563 2564 2565 See definition in RX attention descriptor 2566 2567 <legal all> 2568 */ 2569 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 2570 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 2571 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 2572 2573 /* Description RX_MPDU_INFO_13_EOSP 2574 2575 In case of ndp or phy_err or Phy_err_during_mpdu_header 2576 this field will be set to 0 2577 2578 2579 2580 See definition in RX attention descriptor 2581 2582 <legal all> 2583 */ 2584 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 2585 #define RX_MPDU_INFO_13_EOSP_LSB 24 2586 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 2587 2588 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 2589 2590 In case of ndp or phy_err or Phy_err_during_mpdu_header 2591 this field will be set to 0 2592 2593 2594 2595 See definition in RX attention descriptor 2596 2597 <legal all> 2598 */ 2599 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 2600 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 2601 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 2602 2603 /* Description RX_MPDU_INFO_13_ORDER 2604 2605 In case of ndp or phy_err or Phy_err_during_mpdu_header 2606 this field will be set to 0 2607 2608 2609 2610 See definition in RX attention descriptor 2611 2612 2613 2614 <legal all> 2615 */ 2616 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 2617 #define RX_MPDU_INFO_13_ORDER_LSB 26 2618 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 2619 2620 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 2621 2622 In case of ndp or phy_err or Phy_err_during_mpdu_header 2623 this field will be set to 0 2624 2625 2626 2627 See definition in RX attention descriptor 2628 2629 <legal all> 2630 */ 2631 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 2632 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 2633 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 2634 2635 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 2636 2637 In case of ndp or phy_err or Phy_err_during_mpdu_header 2638 this field will be set to 0 2639 2640 2641 2642 See definition in RX attention descriptor 2643 2644 <legal all> 2645 */ 2646 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 2647 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 2648 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 2649 2650 /* Description RX_MPDU_INFO_13_DIRECTED 2651 2652 In case of ndp or phy_err or Phy_err_during_mpdu_header 2653 this field will be set to 0 2654 2655 2656 2657 See definition in RX attention descriptor 2658 2659 <legal all> 2660 */ 2661 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 2662 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 2663 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 2664 2665 /* Description RX_MPDU_INFO_13_RESERVED_13 2666 2667 <legal 0> 2668 */ 2669 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 2670 #define RX_MPDU_INFO_13_RESERVED_13_LSB 30 2671 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0xc0000000 2672 2673 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 2674 2675 Field only valid when Mpdu_frame_control_valid is set 2676 2677 2678 2679 The frame control field of this received MPDU. 2680 2681 2682 2683 Field only valid when Ndp_frame and phy_err are NOT set 2684 2685 2686 2687 Bytes 0 + 1 of the received MPDU 2688 2689 <legal all> 2690 */ 2691 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2692 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 2693 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2694 2695 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 2696 2697 Field only valid when Mpdu_duration_valid is set 2698 2699 2700 2701 The duration field of this received MPDU. 2702 2703 <legal all> 2704 */ 2705 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 2706 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 2707 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 2708 2709 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 2710 2711 Field only valid when mac_addr_ad1_valid is set 2712 2713 2714 2715 The Least Significant 4 bytes of the Received Frames MAC 2716 Address AD1 2717 2718 <legal all> 2719 */ 2720 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2721 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 2722 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2723 2724 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 2725 2726 Field only valid when mac_addr_ad1_valid is set 2727 2728 2729 2730 The 2 most significant bytes of the Received Frames MAC 2731 Address AD1 2732 2733 <legal all> 2734 */ 2735 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2736 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 2737 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2738 2739 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 2740 2741 Field only valid when mac_addr_ad2_valid is set 2742 2743 2744 2745 The Least Significant 2 bytes of the Received Frames MAC 2746 Address AD2 2747 2748 <legal all> 2749 */ 2750 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2751 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 2752 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2753 2754 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 2755 2756 Field only valid when mac_addr_ad2_valid is set 2757 2758 2759 2760 The 4 most significant bytes of the Received Frames MAC 2761 Address AD2 2762 2763 <legal all> 2764 */ 2765 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2766 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 2767 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2768 2769 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 2770 2771 Field only valid when mac_addr_ad3_valid is set 2772 2773 2774 2775 The Least Significant 4 bytes of the Received Frames MAC 2776 Address AD3 2777 2778 <legal all> 2779 */ 2780 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2781 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 2782 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2783 2784 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 2785 2786 Field only valid when mac_addr_ad3_valid is set 2787 2788 2789 2790 The 2 most significant bytes of the Received Frames MAC 2791 Address AD3 2792 2793 <legal all> 2794 */ 2795 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2796 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 2797 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2798 2799 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 2800 2801 2802 2803 2804 The sequence control field of the MPDU 2805 2806 <legal all> 2807 */ 2808 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2809 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2810 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2811 2812 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 2813 2814 Field only valid when mac_addr_ad4_valid is set 2815 2816 2817 2818 The Least Significant 4 bytes of the Received Frames MAC 2819 Address AD4 2820 2821 <legal all> 2822 */ 2823 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2824 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 2825 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2826 2827 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 2828 2829 Field only valid when mac_addr_ad4_valid is set 2830 2831 2832 2833 The 2 most significant bytes of the Received Frames MAC 2834 Address AD4 2835 2836 <legal all> 2837 */ 2838 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2839 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 2840 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2841 2842 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 2843 2844 Field only valid when mpdu_qos_control_valid is set 2845 2846 2847 2848 The sequence control field of the MPDU 2849 2850 <legal all> 2851 */ 2852 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2853 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 2854 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2855 2856 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 2857 2858 Field only valid when mpdu_qos_control_valid is set 2859 2860 2861 2862 The HT control field of the MPDU 2863 2864 <legal all> 2865 */ 2866 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2867 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 2868 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2869 2870 2871 #endif // _RX_MPDU_INFO_H_ 2872