1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _REO_FLUSH_CACHE_H_ 24 #define _REO_FLUSH_CACHE_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_reo_cmd_header.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 struct uniform_reo_cmd_header cmd_header; 34 // 1 flush_addr_31_0[31:0] 35 // 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15] 36 // 3 reserved_3a[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[31:0] 40 // 7 reserved_7a[31:0] 41 // 8 reserved_8a[31:0] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 46 47 struct reo_flush_cache { 48 struct uniform_reo_cmd_header cmd_header; 49 uint32_t flush_addr_31_0 : 32; //[31:0] 50 uint32_t flush_addr_39_32 : 8, //[7:0] 51 forward_all_mpdus_in_queue : 1, //[8] 52 release_cache_block_index : 1, //[9] 53 cache_block_resource_index : 2, //[11:10] 54 flush_without_invalidate : 1, //[12] 55 block_cache_usage_after_flush : 1, //[13] 56 flush_entire_cache : 1, //[14] 57 reserved_2b : 17; //[31:15] 58 uint32_t reserved_3a : 32; //[31:0] 59 uint32_t reserved_4a : 32; //[31:0] 60 uint32_t reserved_5a : 32; //[31:0] 61 uint32_t reserved_6a : 32; //[31:0] 62 uint32_t reserved_7a : 32; //[31:0] 63 uint32_t reserved_8a : 32; //[31:0] 64 }; 65 66 /* 67 68 struct uniform_reo_cmd_header cmd_header 69 70 Consumer: REO 71 72 Producer: SW 73 74 75 76 Details for command execution tracking purposes. 77 78 flush_addr_31_0 79 80 Consumer: REO 81 82 Producer: SW 83 84 85 86 Address (lower 32 bits) of the descriptor to flush 87 88 <legal all> 89 90 flush_addr_39_32 91 92 Consumer: REO 93 94 Producer: SW 95 96 97 98 Address (upper 8 bits) of the descriptor to flush 99 100 <legal all> 101 102 forward_all_mpdus_in_queue 103 104 Is only allowed to be set when the flush address 105 corresponds with a REO descriptor. 106 107 108 109 When set, REO shall first forward all the MPDUs held in 110 the indicated re-order queue, before flushing the descriptor 111 from the cache. 112 113 <legal all> 114 115 release_cache_block_index 116 117 Field not valid when Flush_entire_cache is set. 118 119 120 121 If SW has previously used a blocking resource that it 122 now wants to re-use for this command, this bit shall be set. 123 It prevents SW from having to send a separate 124 REO_UNBLOCK_CACHE command. 125 126 127 128 When set, HW will first release the blocking resource 129 (indicated in field 'Cache_block_resouce_index') before this 130 command gets executed. 131 132 If that resource was already unblocked, this will be 133 considered an error. This command will not be executed, and 134 an error shall be returned. 135 136 <legal all> 137 138 cache_block_resource_index 139 140 Field not valid when Flush_entire_cache is set. 141 142 143 144 Indicates which of the four blocking resources in REO 145 will be assigned for managing the blocking of this 146 (descriptor) address 147 148 <legal all> 149 150 flush_without_invalidate 151 152 Field not valid when Flush_entire_cache is set. 153 154 155 156 When set, REO shall flush the cache line contents from 157 the cache, but there is NO need to invalidate the cache line 158 entry... The contents in the cache can be maintained. This 159 feature can be used by SW (and DV) to get a current snapshot 160 of the contents in the cache 161 162 163 164 <legal all> 165 166 block_cache_usage_after_flush 167 168 Field not valid when Flush_entire_cache is set. 169 170 171 172 When set, REO shall block any cache accesses to this 173 address till explicitly unblocked. 174 175 176 177 Whenever SW sets this bit, SW shall also set bit 178 'Forward_all_mpdus_in_queue' to ensure all packets are 179 flushed out in order to make sure this queue desc is not in 180 one of the aging link lists. In case SW does not want to 181 flush the MPDUs in the queue, see the recipe description 182 below this TLV definition. 183 184 185 186 The 'blocking' index to be used for this is indicated in 187 field 'cache_block_resource_index'. If SW had previously 188 used this blocking resource and was not freed up yet, SW 189 shall first unblock that index (by setting bit 190 Release_cache_block_index) or use an unblock command. 191 192 193 194 If the resource indicated here was already blocked (and 195 did not get unblocked in this command), it is considered an 196 error scenario... 197 198 No flush shall happen. The status for this command shall 199 indicate error. 200 201 202 203 <legal all> 204 205 flush_entire_cache 206 207 When set, the entire cache shall be flushed. The entire 208 cache will also remain blocked, till the 209 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 210 to unblock_cache. All other fields in this command are to be 211 ignored. 212 213 214 215 Note that flushing the entire cache has no changes to 216 the current settings of the blocking resource settings 217 218 219 220 <legal all> 221 222 reserved_2b 223 224 <legal 0> 225 226 reserved_3a 227 228 <legal 0> 229 230 reserved_4a 231 232 <legal 0> 233 234 reserved_5a 235 236 <legal 0> 237 238 reserved_6a 239 240 <legal 0> 241 242 reserved_7a 243 244 <legal 0> 245 246 reserved_8a 247 248 <legal 0> 249 */ 250 251 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 252 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 253 #define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff 254 255 /* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0 256 257 Consumer: REO 258 259 Producer: SW 260 261 262 263 Address (lower 32 bits) of the descriptor to flush 264 265 <legal all> 266 */ 267 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 268 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 269 #define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff 270 271 /* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32 272 273 Consumer: REO 274 275 Producer: SW 276 277 278 279 Address (upper 8 bits) of the descriptor to flush 280 281 <legal all> 282 */ 283 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 284 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 285 #define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff 286 287 /* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE 288 289 Is only allowed to be set when the flush address 290 corresponds with a REO descriptor. 291 292 293 294 When set, REO shall first forward all the MPDUs held in 295 the indicated re-order queue, before flushing the descriptor 296 from the cache. 297 298 <legal all> 299 */ 300 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 301 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 302 #define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 303 304 /* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX 305 306 Field not valid when Flush_entire_cache is set. 307 308 309 310 If SW has previously used a blocking resource that it 311 now wants to re-use for this command, this bit shall be set. 312 It prevents SW from having to send a separate 313 REO_UNBLOCK_CACHE command. 314 315 316 317 When set, HW will first release the blocking resource 318 (indicated in field 'Cache_block_resouce_index') before this 319 command gets executed. 320 321 If that resource was already unblocked, this will be 322 considered an error. This command will not be executed, and 323 an error shall be returned. 324 325 <legal all> 326 */ 327 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 328 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 329 #define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 330 331 /* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX 332 333 Field not valid when Flush_entire_cache is set. 334 335 336 337 Indicates which of the four blocking resources in REO 338 will be assigned for managing the blocking of this 339 (descriptor) address 340 341 <legal all> 342 */ 343 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 344 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 345 #define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 346 347 /* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE 348 349 Field not valid when Flush_entire_cache is set. 350 351 352 353 When set, REO shall flush the cache line contents from 354 the cache, but there is NO need to invalidate the cache line 355 entry... The contents in the cache can be maintained. This 356 feature can be used by SW (and DV) to get a current snapshot 357 of the contents in the cache 358 359 360 361 <legal all> 362 */ 363 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 364 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 365 #define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 366 367 /* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH 368 369 Field not valid when Flush_entire_cache is set. 370 371 372 373 When set, REO shall block any cache accesses to this 374 address till explicitly unblocked. 375 376 377 378 Whenever SW sets this bit, SW shall also set bit 379 'Forward_all_mpdus_in_queue' to ensure all packets are 380 flushed out in order to make sure this queue desc is not in 381 one of the aging link lists. In case SW does not want to 382 flush the MPDUs in the queue, see the recipe description 383 below this TLV definition. 384 385 386 387 The 'blocking' index to be used for this is indicated in 388 field 'cache_block_resource_index'. If SW had previously 389 used this blocking resource and was not freed up yet, SW 390 shall first unblock that index (by setting bit 391 Release_cache_block_index) or use an unblock command. 392 393 394 395 If the resource indicated here was already blocked (and 396 did not get unblocked in this command), it is considered an 397 error scenario... 398 399 No flush shall happen. The status for this command shall 400 indicate error. 401 402 403 404 <legal all> 405 */ 406 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 407 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 408 #define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 409 410 /* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE 411 412 When set, the entire cache shall be flushed. The entire 413 cache will also remain blocked, till the 414 'REO_UNBLOCK_COMMAND' is received with bit unblock type set 415 to unblock_cache. All other fields in this command are to be 416 ignored. 417 418 419 420 Note that flushing the entire cache has no changes to 421 the current settings of the blocking resource settings 422 423 424 425 <legal all> 426 */ 427 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 428 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 429 #define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 430 431 /* Description REO_FLUSH_CACHE_2_RESERVED_2B 432 433 <legal 0> 434 */ 435 #define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 436 #define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 437 #define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 438 439 /* Description REO_FLUSH_CACHE_3_RESERVED_3A 440 441 <legal 0> 442 */ 443 #define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c 444 #define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 445 #define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff 446 447 /* Description REO_FLUSH_CACHE_4_RESERVED_4A 448 449 <legal 0> 450 */ 451 #define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 452 #define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 453 #define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff 454 455 /* Description REO_FLUSH_CACHE_5_RESERVED_5A 456 457 <legal 0> 458 */ 459 #define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 460 #define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 461 #define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff 462 463 /* Description REO_FLUSH_CACHE_6_RESERVED_6A 464 465 <legal 0> 466 */ 467 #define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 468 #define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 469 #define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff 470 471 /* Description REO_FLUSH_CACHE_7_RESERVED_7A 472 473 <legal 0> 474 */ 475 #define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c 476 #define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 477 #define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff 478 479 /* Description REO_FLUSH_CACHE_8_RESERVED_8A 480 481 <legal 0> 482 */ 483 #define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 484 #define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 485 #define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff 486 487 488 #endif // _REO_FLUSH_CACHE_H_ 489