1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_START_H_ 25 #define _RX_MPDU_START_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_mpdu_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-22 struct rx_mpdu_info rx_mpdu_info_details; 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_RX_MPDU_START 23 39 40 struct rx_mpdu_start { 41 struct rx_mpdu_info rx_mpdu_info_details; 42 }; 43 44 /* 45 46 struct rx_mpdu_info rx_mpdu_info_details 47 48 Structure containing all the MPDU header details that 49 might be needed for other modules further down the received 50 path 51 */ 52 53 54 /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */ 55 56 57 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 58 59 60 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 61 62 The ID of the REO exit ring where the MSDU frame shall 63 push after (MPDU level) reordering has finished. 64 65 66 67 <enum 0 reo_destination_tcl> Reo will push the frame 68 into the REO2TCL ring 69 70 <enum 1 reo_destination_sw1> Reo will push the frame 71 into the REO2SW1 ring 72 73 <enum 2 reo_destination_sw2> Reo will push the frame 74 into the REO2SW2 ring 75 76 <enum 3 reo_destination_sw3> Reo will push the frame 77 into the REO2SW3 ring 78 79 <enum 4 reo_destination_sw4> Reo will push the frame 80 into the REO2SW4 ring 81 82 <enum 5 reo_destination_release> Reo will push the frame 83 into the REO_release ring 84 85 <enum 6 reo_destination_fw> Reo will push the frame into 86 the REO2FW ring 87 88 <enum 7 reo_destination_sw5> Reo will push the frame 89 into the REO2SW5 ring (REO remaps this in chips without 90 REO2SW5 ring, e.g. Pine) 91 92 <enum 8 reo_destination_sw6> Reo will push the frame 93 into the REO2SW6 ring (REO remaps this in chips without 94 REO2SW6 ring, e.g. Pine) 95 96 <enum 9 reo_destination_9> REO remaps this <enum 10 97 reo_destination_10> REO remaps this 98 99 <enum 11 reo_destination_11> REO remaps this 100 101 <enum 12 reo_destination_12> REO remaps this <enum 13 102 reo_destination_13> REO remaps this 103 104 <enum 14 reo_destination_14> REO remaps this 105 106 <enum 15 reo_destination_15> REO remaps this 107 108 <enum 16 reo_destination_16> REO remaps this 109 110 <enum 17 reo_destination_17> REO remaps this 111 112 <enum 18 reo_destination_18> REO remaps this 113 114 <enum 19 reo_destination_19> REO remaps this 115 116 <enum 20 reo_destination_20> REO remaps this 117 118 <enum 21 reo_destination_21> REO remaps this 119 120 <enum 22 reo_destination_22> REO remaps this 121 122 <enum 23 reo_destination_23> REO remaps this 123 124 <enum 24 reo_destination_24> REO remaps this 125 126 <enum 25 reo_destination_25> REO remaps this 127 128 <enum 26 reo_destination_26> REO remaps this 129 130 <enum 27 reo_destination_27> REO remaps this 131 132 <enum 28 reo_destination_28> REO remaps this 133 134 <enum 29 reo_destination_29> REO remaps this 135 136 <enum 30 reo_destination_30> REO remaps this 137 138 <enum 31 reo_destination_31> REO remaps this 139 140 141 142 <legal all> 143 */ 144 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 145 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 146 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 147 148 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 149 150 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 151 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 152 hash[3:0]} using the chosen Toeplitz hash from Common Parser 153 if flow search fails. 154 155 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 156 's not 2'b00, Rx OLE uses a REO desination indication of 157 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 158 from Common Parser if flow search fails. 159 160 This LMAC/peer-based routing is not supported in 161 Hastings80 and HastingsPrime. 162 163 <legal all> 164 */ 165 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 166 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 167 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 168 169 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 170 171 Indication to Rx OLE to enable REO destination routing 172 based on the chosen Toeplitz hash from Common Parser, in 173 case flow search fails 174 175 <legal all> 176 */ 177 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 178 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 179 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 180 181 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 182 183 Filter pass Unicast data frame (matching 184 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 185 selection 186 187 188 189 1'b0: source and destination rings are selected from the 190 RxOLE register settings for the packet type 191 192 193 194 1'b1: source ring and destination ring is selected from 195 the rxdma0_source_ring_selection and 196 rxdma0_destination_ring_selection fields in this STRUCT 197 198 <legal all> 199 */ 200 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 201 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 202 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 203 204 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 205 206 Filter pass Multicast data frame (matching 207 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 208 selection 209 210 211 212 1'b0: source and destination rings are selected from the 213 RxOLE register settings for the packet type 214 215 216 217 1'b1: source ring and destination ring is selected from 218 the rxdma0_source_ring_selection and 219 rxdma0_destination_ring_selection fields in this STRUCT 220 221 <legal all> 222 */ 223 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 224 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 225 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 226 227 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 228 229 Filter pass BAR frame (matching rxpcu_filter_pass and 230 sw_frame_group_ctrl_1000) routing selection 231 232 233 234 1'b0: source and destination rings are selected from the 235 RxOLE register settings for the packet type 236 237 238 239 1'b1: source ring and destination ring is selected from 240 the rxdma0_source_ring_selection and 241 rxdma0_destination_ring_selection fields in this STRUCT 242 243 <legal all> 244 */ 245 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 246 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 247 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 248 249 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 250 251 Field only valid when for the received frame type the 252 corresponding pkt_selection_fp_... bit is set 253 254 255 256 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 257 258 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 259 this frame shall be sourced by fw2rxdma buffer source ring. 260 261 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 262 this frame shall be sourced by sw2rxdma buffer source ring. 263 264 <enum 3 no_buffer_ring> The frame shall not be written 265 to any data buffer. 266 267 268 269 <legal all> 270 */ 271 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 272 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 273 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 274 275 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 276 277 Field only valid when for the received frame type the 278 corresponding pkt_selection_fp_... bit is set 279 280 281 282 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 283 to the Release ring. Effectively this means the frame needs 284 to be dropped. 285 286 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 287 the FW ring. 288 289 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 290 the SW ring. 291 292 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 293 the REO entrance ring. 294 295 296 297 <legal all> 298 */ 299 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 300 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 301 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 302 303 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 304 305 <legal 0> 306 */ 307 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 308 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 309 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 310 311 /* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0 312 313 In case of ndp or phy_err or AST_based_lookup_valid == 314 0, this field will be set to 0 315 316 317 318 Address (lower 32 bits) of the REO queue descriptor. 319 320 321 322 If no Peer entry lookup happened for this frame, the 323 value wil be set to 0, and the frame shall never be pushed 324 to REO entrance ring. 325 326 <legal all> 327 */ 328 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 329 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 330 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 331 332 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32 333 334 In case of ndp or phy_err or AST_based_lookup_valid == 335 0, this field will be set to 0 336 337 338 339 Address (upper 8 bits) of the REO queue descriptor. 340 341 342 343 If no Peer entry lookup happened for this frame, the 344 value wil be set to 0, and the frame shall never be pushed 345 to REO entrance ring. 346 347 <legal all> 348 */ 349 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 350 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 351 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 352 353 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER 354 355 In case of ndp or phy_err or AST_based_lookup_valid == 356 0, this field will be set to 0 357 358 359 360 Indicates the MPDU queue ID to which this MPDU link 361 descriptor belongs 362 363 Used for tracking and debugging 364 365 <legal all> 366 */ 367 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 368 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 369 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 370 371 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING 372 373 Indicates that a delimiter FCS error was found in 374 between the Previous MPDU and this MPDU. 375 376 377 378 Note that this is just a warning, and does not mean that 379 this MPDU is corrupted in any way. If it is, there will be 380 other errors indicated such as FCS or decrypt errors 381 382 383 384 In case of ndp or phy_err, this field will indicate at 385 least one of delimiters located after the last MPDU in the 386 previous PPDU has been corrupted. 387 */ 388 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 389 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 390 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 391 392 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR 393 394 Indicates that the first delimiter had a FCS failure. 395 Only valid when first_mpdu and first_msdu are set. 396 397 398 399 */ 400 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 401 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 402 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 403 404 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A 405 406 <legal 0> 407 */ 408 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 409 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 410 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 411 412 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0 413 414 415 416 417 418 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 419 is valid. 420 421 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 422 WEPSeed[1], pn1}. Only pn[47:0] is valid. 423 424 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 425 pn1, pn0}. Only pn[47:0] is valid. 426 427 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 428 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 429 pn0}. pn[127:0] are valid. 430 431 432 433 */ 434 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c 435 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 436 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff 437 438 /* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32 439 440 441 442 443 Bits [63:32] of the PN number. See description for 444 pn_31_0. 445 446 447 448 */ 449 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 450 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 451 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff 452 453 /* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64 454 455 456 457 458 Bits [95:64] of the PN number. See description for 459 pn_31_0. 460 461 462 463 */ 464 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 465 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 466 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff 467 468 /* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96 469 470 471 472 473 Bits [127:96] of the PN number. See description for 474 pn_31_0. 475 476 477 478 */ 479 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 480 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 481 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff 482 483 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN 484 485 Field only valid when AST_based_lookup_valid == 1. 486 487 488 489 490 491 In case of ndp or phy_err or AST_based_lookup_valid == 492 0, this field will be set to 0 493 494 495 496 If set to one use EPD instead of LPD 497 498 499 500 501 <legal all> 502 */ 503 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c 504 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 505 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 506 507 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED 508 509 In case of ndp or phy_err or AST_based_lookup_valid == 510 0, this field will be set to 0 511 512 513 514 When set, all frames (data only ?) shall be encrypted. 515 If not, RX CRYPTO shall set an error flag. 516 517 <legal all> 518 */ 519 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 520 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 521 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 522 523 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE 524 525 In case of ndp or phy_err or AST_based_lookup_valid == 526 0, this field will be set to 0 527 528 529 530 Indicates type of decrypt cipher used (as defined in the 531 peer entry) 532 533 534 535 <enum 0 wep_40> WEP 40-bit 536 537 <enum 1 wep_104> WEP 104-bit 538 539 <enum 2 tkip_no_mic> TKIP without MIC 540 541 <enum 3 wep_128> WEP 128-bit 542 543 <enum 4 tkip_with_mic> TKIP with MIC 544 545 <enum 5 wapi> WAPI 546 547 <enum 6 aes_ccmp_128> AES CCMP 128 548 549 <enum 7 no_cipher> No crypto 550 551 <enum 8 aes_ccmp_256> AES CCMP 256 552 553 <enum 9 aes_gcmp_128> AES CCMP 128 554 555 <enum 10 aes_gcmp_256> AES CCMP 256 556 557 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 558 559 560 561 <enum 12 wep_varied_width> WEP encryption. As for WEP 562 per keyid the key bit width can vary, the key bit width for 563 this MPDU will be indicated in field 564 wep_key_width_for_variable key 565 566 <legal 0-12> 567 */ 568 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c 569 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 570 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c 571 572 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 573 574 Field only valid when key_type is set to 575 wep_varied_width. 576 577 578 579 This field indicates the size of the wep key for this 580 MPDU. 581 582 583 584 <enum 0 wep_varied_width_40> WEP 40-bit 585 586 <enum 1 wep_varied_width_104> WEP 104-bit 587 588 <enum 2 wep_varied_width_128> WEP 128-bit 589 590 591 592 <legal 0-2> 593 */ 594 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 595 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 596 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 597 598 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA 599 600 In case of ndp or phy_err or AST_based_lookup_valid == 601 0, this field will be set to 0 602 603 604 605 When set, this is a Mesh (11s) STA. 606 607 608 609 The interpretation of the A-MSDU 'Length' field in the 610 MPDU (if any) is decided by the e-numerations below. 611 612 613 614 <enum 0 MESH_DISABLE> 615 616 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 617 includes the length of Mesh Control. 618 619 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 620 excludes the length of Mesh Control. 621 622 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 623 and excludes the length of Mesh Control. This is 624 802.11s-compliant. 625 626 <legal all> 627 */ 628 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000001c 629 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8 630 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000300 631 632 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT 633 634 In case of ndp or phy_err or AST_based_lookup_valid == 635 0, this field will be set to 0 636 637 638 639 When set, the BSSID of the incoming frame matched one of 640 the 8 BSSID register values 641 642 643 644 <legal all> 645 */ 646 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c 647 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 648 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 649 650 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER 651 652 Field only valid when bssid_hit is set. 653 654 655 656 This number indicates which one out of the 8 BSSID 657 register values matched the incoming frame 658 659 <legal all> 660 */ 661 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c 662 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 663 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 664 665 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID 666 667 Field only valid when mpdu_qos_control_valid is set 668 669 670 671 The TID field in the QoS control field 672 673 <legal all> 674 */ 675 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c 676 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 677 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 678 679 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A 680 681 <legal 0> 682 */ 683 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c 684 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 685 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 686 687 /* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA 688 689 In case of ndp or phy_err or AST_based_lookup_valid == 690 0, this field will be set to 0 691 692 693 694 Meta data that SW has programmed in the Peer table entry 695 of the transmitting STA. 696 697 <legal all> 698 */ 699 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 700 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 701 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 702 703 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY 704 705 Field indicates what the reason was that this MPDU frame 706 was allowed to come into the receive path by RXPCU 707 708 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 709 frame filter programming of rxpcu 710 711 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 712 regular frame filter and would have been dropped, were it 713 not for the frame fitting into the 'monitor_client' 714 category. 715 716 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 717 regular frame filter and also did not pass the 718 rxpcu_monitor_client filter. It would have been dropped 719 accept that it did pass the 'monitor_other' category. 720 721 722 723 Note: for ndp frame, if it was expected because the 724 preceding NDPA was filter_pass, the setting 725 rxpcu_filter_pass will be used. This setting will also be 726 used for every ndp frame in case Promiscuous mode is 727 enabled. 728 729 730 731 In case promiscuous is not enabled, and an NDP is not 732 preceded by a NPDA filter pass frame, the only other setting 733 that could appear here for the NDP is rxpcu_monitor_other. 734 735 (rxpcu has a configuration bit specifically for this 736 scenario) 737 738 739 740 Note: for 741 742 <legal 0-2> 743 */ 744 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 745 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 746 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 747 748 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID 749 750 SW processes frames based on certain classifications. 751 This field indicates to what sw classification this MPDU is 752 mapped. 753 754 The classification is given in priority order 755 756 757 758 <enum 0 sw_frame_group_NDP_frame> Note: The 759 corresponding Rxpcu_Mpdu_filter_in_category can be 760 rxpcu_filter_pass or rxpcu_monitor_other 761 762 763 764 <enum 1 sw_frame_group_Multicast_data> 765 766 <enum 2 sw_frame_group_Unicast_data> 767 768 <enum 3 sw_frame_group_Null_data > This includes mpdus 769 of type Data Null as well as QoS Data Null 770 771 772 773 <enum 4 sw_frame_group_mgmt_0000 > 774 775 <enum 5 sw_frame_group_mgmt_0001 > 776 777 <enum 6 sw_frame_group_mgmt_0010 > 778 779 <enum 7 sw_frame_group_mgmt_0011 > 780 781 <enum 8 sw_frame_group_mgmt_0100 > 782 783 <enum 9 sw_frame_group_mgmt_0101 > 784 785 <enum 10 sw_frame_group_mgmt_0110 > 786 787 <enum 11 sw_frame_group_mgmt_0111 > 788 789 <enum 12 sw_frame_group_mgmt_1000 > 790 791 <enum 13 sw_frame_group_mgmt_1001 > 792 793 <enum 14 sw_frame_group_mgmt_1010 > 794 795 <enum 15 sw_frame_group_mgmt_1011 > 796 797 <enum 16 sw_frame_group_mgmt_1100 > 798 799 <enum 17 sw_frame_group_mgmt_1101 > 800 801 <enum 18 sw_frame_group_mgmt_1110 > 802 803 <enum 19 sw_frame_group_mgmt_1111 > 804 805 806 807 <enum 20 sw_frame_group_ctrl_0000 > 808 809 <enum 21 sw_frame_group_ctrl_0001 > 810 811 <enum 22 sw_frame_group_ctrl_0010 > 812 813 <enum 23 sw_frame_group_ctrl_0011 > 814 815 <enum 24 sw_frame_group_ctrl_0100 > 816 817 <enum 25 sw_frame_group_ctrl_0101 > 818 819 <enum 26 sw_frame_group_ctrl_0110 > 820 821 <enum 27 sw_frame_group_ctrl_0111 > 822 823 <enum 28 sw_frame_group_ctrl_1000 > 824 825 <enum 29 sw_frame_group_ctrl_1001 > 826 827 <enum 30 sw_frame_group_ctrl_1010 > 828 829 <enum 31 sw_frame_group_ctrl_1011 > 830 831 <enum 32 sw_frame_group_ctrl_1100 > 832 833 <enum 33 sw_frame_group_ctrl_1101 > 834 835 <enum 34 sw_frame_group_ctrl_1110 > 836 837 <enum 35 sw_frame_group_ctrl_1111 > 838 839 840 841 <enum 36 sw_frame_group_unsupported> This covers type 3 842 and protocol version != 0 843 844 Note: The corresponding Rxpcu_Mpdu_filter_in_category 845 can only be rxpcu_monitor_other 846 847 848 849 850 Note: The corresponding Rxpcu_Mpdu_filter_in_category 851 can be rxpcu_filter_pass 852 853 854 855 <legal 0-37> 856 */ 857 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 858 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 859 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc 860 861 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME 862 863 When set, the received frame was an NDP frame, and thus 864 there will be no MPDU data. 865 866 <legal all> 867 */ 868 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 869 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 870 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 871 872 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR 873 874 When set, a PHY error was received before MAC received 875 any data, and thus there will be no MPDU data. 876 877 <legal all> 878 */ 879 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 880 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 881 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 882 883 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER 884 885 When set, a PHY error was received before MAC received 886 the complete MPDU header which was needed for proper 887 decoding 888 889 <legal all> 890 */ 891 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 892 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 893 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 894 895 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR 896 897 Set when RXPCU detected a version error in the Frame 898 control field 899 900 <legal all> 901 */ 902 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 903 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 904 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 905 906 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID 907 908 When set, AST based lookup for this frame has found a 909 valid result. 910 911 912 913 Note that for NDP frame this will never be set 914 915 <legal all> 916 */ 917 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 918 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 919 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 920 921 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A 922 923 <legal 0> 924 */ 925 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 926 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 927 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 928 929 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID 930 931 A ppdu counter value that PHY increments for every PPDU 932 received. The counter value wraps around 933 934 <legal all> 935 */ 936 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 937 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 938 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 939 940 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX 941 942 This field indicates the index of the AST entry 943 corresponding to this MPDU. It is provided by the GSE module 944 instantiated in RXPCU. 945 946 A value of 0xFFFF indicates an invalid AST index, 947 meaning that No AST entry was found or NO AST search was 948 performed 949 950 951 952 In case of ndp or phy_err, this field will be set to 953 0xFFFF 954 955 <legal all> 956 */ 957 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 958 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 959 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff 960 961 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID 962 963 In case of ndp or phy_err or AST_based_lookup_valid == 964 0, this field will be set to 0 965 966 967 968 This field indicates a unique peer identifier. It is set 969 equal to field 'sw_peer_id' from the AST entry 970 971 972 973 <legal all> 974 */ 975 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 976 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 977 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 978 979 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID 980 981 When set, the field Mpdu_Frame_control_field has valid 982 information 983 984 985 986 987 <legal all> 988 */ 989 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 990 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 991 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 992 993 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID 994 995 When set, the field Mpdu_duration_field has valid 996 information 997 998 999 1000 1001 <legal all> 1002 */ 1003 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c 1004 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 1005 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 1006 1007 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID 1008 1009 When set, the fields mac_addr_ad1_..... have valid 1010 information 1011 1012 1013 1014 1015 <legal all> 1016 */ 1017 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 1018 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 1019 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 1020 1021 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID 1022 1023 When set, the fields mac_addr_ad2_..... have valid 1024 information 1025 1026 1027 1028 1029 1030 1031 1032 <legal all> 1033 */ 1034 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 1035 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 1036 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 1037 1038 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID 1039 1040 When set, the fields mac_addr_ad3_..... have valid 1041 information 1042 1043 1044 1045 1046 1047 1048 1049 <legal all> 1050 */ 1051 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 1052 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 1053 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 1054 1055 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID 1056 1057 When set, the fields mac_addr_ad4_..... have valid 1058 information 1059 1060 1061 1062 1063 1064 1065 1066 <legal all> 1067 */ 1068 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 1069 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 1070 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 1071 1072 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID 1073 1074 When set, the fields mpdu_sequence_control_field and 1075 mpdu_sequence_number have valid information as well as field 1076 1077 1078 1079 For MPDUs without a sequence control field, this field 1080 will not be set. 1081 1082 1083 1084 1085 <legal all> 1086 */ 1087 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 1088 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1089 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1090 1091 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID 1092 1093 When set, the field mpdu_qos_control_field has valid 1094 information 1095 1096 1097 1098 For MPDUs without a QoS control field, this field will 1099 not be set. 1100 1101 1102 1103 1104 <legal all> 1105 */ 1106 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 1107 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 1108 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1109 1110 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID 1111 1112 When set, the field mpdu_HT_control_field has valid 1113 information 1114 1115 1116 1117 For MPDUs without a HT control field, this field will 1118 not be set. 1119 1120 1121 1122 1123 <legal all> 1124 */ 1125 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 1126 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 1127 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1128 1129 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID 1130 1131 When set, the encryption related info fields, like IV 1132 and PN are valid 1133 1134 1135 1136 For MPDUs that are not encrypted, this will not be set. 1137 1138 1139 1140 1141 <legal all> 1142 */ 1143 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 1144 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1145 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1146 1147 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER 1148 1149 Field only valid when Mpdu_sequence_control_valid is set 1150 AND Fragment_flag is set 1151 1152 1153 1154 The fragment number from the 802.11 header 1155 1156 1157 1158 <legal all> 1159 */ 1160 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 1161 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 1162 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1163 1164 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG 1165 1166 The More Fragment bit setting from the MPDU header of 1167 the received frame 1168 1169 1170 1171 <legal all> 1172 */ 1173 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 1174 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 1175 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 1176 1177 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A 1178 1179 <legal 0> 1180 */ 1181 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c 1182 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 1183 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 1184 1185 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS 1186 1187 Field only valid when Mpdu_frame_control_valid is set 1188 1189 1190 1191 Set if the from DS bit is set in the frame control. 1192 1193 <legal all> 1194 */ 1195 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c 1196 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 1197 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 1198 1199 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS 1200 1201 Field only valid when Mpdu_frame_control_valid is set 1202 1203 1204 1205 Set if the to DS bit is set in the frame control. 1206 1207 <legal all> 1208 */ 1209 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c 1210 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 1211 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 1212 1213 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED 1214 1215 Field only valid when Mpdu_frame_control_valid is set. 1216 1217 1218 1219 Protected bit from the frame control. 1220 1221 <legal all> 1222 */ 1223 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c 1224 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 1225 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 1226 1227 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY 1228 1229 Field only valid when Mpdu_frame_control_valid is set. 1230 1231 1232 1233 Retry bit from the frame control. Only valid when 1234 first_msdu is set. 1235 1236 <legal all> 1237 */ 1238 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c 1239 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 1240 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 1241 1242 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 1243 1244 Field only valid when Mpdu_sequence_control_valid is 1245 set. 1246 1247 1248 1249 The sequence number from the 802.11 header. 1250 1251 <legal all> 1252 */ 1253 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 1254 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 1255 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1256 1257 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET 1258 1259 1260 1261 1262 The key ID octet from the IV. 1263 1264 1265 1266 In case of ndp or phy_err or AST_based_lookup_valid == 1267 0, this field will be set to 0 1268 1269 <legal all> 1270 */ 1271 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 1272 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1273 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff 1274 1275 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY 1276 1277 In case of ndp or phy_err or AST_based_lookup_valid == 1278 0, this field will be set to 0 1279 1280 1281 1282 Set if new RX_PEER_ENTRY TLV follows. If clear, 1283 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 1284 uses old peer entry or not decrypt. 1285 1286 <legal all> 1287 */ 1288 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 1289 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1290 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 1291 1292 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED 1293 1294 In case of ndp or phy_err or AST_based_lookup_valid == 1295 0, this field will be set to 0 1296 1297 1298 1299 Set if decryption is needed. 1300 1301 1302 1303 Note: 1304 1305 When RXPCU sets bit 'ast_index_not_found' and/or 1306 ast_index_timeout', RXPCU will also ensure that this bit is 1307 NOT set 1308 1309 CRYPTO for that reason only needs to evaluate this bit 1310 and non of the other ones. 1311 1312 <legal all> 1313 */ 1314 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 1315 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1316 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 1317 1318 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE 1319 1320 In case of ndp or phy_err or AST_based_lookup_valid == 1321 0, this field will be set to 0 1322 1323 1324 1325 Used by the OLE during decapsulation. 1326 1327 1328 1329 Indicates the decapsulation that HW will perform: 1330 1331 1332 1333 <enum 0 RAW> No encapsulation 1334 1335 <enum 1 Native_WiFi> 1336 1337 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 1338 SNAP/LLC) 1339 1340 <enum 3 802_3> Indicate Ethernet 1341 1342 1343 1344 <legal all> 1345 */ 1346 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 1347 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1348 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 1349 1350 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING 1351 1352 In case of ndp or phy_err or AST_based_lookup_valid == 1353 0, this field will be set to 0 1354 1355 1356 1357 Insert 4 byte of all zeros as VLAN tag if the rx payload 1358 does not have VLAN. Used during decapsulation. 1359 1360 <legal all> 1361 */ 1362 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1363 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1364 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1365 1366 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING 1367 1368 In case of ndp or phy_err or AST_based_lookup_valid == 1369 0, this field will be set to 0 1370 1371 1372 1373 Insert 4 byte of all zeros as double VLAN tag if the rx 1374 payload does not have VLAN. Used during 1375 1376 <legal all> 1377 */ 1378 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1379 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1380 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1381 1382 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP 1383 1384 In case of ndp or phy_err or AST_based_lookup_valid == 1385 0, this field will be set to 0 1386 1387 1388 1389 Strip the VLAN during decapsulation. Used by the OLE. 1390 1391 <legal all> 1392 */ 1393 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1394 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1395 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1396 1397 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP 1398 1399 In case of ndp or phy_err or AST_based_lookup_valid == 1400 0, this field will be set to 0 1401 1402 1403 1404 Strip the double VLAN during decapsulation. Used by 1405 the OLE. 1406 1407 <legal all> 1408 */ 1409 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1410 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1411 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1412 1413 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT 1414 1415 The number of delimiters before this MPDU. 1416 1417 1418 1419 Note that this number is cleared at PPDU start. 1420 1421 1422 1423 If this MPDU is the first received MPDU in the PPDU and 1424 this MPDU gets filtered-in, this field will indicate the 1425 number of delimiters located after the last MPDU in the 1426 previous PPDU. 1427 1428 1429 1430 If this MPDU is located after the first received MPDU in 1431 an PPDU, this field will indicate the number of delimiters 1432 located between the previous MPDU and this MPDU. 1433 1434 1435 1436 In case of ndp or phy_err, this field will indicate the 1437 number of delimiters located after the last MPDU in the 1438 previous PPDU. 1439 1440 <legal all> 1441 */ 1442 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 1443 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1444 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 1445 1446 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG 1447 1448 When set, received frame was part of an A-MPDU. 1449 1450 1451 1452 1453 <legal all> 1454 */ 1455 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 1456 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1457 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 1458 1459 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME 1460 1461 In case of ndp or phy_err or AST_based_lookup_valid == 1462 0, this field will be set to 0 1463 1464 1465 1466 When set, received frame is a BAR frame 1467 1468 <legal all> 1469 */ 1470 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 1471 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1472 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 1473 1474 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU 1475 1476 Consumer: SW 1477 1478 Producer: RXOLE 1479 1480 1481 1482 RXPCU sets this field to 0 and RXOLE overwrites it. 1483 1484 1485 1486 Set to 1 by RXOLE when it has not performed any 802.11 1487 to Ethernet/Natvie WiFi header conversion on this MPDU. 1488 1489 <legal all> 1490 */ 1491 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 1492 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 1493 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 1494 1495 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12 1496 1497 <legal 0> 1498 */ 1499 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 1500 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 1501 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 1502 1503 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH 1504 1505 In case of ndp or phy_err this field will be set to 0 1506 1507 1508 1509 MPDU length before decapsulation. 1510 1511 <legal all> 1512 */ 1513 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 1514 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 1515 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff 1516 1517 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU 1518 1519 See definition in RX attention descriptor 1520 1521 1522 1523 In case of ndp or phy_err, this field will be set. Note 1524 however that there will not actually be any data contents in 1525 the MPDU. 1526 1527 <legal all> 1528 */ 1529 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 1530 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 1531 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 1532 1533 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST 1534 1535 In case of ndp or phy_err or Phy_err_during_mpdu_header 1536 this field will be set to 0 1537 1538 1539 1540 See definition in RX attention descriptor 1541 1542 <legal all> 1543 */ 1544 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 1545 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 1546 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 1547 1548 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND 1549 1550 In case of ndp or phy_err or Phy_err_during_mpdu_header 1551 this field will be set to 0 1552 1553 1554 1555 See definition in RX attention descriptor 1556 1557 <legal all> 1558 */ 1559 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1560 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 1561 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 1562 1563 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT 1564 1565 In case of ndp or phy_err or Phy_err_during_mpdu_header 1566 this field will be set to 0 1567 1568 1569 1570 See definition in RX attention descriptor 1571 1572 <legal all> 1573 */ 1574 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1575 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 1576 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 1577 1578 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT 1579 1580 In case of ndp or phy_err or Phy_err_during_mpdu_header 1581 this field will be set to 0 1582 1583 1584 1585 See definition in RX attention descriptor 1586 1587 <legal all> 1588 */ 1589 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 1590 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 1591 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 1592 1593 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS 1594 1595 In case of ndp or phy_err or Phy_err_during_mpdu_header 1596 this field will be set to 1 1597 1598 1599 1600 See definition in RX attention descriptor 1601 1602 <legal all> 1603 */ 1604 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 1605 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 1606 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 1607 1608 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA 1609 1610 In case of ndp or phy_err or Phy_err_during_mpdu_header 1611 this field will be set to 0 1612 1613 1614 1615 See definition in RX attention descriptor 1616 1617 <legal all> 1618 */ 1619 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 1620 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 1621 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 1622 1623 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE 1624 1625 In case of ndp or phy_err or Phy_err_during_mpdu_header 1626 this field will be set to 0 1627 1628 1629 1630 See definition in RX attention descriptor 1631 1632 <legal all> 1633 */ 1634 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 1635 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 1636 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 1637 1638 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE 1639 1640 In case of ndp or phy_err or Phy_err_during_mpdu_header 1641 this field will be set to 0 1642 1643 1644 1645 See definition in RX attention descriptor 1646 1647 <legal all> 1648 */ 1649 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 1650 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 1651 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 1652 1653 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA 1654 1655 In case of ndp or phy_err or Phy_err_during_mpdu_header 1656 this field will be set to 0 1657 1658 1659 1660 See definition in RX attention descriptor 1661 1662 <legal all> 1663 */ 1664 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 1665 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 1666 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 1667 1668 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP 1669 1670 In case of ndp or phy_err or Phy_err_during_mpdu_header 1671 this field will be set to 0 1672 1673 1674 1675 See definition in RX attention descriptor 1676 1677 <legal all> 1678 */ 1679 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 1680 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 1681 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 1682 1683 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG 1684 1685 In case of ndp or phy_err or Phy_err_during_mpdu_header 1686 this field will be set to 0 1687 1688 1689 1690 See definition in RX attention descriptor 1691 1692 <legal all> 1693 */ 1694 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 1695 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 1696 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 1697 1698 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER 1699 1700 In case of ndp or phy_err or Phy_err_during_mpdu_header 1701 this field will be set to 0 1702 1703 1704 1705 See definition in RX attention descriptor 1706 1707 1708 1709 <legal all> 1710 */ 1711 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 1712 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 1713 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 1714 1715 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER 1716 1717 In case of ndp or phy_err or Phy_err_during_mpdu_header 1718 this field will be set to 0 1719 1720 1721 1722 See definition in RX attention descriptor 1723 1724 <legal all> 1725 */ 1726 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 1727 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 1728 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 1729 1730 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED 1731 1732 In case of ndp or phy_err or Phy_err_during_mpdu_header 1733 this field will be set to 0 1734 1735 1736 1737 See definition in RX attention descriptor 1738 1739 <legal all> 1740 */ 1741 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 1742 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 1743 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 1744 1745 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED 1746 1747 In case of ndp or phy_err or Phy_err_during_mpdu_header 1748 this field will be set to 0 1749 1750 1751 1752 See definition in RX attention descriptor 1753 1754 <legal all> 1755 */ 1756 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 1757 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 1758 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 1759 1760 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT 1761 1762 Field only valid when Mpdu_qos_control_valid is set 1763 1764 1765 1766 The 'amsdu_present' bit within the QoS control field of 1767 the MPDU 1768 1769 <legal all> 1770 */ 1771 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 1772 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 1773 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 1774 1775 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13 1776 1777 <legal 0> 1778 */ 1779 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 1780 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 1781 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 1782 1783 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD 1784 1785 Field only valid when Mpdu_frame_control_valid is set 1786 1787 1788 1789 The frame control field of this received MPDU. 1790 1791 1792 1793 Field only valid when Ndp_frame and phy_err are NOT set 1794 1795 1796 1797 Bytes 0 + 1 of the received MPDU 1798 1799 <legal all> 1800 */ 1801 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1802 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1803 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1804 1805 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD 1806 1807 Field only valid when Mpdu_duration_valid is set 1808 1809 1810 1811 The duration field of this received MPDU. 1812 1813 <legal all> 1814 */ 1815 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 1816 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1817 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 1818 1819 /* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0 1820 1821 Field only valid when mac_addr_ad1_valid is set 1822 1823 1824 1825 The Least Significant 4 bytes of the Received Frames MAC 1826 Address AD1 1827 1828 <legal all> 1829 */ 1830 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1831 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 1832 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1833 1834 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32 1835 1836 Field only valid when mac_addr_ad1_valid is set 1837 1838 1839 1840 The 2 most significant bytes of the Received Frames MAC 1841 Address AD1 1842 1843 <legal all> 1844 */ 1845 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1846 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1847 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1848 1849 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0 1850 1851 Field only valid when mac_addr_ad2_valid is set 1852 1853 1854 1855 The Least Significant 2 bytes of the Received Frames MAC 1856 Address AD2 1857 1858 <legal all> 1859 */ 1860 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1861 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1862 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1863 1864 /* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16 1865 1866 Field only valid when mac_addr_ad2_valid is set 1867 1868 1869 1870 The 4 most significant bytes of the Received Frames MAC 1871 Address AD2 1872 1873 <legal all> 1874 */ 1875 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1876 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 1877 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1878 1879 /* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0 1880 1881 Field only valid when mac_addr_ad3_valid is set 1882 1883 1884 1885 The Least Significant 4 bytes of the Received Frames MAC 1886 Address AD3 1887 1888 <legal all> 1889 */ 1890 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1891 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1892 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1893 1894 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32 1895 1896 Field only valid when mac_addr_ad3_valid is set 1897 1898 1899 1900 The 2 most significant bytes of the Received Frames MAC 1901 Address AD3 1902 1903 <legal all> 1904 */ 1905 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1906 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 1907 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1908 1909 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD 1910 1911 1912 1913 1914 The sequence control field of the MPDU 1915 1916 <legal all> 1917 */ 1918 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1919 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1920 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1921 1922 /* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0 1923 1924 Field only valid when mac_addr_ad4_valid is set 1925 1926 1927 1928 The Least Significant 4 bytes of the Received Frames MAC 1929 Address AD4 1930 1931 <legal all> 1932 */ 1933 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1934 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1935 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1936 1937 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32 1938 1939 Field only valid when mac_addr_ad4_valid is set 1940 1941 1942 1943 The 2 most significant bytes of the Received Frames MAC 1944 Address AD4 1945 1946 <legal all> 1947 */ 1948 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1949 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 1950 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1951 1952 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD 1953 1954 Field only valid when mpdu_qos_control_valid is set 1955 1956 1957 1958 The sequence control field of the MPDU 1959 1960 <legal all> 1961 */ 1962 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1963 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 1964 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1965 1966 /* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD 1967 1968 Field only valid when mpdu_qos_control_valid is set 1969 1970 1971 1972 The HT control field of the MPDU 1973 1974 <legal all> 1975 */ 1976 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1977 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 1978 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1979 1980 1981 #endif // _RX_MPDU_START_H_ 1982