1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/13/2019 22 // User Name:sanjdas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __REO_REG_SEQ_REG_H__ 29 #define __REO_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "reo_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block REO_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register REO_R0_GENERAL_ENABLE //// 45 46 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 47 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 48 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xffffffff 49 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 50 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 51 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 52 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 53 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 54 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 55 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 56 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 64 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x1f 65 66 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 67 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 0x1e 68 69 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 70 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 0x1d 71 72 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 73 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1c 74 75 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x08000000 76 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1b 77 78 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x07800000 79 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x17 80 81 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00400000 82 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x16 83 84 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00200000 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x15 86 87 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00100000 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x14 89 90 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00080000 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x13 92 93 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00040000 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x12 95 96 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00020000 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x11 98 99 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00010000 100 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0x10 101 102 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00008000 103 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xf 104 105 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00004000 106 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xe 107 108 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00002000 109 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xd 110 111 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00001000 112 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xc 113 114 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000e00 115 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x9 116 117 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000100 118 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x8 119 120 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x000000f0 121 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 122 123 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 124 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 125 126 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 127 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 128 129 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 130 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 131 132 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 133 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 134 135 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 136 137 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 138 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 139 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff 140 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 0 141 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 142 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 143 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 144 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 145 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 146 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 147 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 148 do {\ 149 HWIO_INTLOCK(); \ 150 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 151 HWIO_INTFREE();\ 152 } while (0) 153 154 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1c 156 157 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x0f000000 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x18 159 160 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00f00000 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x14 162 163 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x000f0000 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x10 165 166 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x0000f000 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0xc 168 169 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000f00 170 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0x8 171 172 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x000000f0 173 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0x4 174 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x0000000f 176 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x0 177 178 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 179 180 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 181 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 182 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff 183 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 0 184 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 185 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 186 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 187 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 188 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 189 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 190 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 191 do {\ 192 HWIO_INTLOCK(); \ 193 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 194 HWIO_INTFREE();\ 195 } while (0) 196 197 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xf0000000 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1c 199 200 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x0f000000 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x18 202 203 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00f00000 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x14 205 206 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x000f0000 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x10 208 209 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x0000f000 210 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0xc 211 212 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000f00 213 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0x8 214 215 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x000000f0 216 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0x4 217 218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x0000000f 219 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x0 220 221 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 222 223 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 224 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 225 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffffff 226 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 0 227 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 228 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 229 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 230 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 231 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 232 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 233 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 234 do {\ 235 HWIO_INTLOCK(); \ 236 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 237 HWIO_INTFREE();\ 238 } while (0) 239 240 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1c 242 243 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x0f000000 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x18 245 246 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00f00000 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x14 248 249 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x000f0000 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x10 251 252 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x0000f000 253 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0xc 254 255 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000f00 256 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0x8 257 258 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x000000f0 259 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0x4 260 261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x0000000f 262 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x0 263 264 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 265 266 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 267 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 268 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffffff 269 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 0 270 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 271 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 272 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 273 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 274 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 275 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 276 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 277 do {\ 278 HWIO_INTLOCK(); \ 279 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 280 HWIO_INTFREE();\ 281 } while (0) 282 283 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1c 285 286 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x0f000000 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x18 288 289 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00f00000 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x14 291 292 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x000f0000 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x10 294 295 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x0000f000 296 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0xc 297 298 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000f00 299 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0x8 300 301 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x000000f0 302 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0x4 303 304 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x0000000f 305 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x0 306 307 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 308 309 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 310 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 311 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffffff 312 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 0 313 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 314 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 315 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 316 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 317 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 318 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 319 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 320 do {\ 321 HWIO_INTLOCK(); \ 322 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 323 HWIO_INTFREE();\ 324 } while (0) 325 326 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xf0000000 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1c 328 329 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x0f000000 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x18 331 332 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00f00000 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x14 334 335 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x000f0000 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x10 337 338 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x0000f000 339 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0xc 340 341 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000f00 342 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0x8 343 344 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x000000f0 345 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0x4 346 347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x0000000f 348 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x0 349 350 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 351 352 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 353 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 354 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffffff 355 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 0 356 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 357 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 358 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 359 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 360 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 361 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 362 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 363 do {\ 364 HWIO_INTLOCK(); \ 365 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 366 HWIO_INTFREE();\ 367 } while (0) 368 369 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xf0000000 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1c 371 372 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x0f000000 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x18 374 375 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00f00000 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x14 377 378 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x000f0000 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x10 380 381 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x0000f000 382 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0xc 383 384 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000f00 385 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0x8 386 387 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x000000f0 388 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0x4 389 390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x0000000f 391 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x0 392 393 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 394 395 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 396 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 397 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffffff 398 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 0 399 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 400 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 401 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 402 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 403 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 404 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 405 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 406 do {\ 407 HWIO_INTLOCK(); \ 408 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 409 HWIO_INTFREE();\ 410 } while (0) 411 412 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xf0000000 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1c 414 415 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x0f000000 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x18 417 418 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00f00000 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x14 420 421 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x000f0000 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x10 423 424 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x0000f000 425 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0xc 426 427 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000f00 428 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0x8 429 430 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x000000f0 431 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0x4 432 433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x0000000f 434 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x0 435 436 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 437 438 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 439 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 440 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffffff 441 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 0 442 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 443 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 444 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 445 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 446 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 447 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 448 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 449 do {\ 450 HWIO_INTLOCK(); \ 451 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 452 HWIO_INTFREE();\ 453 } while (0) 454 455 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xf0000000 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1c 457 458 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x0f000000 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x18 460 461 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00f00000 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x14 463 464 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x000f0000 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x10 466 467 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x0000f000 468 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0xc 469 470 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000f00 471 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0x8 472 473 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x000000f0 474 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0x4 475 476 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x0000000f 477 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x0 478 479 //// Register REO_R0_TIMESTAMP //// 480 481 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 482 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 483 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 484 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 485 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 486 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 487 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 488 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 489 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 490 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 491 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 492 do {\ 493 HWIO_INTLOCK(); \ 494 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 495 HWIO_INTFREE();\ 496 } while (0) 497 498 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 499 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 500 501 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 502 503 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 504 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 505 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0xffffffff 506 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 507 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 508 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 509 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 510 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 511 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 512 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 513 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 514 do {\ 515 HWIO_INTLOCK(); \ 516 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 517 HWIO_INTFREE();\ 518 } while (0) 519 520 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x1c 522 523 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x0f000000 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x18 525 526 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00f00000 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0x14 528 529 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x000f0000 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0x10 531 532 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x0000f000 533 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0xc 534 535 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000f00 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x8 537 538 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x000000f0 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x4 540 541 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x0000000f 542 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 543 544 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 545 546 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 547 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 548 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0xffffffff 549 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 550 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 551 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 552 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 553 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 554 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 555 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 556 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 557 do {\ 558 HWIO_INTLOCK(); \ 559 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 560 HWIO_INTFREE();\ 561 } while (0) 562 563 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0xf0000000 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0x1c 565 566 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x0f000000 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0x18 568 569 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00f00000 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x14 571 572 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000f0000 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x10 574 575 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x0000f000 576 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0xc 577 578 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000f00 579 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x8 580 581 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x000000f0 582 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 0x4 583 584 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x0000000f 585 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0x0 586 587 //// Register REO_R0_IDLE_REQ_CTRL //// 588 589 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 590 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 591 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 592 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 593 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 594 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 595 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 596 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 597 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 598 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 599 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 600 do {\ 601 HWIO_INTLOCK(); \ 602 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 603 HWIO_INTFREE();\ 604 } while (0) 605 606 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 607 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 608 609 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 610 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 611 612 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 613 614 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 615 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 616 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 617 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 618 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 619 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 620 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 621 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 622 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 623 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 624 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 625 do {\ 626 HWIO_INTLOCK(); \ 627 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 628 HWIO_INTFREE();\ 629 } while (0) 630 631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 632 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 633 634 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 635 636 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 637 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 638 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 639 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 640 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 641 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 642 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 643 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 644 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 645 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 646 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 647 do {\ 648 HWIO_INTLOCK(); \ 649 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 650 HWIO_INTFREE();\ 651 } while (0) 652 653 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 654 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 655 656 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 657 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 658 659 //// Register REO_R0_RXDMA2REO0_RING_ID //// 660 661 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 662 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 663 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 664 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 665 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 666 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 667 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 668 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 669 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 670 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 671 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 672 do {\ 673 HWIO_INTLOCK(); \ 674 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 675 HWIO_INTFREE();\ 676 } while (0) 677 678 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 679 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 680 681 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 682 683 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 684 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 685 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 686 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 687 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 688 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 689 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 690 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 691 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 692 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 693 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 694 do {\ 695 HWIO_INTLOCK(); \ 696 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 697 HWIO_INTFREE();\ 698 } while (0) 699 700 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 701 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 702 703 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 704 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 705 706 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 707 708 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 709 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 710 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff 711 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 712 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 713 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 714 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 715 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 716 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 717 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 718 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 719 do {\ 720 HWIO_INTLOCK(); \ 721 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 722 HWIO_INTFREE();\ 723 } while (0) 724 725 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe 727 728 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 730 731 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 733 734 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 735 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 736 737 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 738 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 739 740 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 741 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 742 743 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 744 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 745 746 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 747 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 748 749 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 750 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 751 752 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 753 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 754 755 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 756 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 757 758 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 759 760 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 761 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 762 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 763 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 764 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 765 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 766 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 767 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 768 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 769 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 770 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 771 do {\ 772 HWIO_INTLOCK(); \ 773 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 774 HWIO_INTFREE();\ 775 } while (0) 776 777 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 778 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 779 780 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 781 782 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 783 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 784 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 785 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 786 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 787 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 788 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 789 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 790 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 791 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 792 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 793 do {\ 794 HWIO_INTLOCK(); \ 795 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 796 HWIO_INTFREE();\ 797 } while (0) 798 799 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 800 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 801 802 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 803 804 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 805 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 806 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 807 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 808 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 809 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 810 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 811 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 812 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 813 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 814 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 815 do {\ 816 HWIO_INTLOCK(); \ 817 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 818 HWIO_INTFREE();\ 819 } while (0) 820 821 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 822 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 823 824 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 825 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 826 827 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 828 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 829 830 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 831 832 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 833 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 834 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 835 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 836 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 837 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 838 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 839 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 840 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 841 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 842 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 843 do {\ 844 HWIO_INTLOCK(); \ 845 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 846 HWIO_INTFREE();\ 847 } while (0) 848 849 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 850 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 851 852 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 853 854 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 855 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 856 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 857 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 858 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 859 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 860 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 861 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 862 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 863 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 864 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 865 do {\ 866 HWIO_INTLOCK(); \ 867 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 868 HWIO_INTFREE();\ 869 } while (0) 870 871 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 872 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 873 874 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 875 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 876 877 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 878 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 879 880 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 881 882 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 883 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 884 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 885 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 886 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 887 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 888 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 889 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 890 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 891 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 892 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 893 do {\ 894 HWIO_INTLOCK(); \ 895 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 896 HWIO_INTFREE();\ 897 } while (0) 898 899 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 900 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 901 902 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 903 904 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 905 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 906 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 907 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 908 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 909 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 910 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 911 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 912 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 913 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 914 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 915 do {\ 916 HWIO_INTLOCK(); \ 917 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 918 HWIO_INTFREE();\ 919 } while (0) 920 921 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 922 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 923 924 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 925 926 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 927 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 928 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 929 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 930 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 931 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 932 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 933 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 934 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 935 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 936 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 937 do {\ 938 HWIO_INTLOCK(); \ 939 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 940 HWIO_INTFREE();\ 941 } while (0) 942 943 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 944 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 945 946 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 947 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 948 949 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 950 951 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 952 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 953 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 954 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 955 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 956 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 957 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 958 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 959 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 960 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 961 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 962 do {\ 963 HWIO_INTLOCK(); \ 964 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 965 HWIO_INTFREE();\ 966 } while (0) 967 968 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 969 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 970 971 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 972 973 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 974 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 975 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 976 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 977 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 978 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 979 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 980 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 981 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 982 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 983 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 984 do {\ 985 HWIO_INTLOCK(); \ 986 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 987 HWIO_INTFREE();\ 988 } while (0) 989 990 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 991 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 992 993 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 994 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 995 996 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 997 998 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 999 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 1000 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 1001 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 1002 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 1003 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 1004 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 1005 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 1006 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 1007 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 1008 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 1009 do {\ 1010 HWIO_INTLOCK(); \ 1011 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 1012 HWIO_INTFREE();\ 1013 } while (0) 1014 1015 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1016 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 1017 1018 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 1019 1020 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 1021 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 1022 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1023 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1024 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1025 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1026 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1027 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1028 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1029 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1030 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1031 do {\ 1032 HWIO_INTLOCK(); \ 1033 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1034 HWIO_INTFREE();\ 1035 } while (0) 1036 1037 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1038 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1039 1040 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1041 1042 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1043 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1044 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1045 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1046 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1047 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1048 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1049 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1050 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1051 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1052 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1053 do {\ 1054 HWIO_INTLOCK(); \ 1055 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1056 HWIO_INTFREE();\ 1057 } while (0) 1058 1059 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1060 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1061 1062 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1063 1064 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1065 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1066 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1067 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1068 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1069 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1070 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1071 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1072 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1073 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1074 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1075 do {\ 1076 HWIO_INTLOCK(); \ 1077 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1078 HWIO_INTFREE();\ 1079 } while (0) 1080 1081 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1082 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1083 1084 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1085 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1086 1087 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1088 1089 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000094) 1090 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000094) 1091 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1092 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1093 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1094 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1095 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1096 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1097 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1098 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1099 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1100 do {\ 1101 HWIO_INTLOCK(); \ 1102 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1103 HWIO_INTFREE();\ 1104 } while (0) 1105 1106 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1107 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1108 1109 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1110 1111 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000098) 1112 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000098) 1113 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1114 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1115 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1116 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1117 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1118 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1119 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1120 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1121 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1122 do {\ 1123 HWIO_INTLOCK(); \ 1124 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1125 HWIO_INTFREE();\ 1126 } while (0) 1127 1128 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1129 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1130 1131 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1132 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1133 1134 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1135 1136 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000009c) 1137 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000009c) 1138 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff 1139 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1140 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1141 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1142 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1143 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1144 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1145 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1146 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1147 do {\ 1148 HWIO_INTLOCK(); \ 1149 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 1150 HWIO_INTFREE();\ 1151 } while (0) 1152 1153 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1154 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe 1155 1156 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1157 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1158 1159 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1160 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1161 1162 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1163 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1164 1165 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1166 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 1167 1168 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1169 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1170 1171 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1172 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1173 1174 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1175 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1176 1177 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1178 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 1179 1180 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1181 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1182 1183 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1184 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1185 1186 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 1187 1188 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1189 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1190 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 1191 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 1192 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 1193 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 1194 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 1195 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 1196 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 1197 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 1198 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1199 do {\ 1200 HWIO_INTLOCK(); \ 1201 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 1202 HWIO_INTFREE();\ 1203 } while (0) 1204 1205 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1206 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1207 1208 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 1209 1210 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1211 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1212 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 1213 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 1214 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 1215 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 1216 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 1217 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 1218 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 1219 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 1220 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1221 do {\ 1222 HWIO_INTLOCK(); \ 1223 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 1224 HWIO_INTFREE();\ 1225 } while (0) 1226 1227 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1228 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1229 1230 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 1231 1232 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1233 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1234 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1235 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1236 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1237 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1238 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1239 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1240 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1241 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1242 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1243 do {\ 1244 HWIO_INTLOCK(); \ 1245 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1246 HWIO_INTFREE();\ 1247 } while (0) 1248 1249 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1250 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1251 1252 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1253 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1254 1255 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1256 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1257 1258 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 1259 1260 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1261 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1262 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1263 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1264 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1265 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1266 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1267 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1268 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1269 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1270 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1271 do {\ 1272 HWIO_INTLOCK(); \ 1273 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1274 HWIO_INTFREE();\ 1275 } while (0) 1276 1277 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1278 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1279 1280 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 1281 1282 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1283 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1284 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1285 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 1286 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 1287 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 1288 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1289 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1290 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1291 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1292 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1293 do {\ 1294 HWIO_INTLOCK(); \ 1295 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 1296 HWIO_INTFREE();\ 1297 } while (0) 1298 1299 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1300 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1301 1302 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1303 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1304 1305 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1306 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1307 1308 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 1309 1310 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1311 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1312 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1313 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1314 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1315 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1316 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1317 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1318 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1319 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1320 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1321 do {\ 1322 HWIO_INTLOCK(); \ 1323 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1324 HWIO_INTFREE();\ 1325 } while (0) 1326 1327 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1328 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1329 1330 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 1331 1332 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1333 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1334 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1335 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1336 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1337 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1338 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1339 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1340 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1341 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1342 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1343 do {\ 1344 HWIO_INTLOCK(); \ 1345 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1346 HWIO_INTFREE();\ 1347 } while (0) 1348 1349 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1350 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1351 1352 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 1353 1354 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1355 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1356 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1357 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1358 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1359 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1360 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1361 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1362 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1363 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1364 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1365 do {\ 1366 HWIO_INTLOCK(); \ 1367 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1368 HWIO_INTFREE();\ 1369 } while (0) 1370 1371 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1372 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1373 1374 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1375 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1376 1377 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB //// 1378 1379 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1380 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1381 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1382 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0 1383 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ 1384 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK) 1385 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ 1386 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 1387 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ 1388 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) 1389 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1390 do {\ 1391 HWIO_INTLOCK(); \ 1392 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \ 1393 HWIO_INTFREE();\ 1394 } while (0) 1395 1396 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1397 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1398 1399 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB //// 1400 1401 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1402 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1403 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1404 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0 1405 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ 1406 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK) 1407 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ 1408 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 1409 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ 1410 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) 1411 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1412 do {\ 1413 HWIO_INTLOCK(); \ 1414 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \ 1415 HWIO_INTFREE();\ 1416 } while (0) 1417 1418 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1419 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1420 1421 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1422 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1423 1424 //// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA //// 1425 1426 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1427 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1428 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff 1429 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0 1430 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ 1431 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK) 1432 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ 1433 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) 1434 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \ 1435 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val) 1436 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ 1437 do {\ 1438 HWIO_INTLOCK(); \ 1439 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \ 1440 HWIO_INTFREE();\ 1441 } while (0) 1442 1443 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1444 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 1445 1446 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 1447 1448 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1449 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1450 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1451 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 1452 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 1453 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 1454 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1455 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1456 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1457 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1458 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1459 do {\ 1460 HWIO_INTLOCK(); \ 1461 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 1462 HWIO_INTFREE();\ 1463 } while (0) 1464 1465 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1466 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1467 1468 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 1469 1470 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1471 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1472 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 1473 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 1474 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 1475 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 1476 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 1477 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 1478 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 1479 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 1480 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 1481 do {\ 1482 HWIO_INTLOCK(); \ 1483 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 1484 HWIO_INTFREE();\ 1485 } while (0) 1486 1487 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1488 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1489 1490 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 1491 1492 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1493 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1494 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 1495 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 1496 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 1497 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 1498 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 1499 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 1500 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 1501 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 1502 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 1503 do {\ 1504 HWIO_INTLOCK(); \ 1505 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 1506 HWIO_INTFREE();\ 1507 } while (0) 1508 1509 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1510 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1511 1512 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1513 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1514 1515 //// Register REO_R0_REO_CMD_RING_ID //// 1516 1517 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x000000ec) 1518 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x000000ec) 1519 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 1520 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 1521 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 1522 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 1523 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 1524 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 1525 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 1526 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 1527 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 1528 do {\ 1529 HWIO_INTLOCK(); \ 1530 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 1531 HWIO_INTFREE();\ 1532 } while (0) 1533 1534 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1535 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 1536 1537 //// Register REO_R0_REO_CMD_RING_STATUS //// 1538 1539 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000000f0) 1540 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000000f0) 1541 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 1542 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 1543 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 1544 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 1545 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 1546 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 1547 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 1548 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 1549 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 1550 do {\ 1551 HWIO_INTLOCK(); \ 1552 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 1553 HWIO_INTFREE();\ 1554 } while (0) 1555 1556 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1557 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1558 1559 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1560 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1561 1562 //// Register REO_R0_REO_CMD_RING_MISC //// 1563 1564 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000000f4) 1565 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000000f4) 1566 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff 1567 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 1568 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 1569 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 1570 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 1571 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 1572 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 1573 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 1574 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 1575 do {\ 1576 HWIO_INTLOCK(); \ 1577 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 1578 HWIO_INTFREE();\ 1579 } while (0) 1580 1581 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1582 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 1583 1584 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1585 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1586 1587 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1588 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1589 1590 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1591 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1592 1593 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1594 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 1595 1596 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1597 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1598 1599 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1600 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1601 1602 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1603 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1604 1605 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1606 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 1607 1608 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1609 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1610 1611 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1612 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1613 1614 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 1615 1616 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1617 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1618 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 1619 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 1620 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 1621 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 1622 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 1623 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 1624 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 1625 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 1626 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1627 do {\ 1628 HWIO_INTLOCK(); \ 1629 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 1630 HWIO_INTFREE();\ 1631 } while (0) 1632 1633 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1634 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1635 1636 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 1637 1638 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1639 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1640 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 1641 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 1642 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 1643 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 1644 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 1645 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 1646 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 1647 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 1648 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1649 do {\ 1650 HWIO_INTLOCK(); \ 1651 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 1652 HWIO_INTFREE();\ 1653 } while (0) 1654 1655 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1656 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1657 1658 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 1659 1660 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1661 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1662 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1663 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1664 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1665 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1666 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1667 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1668 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1669 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1670 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1671 do {\ 1672 HWIO_INTLOCK(); \ 1673 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1674 HWIO_INTFREE();\ 1675 } while (0) 1676 1677 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1678 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1679 1680 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1681 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1682 1683 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1684 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1685 1686 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 1687 1688 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1689 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1690 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1691 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1692 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1693 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1694 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1695 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1696 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1697 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1698 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1699 do {\ 1700 HWIO_INTLOCK(); \ 1701 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1702 HWIO_INTFREE();\ 1703 } while (0) 1704 1705 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1706 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1707 1708 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 1709 1710 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1711 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1712 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1713 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 1714 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 1715 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 1716 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1717 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1718 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1719 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1720 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1721 do {\ 1722 HWIO_INTLOCK(); \ 1723 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 1724 HWIO_INTFREE();\ 1725 } while (0) 1726 1727 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1728 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1729 1730 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1731 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1732 1733 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1734 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1735 1736 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 1737 1738 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1739 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1740 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1741 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1742 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1743 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1744 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1745 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1746 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1747 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1748 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1749 do {\ 1750 HWIO_INTLOCK(); \ 1751 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1752 HWIO_INTFREE();\ 1753 } while (0) 1754 1755 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1756 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1757 1758 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 1759 1760 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1761 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1762 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1763 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1764 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1765 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1766 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1767 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1768 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1769 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1770 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1771 do {\ 1772 HWIO_INTLOCK(); \ 1773 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1774 HWIO_INTFREE();\ 1775 } while (0) 1776 1777 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1778 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1779 1780 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 1781 1782 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1783 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1784 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1785 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1786 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1787 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1788 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1789 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1790 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1791 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1792 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1793 do {\ 1794 HWIO_INTLOCK(); \ 1795 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1796 HWIO_INTFREE();\ 1797 } while (0) 1798 1799 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1800 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1801 1802 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1803 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1804 1805 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 1806 1807 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1808 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1809 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1810 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 1811 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 1812 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 1813 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 1814 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 1815 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 1816 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 1817 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1818 do {\ 1819 HWIO_INTLOCK(); \ 1820 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 1821 HWIO_INTFREE();\ 1822 } while (0) 1823 1824 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1825 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1826 1827 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 1828 1829 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1830 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1831 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1832 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 1833 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 1834 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 1835 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 1836 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 1837 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 1838 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 1839 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1840 do {\ 1841 HWIO_INTLOCK(); \ 1842 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 1843 HWIO_INTFREE();\ 1844 } while (0) 1845 1846 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1847 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1848 1849 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1850 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1851 1852 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 1853 1854 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1855 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1856 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 1857 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 1858 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 1859 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 1860 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 1861 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 1862 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 1863 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 1864 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 1865 do {\ 1866 HWIO_INTLOCK(); \ 1867 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 1868 HWIO_INTFREE();\ 1869 } while (0) 1870 1871 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1872 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 1873 1874 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 1875 1876 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1877 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1878 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1879 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 1880 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 1881 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 1882 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1883 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1884 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1885 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1886 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1887 do {\ 1888 HWIO_INTLOCK(); \ 1889 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 1890 HWIO_INTFREE();\ 1891 } while (0) 1892 1893 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1894 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1895 1896 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 1897 1898 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1899 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1900 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 1901 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 1902 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 1903 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 1904 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 1905 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 1906 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 1907 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 1908 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 1909 do {\ 1910 HWIO_INTLOCK(); \ 1911 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 1912 HWIO_INTFREE();\ 1913 } while (0) 1914 1915 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1916 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1917 1918 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 1919 1920 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1921 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1922 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 1923 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 1924 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 1925 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 1926 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 1927 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 1928 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 1929 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 1930 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 1931 do {\ 1932 HWIO_INTLOCK(); \ 1933 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 1934 HWIO_INTFREE();\ 1935 } while (0) 1936 1937 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1938 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1939 1940 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1941 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1942 1943 //// Register REO_R0_SW2REO_RING_ID //// 1944 1945 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x00000144) 1946 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x00000144) 1947 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 1948 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 1949 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 1950 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 1951 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 1952 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 1953 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 1954 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 1955 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 1956 do {\ 1957 HWIO_INTLOCK(); \ 1958 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 1959 HWIO_INTFREE();\ 1960 } while (0) 1961 1962 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1963 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 1964 1965 //// Register REO_R0_SW2REO_RING_STATUS //// 1966 1967 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x00000148) 1968 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x00000148) 1969 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 1970 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 1971 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 1972 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 1973 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 1974 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 1975 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 1976 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 1977 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 1978 do {\ 1979 HWIO_INTLOCK(); \ 1980 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 1981 HWIO_INTFREE();\ 1982 } while (0) 1983 1984 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1985 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1986 1987 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1988 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1989 1990 //// Register REO_R0_SW2REO_RING_MISC //// 1991 1992 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x0000014c) 1993 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x0000014c) 1994 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff 1995 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 1996 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 1997 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 1998 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 1999 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 2000 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 2001 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 2002 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 2003 do {\ 2004 HWIO_INTLOCK(); \ 2005 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 2006 HWIO_INTFREE();\ 2007 } while (0) 2008 2009 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2010 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe 2011 2012 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2013 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2014 2015 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2016 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2017 2018 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2019 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2020 2021 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2022 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 2023 2024 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2025 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2026 2027 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2028 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2029 2030 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2031 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2032 2033 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2034 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2035 2036 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2037 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2038 2039 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2040 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2041 2042 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2043 2044 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 2045 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 2046 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2047 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2048 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2049 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2050 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2051 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2052 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2053 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2054 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2055 do {\ 2056 HWIO_INTLOCK(); \ 2057 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2058 HWIO_INTFREE();\ 2059 } while (0) 2060 2061 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2062 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2063 2064 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2065 2066 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 2067 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 2068 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2069 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2070 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2071 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2072 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2073 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2074 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2075 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2076 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2077 do {\ 2078 HWIO_INTLOCK(); \ 2079 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2080 HWIO_INTFREE();\ 2081 } while (0) 2082 2083 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2084 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2085 2086 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2087 2088 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2089 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2090 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2091 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2092 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2093 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2094 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2095 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2096 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2097 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2098 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2099 do {\ 2100 HWIO_INTLOCK(); \ 2101 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2102 HWIO_INTFREE();\ 2103 } while (0) 2104 2105 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2106 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2107 2108 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2109 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2110 2111 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2112 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2113 2114 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2115 2116 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2117 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2118 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2119 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2120 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2121 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2122 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2123 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2124 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2125 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2126 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2127 do {\ 2128 HWIO_INTLOCK(); \ 2129 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2130 HWIO_INTFREE();\ 2131 } while (0) 2132 2133 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2134 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2135 2136 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2137 2138 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2139 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2140 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2141 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2142 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2143 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2144 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2145 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2146 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2147 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2148 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2149 do {\ 2150 HWIO_INTLOCK(); \ 2151 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2152 HWIO_INTFREE();\ 2153 } while (0) 2154 2155 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2156 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2157 2158 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2159 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2160 2161 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2162 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2163 2164 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2165 2166 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2167 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2168 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2169 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2170 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2171 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2172 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2173 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2174 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2175 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2176 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2177 do {\ 2178 HWIO_INTLOCK(); \ 2179 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2180 HWIO_INTFREE();\ 2181 } while (0) 2182 2183 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2184 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2185 2186 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2187 2188 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2189 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2190 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2191 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2192 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2193 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2194 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2195 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2196 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2197 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2198 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2199 do {\ 2200 HWIO_INTLOCK(); \ 2201 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2202 HWIO_INTFREE();\ 2203 } while (0) 2204 2205 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2206 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2207 2208 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2209 2210 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2211 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2212 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2213 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2214 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2215 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2216 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2217 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2218 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2219 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2220 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2221 do {\ 2222 HWIO_INTLOCK(); \ 2223 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2224 HWIO_INTFREE();\ 2225 } while (0) 2226 2227 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2228 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2229 2230 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2231 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2232 2233 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 2234 2235 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184) 2236 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184) 2237 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2238 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 2239 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 2240 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 2241 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 2242 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 2243 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 2244 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 2245 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2246 do {\ 2247 HWIO_INTLOCK(); \ 2248 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 2249 HWIO_INTFREE();\ 2250 } while (0) 2251 2252 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2253 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2254 2255 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 2256 2257 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188) 2258 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188) 2259 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2260 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 2261 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 2262 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 2263 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 2264 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 2265 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 2266 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 2267 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2268 do {\ 2269 HWIO_INTLOCK(); \ 2270 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 2271 HWIO_INTFREE();\ 2272 } while (0) 2273 2274 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2275 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2276 2277 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2278 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2279 2280 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 2281 2282 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000018c) 2283 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000018c) 2284 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 2285 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 2286 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 2287 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 2288 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 2289 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 2290 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 2291 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 2292 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 2293 do {\ 2294 HWIO_INTLOCK(); \ 2295 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 2296 HWIO_INTFREE();\ 2297 } while (0) 2298 2299 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2300 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 2301 2302 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 2303 2304 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2305 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2306 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2307 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 2308 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 2309 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 2310 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2311 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2312 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2313 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2314 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2315 do {\ 2316 HWIO_INTLOCK(); \ 2317 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 2318 HWIO_INTFREE();\ 2319 } while (0) 2320 2321 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2322 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2323 2324 //// Register REO_R0_SW2REO1_RING_BASE_LSB //// 2325 2326 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2327 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2328 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff 2329 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0 2330 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ 2331 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK) 2332 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ 2333 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) 2334 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \ 2335 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val) 2336 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 2337 do {\ 2338 HWIO_INTLOCK(); \ 2339 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \ 2340 HWIO_INTFREE();\ 2341 } while (0) 2342 2343 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2344 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2345 2346 //// Register REO_R0_SW2REO1_RING_BASE_MSB //// 2347 2348 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2349 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2350 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff 2351 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0 2352 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ 2353 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK) 2354 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ 2355 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) 2356 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \ 2357 out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val) 2358 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 2359 do {\ 2360 HWIO_INTLOCK(); \ 2361 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \ 2362 HWIO_INTFREE();\ 2363 } while (0) 2364 2365 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2366 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2367 2368 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2369 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2370 2371 //// Register REO_R0_SW2REO1_RING_ID //// 2372 2373 #define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000019c) 2374 #define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000019c) 2375 #define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff 2376 #define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0 2377 #define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ 2378 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK) 2379 #define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ 2380 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) 2381 #define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \ 2382 out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val) 2383 #define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ 2384 do {\ 2385 HWIO_INTLOCK(); \ 2386 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \ 2387 HWIO_INTFREE();\ 2388 } while (0) 2389 2390 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2391 #define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 2392 2393 //// Register REO_R0_SW2REO1_RING_STATUS //// 2394 2395 #define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x000001a0) 2396 #define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x000001a0) 2397 #define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff 2398 #define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0 2399 #define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ 2400 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK) 2401 #define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ 2402 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) 2403 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \ 2404 out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val) 2405 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ 2406 do {\ 2407 HWIO_INTLOCK(); \ 2408 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \ 2409 HWIO_INTFREE();\ 2410 } while (0) 2411 2412 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2413 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2414 2415 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2416 #define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2417 2418 //// Register REO_R0_SW2REO1_RING_MISC //// 2419 2420 #define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x000001a4) 2421 #define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x000001a4) 2422 #define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff 2423 #define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0 2424 #define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ 2425 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK) 2426 #define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ 2427 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) 2428 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \ 2429 out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val) 2430 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ 2431 do {\ 2432 HWIO_INTLOCK(); \ 2433 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \ 2434 HWIO_INTFREE();\ 2435 } while (0) 2436 2437 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2438 #define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2439 2440 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2441 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2442 2443 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2444 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2445 2446 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2447 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2448 2449 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2450 #define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2451 2452 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2453 #define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2454 2455 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2456 #define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2457 2458 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2459 #define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2460 2461 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2462 #define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 2463 2464 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2465 #define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2466 2467 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2468 #define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2469 2470 //// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB //// 2471 2472 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2473 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2474 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2475 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0 2476 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ 2477 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK) 2478 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 2479 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 2480 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 2481 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 2482 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2483 do {\ 2484 HWIO_INTLOCK(); \ 2485 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \ 2486 HWIO_INTFREE();\ 2487 } while (0) 2488 2489 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2490 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2491 2492 //// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB //// 2493 2494 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2495 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2496 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2497 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0 2498 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ 2499 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK) 2500 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 2501 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 2502 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 2503 out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 2504 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2505 do {\ 2506 HWIO_INTLOCK(); \ 2507 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \ 2508 HWIO_INTFREE();\ 2509 } while (0) 2510 2511 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2512 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2513 2514 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 2515 2516 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2517 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2518 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2519 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2520 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2521 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2522 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2523 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2524 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2525 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2526 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2527 do {\ 2528 HWIO_INTLOCK(); \ 2529 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2530 HWIO_INTFREE();\ 2531 } while (0) 2532 2533 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2534 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2535 2536 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2537 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2538 2539 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2540 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2541 2542 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 2543 2544 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2545 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2546 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2547 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2548 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2549 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2550 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2551 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2552 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2553 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2554 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2555 do {\ 2556 HWIO_INTLOCK(); \ 2557 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2558 HWIO_INTFREE();\ 2559 } while (0) 2560 2561 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2562 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2563 2564 //// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS //// 2565 2566 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2567 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2568 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2569 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 2570 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 2571 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK) 2572 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2573 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2574 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2575 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2576 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2577 do {\ 2578 HWIO_INTLOCK(); \ 2579 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 2580 HWIO_INTFREE();\ 2581 } while (0) 2582 2583 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2584 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2585 2586 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2587 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2588 2589 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2590 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2591 2592 //// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER //// 2593 2594 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2595 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2596 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2597 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2598 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2599 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2600 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2601 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2602 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2603 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2604 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2605 do {\ 2606 HWIO_INTLOCK(); \ 2607 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2608 HWIO_INTFREE();\ 2609 } while (0) 2610 2611 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2612 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2613 2614 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER //// 2615 2616 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2617 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2618 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2619 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2620 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2621 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2622 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2623 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2624 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2625 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2626 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2627 do {\ 2628 HWIO_INTLOCK(); \ 2629 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2630 HWIO_INTFREE();\ 2631 } while (0) 2632 2633 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2634 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2635 2636 //// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS //// 2637 2638 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2639 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2640 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2641 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2642 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2643 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2644 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2645 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2646 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2647 out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2648 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2649 do {\ 2650 HWIO_INTLOCK(); \ 2651 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2652 HWIO_INTFREE();\ 2653 } while (0) 2654 2655 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2656 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2657 2658 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2659 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2660 2661 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB //// 2662 2663 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2664 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2665 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2666 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0 2667 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ 2668 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK) 2669 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 2670 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 2671 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 2672 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 2673 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2674 do {\ 2675 HWIO_INTLOCK(); \ 2676 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 2677 HWIO_INTFREE();\ 2678 } while (0) 2679 2680 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2681 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2682 2683 //// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB //// 2684 2685 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2686 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2687 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2688 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0 2689 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ 2690 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK) 2691 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 2692 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 2693 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 2694 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 2695 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2696 do {\ 2697 HWIO_INTLOCK(); \ 2698 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 2699 HWIO_INTFREE();\ 2700 } while (0) 2701 2702 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2703 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2704 2705 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2706 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2707 2708 //// Register REO_R0_SW2REO1_RING_MSI1_DATA //// 2709 2710 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2711 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2712 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff 2713 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0 2714 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ 2715 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK) 2716 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ 2717 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) 2718 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \ 2719 out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val) 2720 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 2721 do {\ 2722 HWIO_INTLOCK(); \ 2723 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \ 2724 HWIO_INTFREE();\ 2725 } while (0) 2726 2727 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2728 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 2729 2730 //// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET //// 2731 2732 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2733 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2734 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2735 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 2736 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 2737 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK) 2738 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2739 in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2740 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2741 out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2742 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2743 do {\ 2744 HWIO_INTLOCK(); \ 2745 out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 2746 HWIO_INTFREE();\ 2747 } while (0) 2748 2749 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2750 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2751 2752 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 2753 2754 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2755 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2756 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 2757 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 2758 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 2759 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 2760 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 2761 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 2762 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 2763 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 2764 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 2765 do {\ 2766 HWIO_INTLOCK(); \ 2767 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 2768 HWIO_INTFREE();\ 2769 } while (0) 2770 2771 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2772 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2773 2774 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 2775 2776 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2777 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2778 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff 2779 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 2780 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 2781 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 2782 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 2783 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 2784 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 2785 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 2786 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 2787 do {\ 2788 HWIO_INTLOCK(); \ 2789 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 2790 HWIO_INTFREE();\ 2791 } while (0) 2792 2793 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2794 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2795 2796 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2797 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2798 2799 //// Register REO_R0_REO2SW1_RING_ID //// 2800 2801 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000001f4) 2802 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000001f4) 2803 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 2804 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 2805 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 2806 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 2807 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 2808 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 2809 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 2810 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 2811 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 2812 do {\ 2813 HWIO_INTLOCK(); \ 2814 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 2815 HWIO_INTFREE();\ 2816 } while (0) 2817 2818 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 2819 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 2820 2821 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2822 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 2823 2824 //// Register REO_R0_REO2SW1_RING_STATUS //// 2825 2826 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000001f8) 2827 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000001f8) 2828 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 2829 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 2830 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 2831 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 2832 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 2833 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 2834 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 2835 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 2836 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 2837 do {\ 2838 HWIO_INTLOCK(); \ 2839 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 2840 HWIO_INTFREE();\ 2841 } while (0) 2842 2843 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2844 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2845 2846 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2847 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2848 2849 //// Register REO_R0_REO2SW1_RING_MISC //// 2850 2851 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000001fc) 2852 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000001fc) 2853 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff 2854 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 2855 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 2856 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 2857 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 2858 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 2859 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 2860 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 2861 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 2862 do {\ 2863 HWIO_INTLOCK(); \ 2864 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 2865 HWIO_INTFREE();\ 2866 } while (0) 2867 2868 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 2869 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 2870 2871 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2872 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2873 2874 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2875 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2876 2877 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2878 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2879 2880 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2881 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2882 2883 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2884 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2885 2886 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2887 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2888 2889 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2890 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2891 2892 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2893 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2894 2895 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2896 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 2897 2898 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2899 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2900 2901 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2902 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2903 2904 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 2905 2906 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000200) 2907 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000200) 2908 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 2909 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 2910 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 2911 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 2912 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 2913 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 2914 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 2915 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 2916 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 2917 do {\ 2918 HWIO_INTLOCK(); \ 2919 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 2920 HWIO_INTFREE();\ 2921 } while (0) 2922 2923 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 2924 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 2925 2926 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 2927 2928 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000204) 2929 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000204) 2930 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 2931 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 2932 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 2933 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 2934 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 2935 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 2936 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 2937 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 2938 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 2939 do {\ 2940 HWIO_INTLOCK(); \ 2941 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 2942 HWIO_INTFREE();\ 2943 } while (0) 2944 2945 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 2946 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 2947 2948 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 2949 2950 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000210) 2951 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000210) 2952 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 2953 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 2954 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 2955 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 2956 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 2957 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 2958 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 2959 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 2960 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 2961 do {\ 2962 HWIO_INTLOCK(); \ 2963 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 2964 HWIO_INTFREE();\ 2965 } while (0) 2966 2967 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2968 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2969 2970 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 2971 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 2972 2973 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2974 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2975 2976 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 2977 2978 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000214) 2979 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000214) 2980 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 2981 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 2982 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 2983 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 2984 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 2985 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 2986 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 2987 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 2988 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 2989 do {\ 2990 HWIO_INTLOCK(); \ 2991 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 2992 HWIO_INTFREE();\ 2993 } while (0) 2994 2995 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2996 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2997 2998 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 2999 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3000 3001 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3002 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3003 3004 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 3005 3006 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000218) 3007 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000218) 3008 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3009 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3010 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3011 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3012 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3013 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3014 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3015 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3016 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3017 do {\ 3018 HWIO_INTLOCK(); \ 3019 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3020 HWIO_INTFREE();\ 3021 } while (0) 3022 3023 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3024 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3025 3026 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3027 3028 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 3029 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 3030 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3031 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3032 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3033 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3034 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3035 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3036 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3037 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3038 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3039 do {\ 3040 HWIO_INTLOCK(); \ 3041 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3042 HWIO_INTFREE();\ 3043 } while (0) 3044 3045 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3046 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3047 3048 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3049 3050 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 3051 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 3052 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3053 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3054 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3055 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3056 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3057 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3058 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3059 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3060 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3061 do {\ 3062 HWIO_INTLOCK(); \ 3063 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3064 HWIO_INTFREE();\ 3065 } while (0) 3066 3067 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3068 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3069 3070 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3071 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3072 3073 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3074 3075 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 3076 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 3077 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3078 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3079 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3080 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3081 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3082 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3083 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3084 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3085 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3086 do {\ 3087 HWIO_INTLOCK(); \ 3088 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3089 HWIO_INTFREE();\ 3090 } while (0) 3091 3092 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3093 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3094 3095 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3096 3097 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 3098 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 3099 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3100 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3101 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3102 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3103 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3104 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3105 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3106 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3107 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3108 do {\ 3109 HWIO_INTLOCK(); \ 3110 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3111 HWIO_INTFREE();\ 3112 } while (0) 3113 3114 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3115 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3116 3117 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3118 3119 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3120 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3121 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3122 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3123 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3124 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3125 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3126 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3127 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3128 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3129 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3130 do {\ 3131 HWIO_INTLOCK(); \ 3132 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3133 HWIO_INTFREE();\ 3134 } while (0) 3135 3136 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3137 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3138 3139 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3140 3141 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3142 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3143 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff 3144 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3145 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3146 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3147 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3148 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3149 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3150 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3151 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3152 do {\ 3153 HWIO_INTLOCK(); \ 3154 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3155 HWIO_INTFREE();\ 3156 } while (0) 3157 3158 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3159 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3160 3161 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3162 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3163 3164 //// Register REO_R0_REO2SW2_RING_ID //// 3165 3166 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x0000024c) 3167 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x0000024c) 3168 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3169 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3170 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3171 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3172 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3173 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3174 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3175 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3176 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3177 do {\ 3178 HWIO_INTLOCK(); \ 3179 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3180 HWIO_INTFREE();\ 3181 } while (0) 3182 3183 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3184 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3185 3186 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3187 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3188 3189 //// Register REO_R0_REO2SW2_RING_STATUS //// 3190 3191 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000250) 3192 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000250) 3193 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3194 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3195 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3196 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3197 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3198 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3199 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3200 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3201 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3202 do {\ 3203 HWIO_INTLOCK(); \ 3204 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3205 HWIO_INTFREE();\ 3206 } while (0) 3207 3208 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3209 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3210 3211 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3212 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3213 3214 //// Register REO_R0_REO2SW2_RING_MISC //// 3215 3216 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000254) 3217 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000254) 3218 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff 3219 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 3220 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 3221 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 3222 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 3223 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 3224 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 3225 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 3226 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 3227 do {\ 3228 HWIO_INTLOCK(); \ 3229 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 3230 HWIO_INTFREE();\ 3231 } while (0) 3232 3233 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3234 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 3235 3236 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3237 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3238 3239 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3240 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3241 3242 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3243 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3244 3245 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3246 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3247 3248 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3249 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3250 3251 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3252 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3253 3254 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3255 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3256 3257 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3258 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3259 3260 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3261 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 3262 3263 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3264 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3265 3266 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3267 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3268 3269 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 3270 3271 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) 3272 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) 3273 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3274 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 3275 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 3276 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 3277 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 3278 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 3279 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 3280 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 3281 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3282 do {\ 3283 HWIO_INTLOCK(); \ 3284 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 3285 HWIO_INTFREE();\ 3286 } while (0) 3287 3288 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3289 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3290 3291 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 3292 3293 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) 3294 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) 3295 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3296 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 3297 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 3298 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 3299 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 3300 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 3301 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 3302 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 3303 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3304 do {\ 3305 HWIO_INTLOCK(); \ 3306 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 3307 HWIO_INTFREE();\ 3308 } while (0) 3309 3310 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3311 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3312 3313 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 3314 3315 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) 3316 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) 3317 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3318 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 3319 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 3320 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 3321 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3322 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3323 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3324 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3325 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3326 do {\ 3327 HWIO_INTLOCK(); \ 3328 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3329 HWIO_INTFREE();\ 3330 } while (0) 3331 3332 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3333 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3334 3335 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3336 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3337 3338 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3339 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3340 3341 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 3342 3343 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) 3344 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) 3345 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3346 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 3347 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 3348 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 3349 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3350 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3351 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3352 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3353 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3354 do {\ 3355 HWIO_INTLOCK(); \ 3356 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3357 HWIO_INTFREE();\ 3358 } while (0) 3359 3360 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3361 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3362 3363 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3364 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3365 3366 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3367 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3368 3369 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 3370 3371 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) 3372 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) 3373 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3374 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 3375 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3376 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 3377 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3378 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3379 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3380 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3381 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3382 do {\ 3383 HWIO_INTLOCK(); \ 3384 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3385 HWIO_INTFREE();\ 3386 } while (0) 3387 3388 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3389 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3390 3391 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 3392 3393 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3394 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3395 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3396 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 3397 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 3398 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 3399 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 3400 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 3401 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 3402 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 3403 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3404 do {\ 3405 HWIO_INTLOCK(); \ 3406 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 3407 HWIO_INTFREE();\ 3408 } while (0) 3409 3410 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3411 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3412 3413 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 3414 3415 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3416 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3417 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3418 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 3419 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 3420 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 3421 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 3422 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 3423 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 3424 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 3425 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3426 do {\ 3427 HWIO_INTLOCK(); \ 3428 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 3429 HWIO_INTFREE();\ 3430 } while (0) 3431 3432 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3433 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3434 3435 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3436 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3437 3438 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 3439 3440 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3441 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3442 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 3443 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 3444 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 3445 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 3446 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 3447 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 3448 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 3449 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 3450 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 3451 do {\ 3452 HWIO_INTLOCK(); \ 3453 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 3454 HWIO_INTFREE();\ 3455 } while (0) 3456 3457 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3458 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 3459 3460 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 3461 3462 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3463 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3464 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3465 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 3466 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 3467 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 3468 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3469 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3470 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3471 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3472 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3473 do {\ 3474 HWIO_INTLOCK(); \ 3475 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 3476 HWIO_INTFREE();\ 3477 } while (0) 3478 3479 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3480 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3481 3482 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 3483 3484 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3485 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3486 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 3487 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 3488 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 3489 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 3490 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 3491 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 3492 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 3493 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 3494 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 3495 do {\ 3496 HWIO_INTLOCK(); \ 3497 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 3498 HWIO_INTFREE();\ 3499 } while (0) 3500 3501 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3502 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3503 3504 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 3505 3506 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3507 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3508 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff 3509 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 3510 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 3511 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 3512 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 3513 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 3514 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 3515 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 3516 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 3517 do {\ 3518 HWIO_INTLOCK(); \ 3519 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 3520 HWIO_INTFREE();\ 3521 } while (0) 3522 3523 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3524 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3525 3526 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3527 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3528 3529 //// Register REO_R0_REO2SW3_RING_ID //// 3530 3531 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002a4) 3532 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002a4) 3533 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 3534 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 3535 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 3536 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 3537 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 3538 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 3539 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 3540 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 3541 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 3542 do {\ 3543 HWIO_INTLOCK(); \ 3544 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 3545 HWIO_INTFREE();\ 3546 } while (0) 3547 3548 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 3549 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 3550 3551 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3552 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 3553 3554 //// Register REO_R0_REO2SW3_RING_STATUS //// 3555 3556 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x000002a8) 3557 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x000002a8) 3558 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 3559 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 3560 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 3561 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 3562 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 3563 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 3564 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 3565 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 3566 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 3567 do {\ 3568 HWIO_INTLOCK(); \ 3569 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 3570 HWIO_INTFREE();\ 3571 } while (0) 3572 3573 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3574 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3575 3576 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3577 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3578 3579 //// Register REO_R0_REO2SW3_RING_MISC //// 3580 3581 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x000002ac) 3582 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x000002ac) 3583 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff 3584 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 3585 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 3586 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 3587 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 3588 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 3589 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 3590 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 3591 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 3592 do {\ 3593 HWIO_INTLOCK(); \ 3594 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 3595 HWIO_INTFREE();\ 3596 } while (0) 3597 3598 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3599 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 3600 3601 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3602 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe 3603 3604 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3605 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3606 3607 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3608 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3609 3610 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3611 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3612 3613 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3614 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 3615 3616 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3617 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3618 3619 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3620 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3621 3622 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3623 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3624 3625 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3626 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 3627 3628 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3629 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3630 3631 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3632 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3633 3634 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 3635 3636 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3637 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3638 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 3639 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 3640 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 3641 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 3642 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 3643 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 3644 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 3645 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 3646 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3647 do {\ 3648 HWIO_INTLOCK(); \ 3649 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 3650 HWIO_INTFREE();\ 3651 } while (0) 3652 3653 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3654 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3655 3656 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 3657 3658 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3659 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3660 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 3661 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 3662 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 3663 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 3664 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 3665 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 3666 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 3667 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 3668 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3669 do {\ 3670 HWIO_INTLOCK(); \ 3671 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 3672 HWIO_INTFREE();\ 3673 } while (0) 3674 3675 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3676 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3677 3678 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 3679 3680 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3681 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3682 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3683 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 3684 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 3685 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 3686 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3687 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3688 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3689 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3690 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3691 do {\ 3692 HWIO_INTLOCK(); \ 3693 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 3694 HWIO_INTFREE();\ 3695 } while (0) 3696 3697 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3698 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3699 3700 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3701 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3702 3703 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3704 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3705 3706 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 3707 3708 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3709 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3710 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3711 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 3712 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 3713 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 3714 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3715 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3716 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3717 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3718 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3719 do {\ 3720 HWIO_INTLOCK(); \ 3721 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 3722 HWIO_INTFREE();\ 3723 } while (0) 3724 3725 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3726 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3727 3728 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3729 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3730 3731 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3732 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3733 3734 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 3735 3736 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3737 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3738 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3739 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 3740 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3741 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 3742 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3743 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3744 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3745 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3746 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3747 do {\ 3748 HWIO_INTLOCK(); \ 3749 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3750 HWIO_INTFREE();\ 3751 } while (0) 3752 3753 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3754 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3755 3756 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 3757 3758 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3759 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3760 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3761 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 3762 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 3763 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 3764 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 3765 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 3766 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 3767 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 3768 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3769 do {\ 3770 HWIO_INTLOCK(); \ 3771 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 3772 HWIO_INTFREE();\ 3773 } while (0) 3774 3775 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3776 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3777 3778 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 3779 3780 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3781 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3782 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3783 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 3784 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 3785 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 3786 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 3787 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 3788 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 3789 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 3790 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3791 do {\ 3792 HWIO_INTLOCK(); \ 3793 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 3794 HWIO_INTFREE();\ 3795 } while (0) 3796 3797 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3798 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3799 3800 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3801 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3802 3803 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 3804 3805 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3806 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3807 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 3808 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 3809 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 3810 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 3811 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 3812 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 3813 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 3814 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 3815 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 3816 do {\ 3817 HWIO_INTLOCK(); \ 3818 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 3819 HWIO_INTFREE();\ 3820 } while (0) 3821 3822 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3823 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 3824 3825 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 3826 3827 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3828 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3829 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3830 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 3831 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 3832 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 3833 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3834 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3835 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3836 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3837 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3838 do {\ 3839 HWIO_INTLOCK(); \ 3840 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 3841 HWIO_INTFREE();\ 3842 } while (0) 3843 3844 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3845 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3846 3847 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 3848 3849 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3850 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3851 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 3852 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 3853 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 3854 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 3855 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 3856 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 3857 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 3858 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 3859 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 3860 do {\ 3861 HWIO_INTLOCK(); \ 3862 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 3863 HWIO_INTFREE();\ 3864 } while (0) 3865 3866 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3867 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3868 3869 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 3870 3871 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3872 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3873 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff 3874 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 3875 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 3876 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 3877 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 3878 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 3879 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 3880 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 3881 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 3882 do {\ 3883 HWIO_INTLOCK(); \ 3884 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 3885 HWIO_INTFREE();\ 3886 } while (0) 3887 3888 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 3889 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3890 3891 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3892 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3893 3894 //// Register REO_R0_REO2SW4_RING_ID //// 3895 3896 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000002fc) 3897 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000002fc) 3898 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 3899 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 3900 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 3901 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 3902 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 3903 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 3904 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 3905 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 3906 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 3907 do {\ 3908 HWIO_INTLOCK(); \ 3909 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 3910 HWIO_INTFREE();\ 3911 } while (0) 3912 3913 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 3914 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 3915 3916 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3917 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 3918 3919 //// Register REO_R0_REO2SW4_RING_STATUS //// 3920 3921 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000300) 3922 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000300) 3923 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 3924 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 3925 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 3926 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 3927 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 3928 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 3929 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 3930 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 3931 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 3932 do {\ 3933 HWIO_INTLOCK(); \ 3934 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 3935 HWIO_INTFREE();\ 3936 } while (0) 3937 3938 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3939 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3940 3941 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3942 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3943 3944 //// Register REO_R0_REO2SW4_RING_MISC //// 3945 3946 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x00000304) 3947 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x00000304) 3948 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff 3949 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 3950 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 3951 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 3952 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 3953 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 3954 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 3955 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 3956 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 3957 do {\ 3958 HWIO_INTLOCK(); \ 3959 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 3960 HWIO_INTFREE();\ 3961 } while (0) 3962 3963 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3964 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 3965 3966 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3967 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe 3968 3969 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3970 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3971 3972 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3973 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3974 3975 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3976 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3977 3978 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3979 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 3980 3981 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3982 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3983 3984 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3985 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3986 3987 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3988 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3989 3990 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3991 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 3992 3993 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3994 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3995 3996 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3997 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3998 3999 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 4000 4001 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 4002 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 4003 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 4004 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 4005 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 4006 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 4007 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 4008 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 4009 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 4010 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4011 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4012 do {\ 4013 HWIO_INTLOCK(); \ 4014 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4015 HWIO_INTFREE();\ 4016 } while (0) 4017 4018 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4019 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4020 4021 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4022 4023 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 4024 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 4025 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4026 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4027 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4028 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4029 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4030 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4031 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4032 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4033 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4034 do {\ 4035 HWIO_INTLOCK(); \ 4036 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4037 HWIO_INTFREE();\ 4038 } while (0) 4039 4040 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4041 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4042 4043 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4044 4045 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 4046 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 4047 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4048 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4049 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4050 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4051 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4052 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4053 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4054 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4055 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4056 do {\ 4057 HWIO_INTLOCK(); \ 4058 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4059 HWIO_INTFREE();\ 4060 } while (0) 4061 4062 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4063 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4064 4065 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4066 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4067 4068 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4069 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4070 4071 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4072 4073 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 4074 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 4075 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4076 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4077 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4078 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4079 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4080 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4081 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4082 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4083 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4084 do {\ 4085 HWIO_INTLOCK(); \ 4086 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4087 HWIO_INTFREE();\ 4088 } while (0) 4089 4090 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4091 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4092 4093 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4094 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4095 4096 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4097 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4098 4099 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4100 4101 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 4102 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 4103 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4104 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4105 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4106 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4107 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4108 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4109 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4110 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4111 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4112 do {\ 4113 HWIO_INTLOCK(); \ 4114 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4115 HWIO_INTFREE();\ 4116 } while (0) 4117 4118 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4119 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4120 4121 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4122 4123 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 4124 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 4125 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4126 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4127 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4128 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4129 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4130 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4131 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4132 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4133 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4134 do {\ 4135 HWIO_INTLOCK(); \ 4136 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4137 HWIO_INTFREE();\ 4138 } while (0) 4139 4140 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4141 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4142 4143 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4144 4145 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 4146 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 4147 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4148 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4149 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4150 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4151 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4152 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4153 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4154 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4155 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4156 do {\ 4157 HWIO_INTLOCK(); \ 4158 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4159 HWIO_INTFREE();\ 4160 } while (0) 4161 4162 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4163 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4164 4165 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4166 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4167 4168 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4169 4170 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4171 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4172 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4173 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4174 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4175 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4176 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4177 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4178 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4179 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4180 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4181 do {\ 4182 HWIO_INTLOCK(); \ 4183 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4184 HWIO_INTFREE();\ 4185 } while (0) 4186 4187 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4188 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4189 4190 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4191 4192 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4193 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4194 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4195 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4196 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4197 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4198 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4199 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4200 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4201 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4202 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4203 do {\ 4204 HWIO_INTLOCK(); \ 4205 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4206 HWIO_INTFREE();\ 4207 } while (0) 4208 4209 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4210 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4211 4212 //// Register REO_R0_REO2SW5_RING_BASE_LSB //// 4213 4214 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x) (x+0x0000034c) 4215 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_PHYS(x) (x+0x0000034c) 4216 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK 0xffffffff 4217 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_SHFT 0 4218 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x) \ 4219 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK) 4220 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, mask) \ 4221 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), mask) 4222 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUT(x, val) \ 4223 out_dword( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), val) 4224 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x, mask, val) \ 4225 do {\ 4226 HWIO_INTLOCK(); \ 4227 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x)); \ 4228 HWIO_INTFREE();\ 4229 } while (0) 4230 4231 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4232 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4233 4234 //// Register REO_R0_REO2SW5_RING_BASE_MSB //// 4235 4236 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x) (x+0x00000350) 4237 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_PHYS(x) (x+0x00000350) 4238 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK 0x0fffffff 4239 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_SHFT 0 4240 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x) \ 4241 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK) 4242 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, mask) \ 4243 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), mask) 4244 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUT(x, val) \ 4245 out_dword( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), val) 4246 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x, mask, val) \ 4247 do {\ 4248 HWIO_INTLOCK(); \ 4249 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x)); \ 4250 HWIO_INTFREE();\ 4251 } while (0) 4252 4253 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4254 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4255 4256 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4257 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4258 4259 //// Register REO_R0_REO2SW5_RING_ID //// 4260 4261 #define HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x) (x+0x00000354) 4262 #define HWIO_REO_R0_REO2SW5_RING_ID_PHYS(x) (x+0x00000354) 4263 #define HWIO_REO_R0_REO2SW5_RING_ID_RMSK 0x0000ffff 4264 #define HWIO_REO_R0_REO2SW5_RING_ID_SHFT 0 4265 #define HWIO_REO_R0_REO2SW5_RING_ID_IN(x) \ 4266 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW5_RING_ID_RMSK) 4267 #define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, mask) \ 4268 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), mask) 4269 #define HWIO_REO_R0_REO2SW5_RING_ID_OUT(x, val) \ 4270 out_dword( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), val) 4271 #define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x, mask, val) \ 4272 do {\ 4273 HWIO_INTLOCK(); \ 4274 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_ID_IN(x)); \ 4275 HWIO_INTFREE();\ 4276 } while (0) 4277 4278 #define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_BMSK 0x0000ff00 4279 #define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_SHFT 0x8 4280 4281 #define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4282 #define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_SHFT 0x0 4283 4284 //// Register REO_R0_REO2SW5_RING_STATUS //// 4285 4286 #define HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x) (x+0x00000358) 4287 #define HWIO_REO_R0_REO2SW5_RING_STATUS_PHYS(x) (x+0x00000358) 4288 #define HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK 0xffffffff 4289 #define HWIO_REO_R0_REO2SW5_RING_STATUS_SHFT 0 4290 #define HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x) \ 4291 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK) 4292 #define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, mask) \ 4293 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), mask) 4294 #define HWIO_REO_R0_REO2SW5_RING_STATUS_OUT(x, val) \ 4295 out_dword( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), val) 4296 #define HWIO_REO_R0_REO2SW5_RING_STATUS_OUTM(x, mask, val) \ 4297 do {\ 4298 HWIO_INTLOCK(); \ 4299 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x)); \ 4300 HWIO_INTFREE();\ 4301 } while (0) 4302 4303 #define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4304 #define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4305 4306 #define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4307 #define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4308 4309 //// Register REO_R0_REO2SW5_RING_MISC //// 4310 4311 #define HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x) (x+0x0000035c) 4312 #define HWIO_REO_R0_REO2SW5_RING_MISC_PHYS(x) (x+0x0000035c) 4313 #define HWIO_REO_R0_REO2SW5_RING_MISC_RMSK 0x03ffffff 4314 #define HWIO_REO_R0_REO2SW5_RING_MISC_SHFT 0 4315 #define HWIO_REO_R0_REO2SW5_RING_MISC_IN(x) \ 4316 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MISC_RMSK) 4317 #define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, mask) \ 4318 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), mask) 4319 #define HWIO_REO_R0_REO2SW5_RING_MISC_OUT(x, val) \ 4320 out_dword( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), val) 4321 #define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x, mask, val) \ 4322 do {\ 4323 HWIO_INTLOCK(); \ 4324 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MISC_IN(x)); \ 4325 HWIO_INTFREE();\ 4326 } while (0) 4327 4328 #define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4329 #define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_SHFT 0x16 4330 4331 #define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4332 #define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_SHFT 0xe 4333 4334 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4335 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4336 4337 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4338 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4339 4340 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4341 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4342 4343 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4344 #define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_SHFT 0x6 4345 4346 #define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4347 #define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4348 4349 #define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4350 #define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4351 4352 #define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4353 #define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4354 4355 #define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4356 #define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_SHFT 0x2 4357 4358 #define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4359 #define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4360 4361 #define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4362 #define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4363 4364 //// Register REO_R0_REO2SW5_RING_HP_ADDR_LSB //// 4365 4366 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) 4367 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) 4368 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK 0xffffffff 4369 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_SHFT 0 4370 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x) \ 4371 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK) 4372 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, mask) \ 4373 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), mask) 4374 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUT(x, val) \ 4375 out_dword( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), val) 4376 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4377 do {\ 4378 HWIO_INTLOCK(); \ 4379 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x)); \ 4380 HWIO_INTFREE();\ 4381 } while (0) 4382 4383 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4384 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4385 4386 //// Register REO_R0_REO2SW5_RING_HP_ADDR_MSB //// 4387 4388 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) 4389 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) 4390 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK 0x000000ff 4391 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_SHFT 0 4392 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x) \ 4393 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK) 4394 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, mask) \ 4395 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), mask) 4396 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUT(x, val) \ 4397 out_dword( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), val) 4398 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4399 do {\ 4400 HWIO_INTLOCK(); \ 4401 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x)); \ 4402 HWIO_INTFREE();\ 4403 } while (0) 4404 4405 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4406 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4407 4408 //// Register REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP //// 4409 4410 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) 4411 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) 4412 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4413 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SHFT 0 4414 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x) \ 4415 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK) 4416 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4417 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4418 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4419 out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4420 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4421 do {\ 4422 HWIO_INTLOCK(); \ 4423 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x)); \ 4424 HWIO_INTFREE();\ 4425 } while (0) 4426 4427 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4428 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4429 4430 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4431 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4432 4433 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4434 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4435 4436 //// Register REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS //// 4437 4438 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) 4439 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) 4440 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4441 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_SHFT 0 4442 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x) \ 4443 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK) 4444 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4445 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4446 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4447 out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4448 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4449 do {\ 4450 HWIO_INTLOCK(); \ 4451 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x)); \ 4452 HWIO_INTFREE();\ 4453 } while (0) 4454 4455 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4456 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4457 4458 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4459 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4460 4461 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4462 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4463 4464 //// Register REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER //// 4465 4466 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) 4467 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) 4468 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4469 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_SHFT 0 4470 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4471 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK) 4472 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4473 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4474 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4475 out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4476 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4477 do {\ 4478 HWIO_INTLOCK(); \ 4479 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4480 HWIO_INTFREE();\ 4481 } while (0) 4482 4483 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4484 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4485 4486 //// Register REO_R0_REO2SW5_RING_MSI1_BASE_LSB //// 4487 4488 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) 4489 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) 4490 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4491 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_SHFT 0 4492 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x) \ 4493 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK) 4494 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, mask) \ 4495 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), mask) 4496 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUT(x, val) \ 4497 out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), val) 4498 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4499 do {\ 4500 HWIO_INTLOCK(); \ 4501 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x)); \ 4502 HWIO_INTFREE();\ 4503 } while (0) 4504 4505 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4506 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4507 4508 //// Register REO_R0_REO2SW5_RING_MSI1_BASE_MSB //// 4509 4510 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) 4511 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) 4512 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4513 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_SHFT 0 4514 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x) \ 4515 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK) 4516 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, mask) \ 4517 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), mask) 4518 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUT(x, val) \ 4519 out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), val) 4520 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4521 do {\ 4522 HWIO_INTLOCK(); \ 4523 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x)); \ 4524 HWIO_INTFREE();\ 4525 } while (0) 4526 4527 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4528 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4529 4530 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4531 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4532 4533 //// Register REO_R0_REO2SW5_RING_MSI1_DATA //// 4534 4535 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) 4536 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) 4537 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK 0xffffffff 4538 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_SHFT 0 4539 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x) \ 4540 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK) 4541 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, mask) \ 4542 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), mask) 4543 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUT(x, val) \ 4544 out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), val) 4545 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x, mask, val) \ 4546 do {\ 4547 HWIO_INTLOCK(); \ 4548 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x)); \ 4549 HWIO_INTFREE();\ 4550 } while (0) 4551 4552 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4553 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_SHFT 0x0 4554 4555 //// Register REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET //// 4556 4557 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) 4558 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) 4559 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4560 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_SHFT 0 4561 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x) \ 4562 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK) 4563 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4564 in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4565 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4566 out_dword( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4567 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4568 do {\ 4569 HWIO_INTLOCK(); \ 4570 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x)); \ 4571 HWIO_INTFREE();\ 4572 } while (0) 4573 4574 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4575 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4576 4577 //// Register REO_R0_REO2SW6_RING_BASE_LSB //// 4578 4579 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x) (x+0x000003a4) 4580 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_PHYS(x) (x+0x000003a4) 4581 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK 0xffffffff 4582 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_SHFT 0 4583 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x) \ 4584 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK) 4585 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, mask) \ 4586 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), mask) 4587 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUT(x, val) \ 4588 out_dword( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), val) 4589 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x, mask, val) \ 4590 do {\ 4591 HWIO_INTLOCK(); \ 4592 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x)); \ 4593 HWIO_INTFREE();\ 4594 } while (0) 4595 4596 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4597 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4598 4599 //// Register REO_R0_REO2SW6_RING_BASE_MSB //// 4600 4601 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x) (x+0x000003a8) 4602 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_PHYS(x) (x+0x000003a8) 4603 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK 0x0fffffff 4604 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_SHFT 0 4605 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x) \ 4606 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK) 4607 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, mask) \ 4608 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), mask) 4609 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUT(x, val) \ 4610 out_dword( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), val) 4611 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x, mask, val) \ 4612 do {\ 4613 HWIO_INTLOCK(); \ 4614 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x)); \ 4615 HWIO_INTFREE();\ 4616 } while (0) 4617 4618 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4619 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4620 4621 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4622 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4623 4624 //// Register REO_R0_REO2SW6_RING_ID //// 4625 4626 #define HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x) (x+0x000003ac) 4627 #define HWIO_REO_R0_REO2SW6_RING_ID_PHYS(x) (x+0x000003ac) 4628 #define HWIO_REO_R0_REO2SW6_RING_ID_RMSK 0x0000ffff 4629 #define HWIO_REO_R0_REO2SW6_RING_ID_SHFT 0 4630 #define HWIO_REO_R0_REO2SW6_RING_ID_IN(x) \ 4631 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW6_RING_ID_RMSK) 4632 #define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, mask) \ 4633 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), mask) 4634 #define HWIO_REO_R0_REO2SW6_RING_ID_OUT(x, val) \ 4635 out_dword( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), val) 4636 #define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x, mask, val) \ 4637 do {\ 4638 HWIO_INTLOCK(); \ 4639 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_ID_IN(x)); \ 4640 HWIO_INTFREE();\ 4641 } while (0) 4642 4643 #define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_BMSK 0x0000ff00 4644 #define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_SHFT 0x8 4645 4646 #define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4647 #define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_SHFT 0x0 4648 4649 //// Register REO_R0_REO2SW6_RING_STATUS //// 4650 4651 #define HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x) (x+0x000003b0) 4652 #define HWIO_REO_R0_REO2SW6_RING_STATUS_PHYS(x) (x+0x000003b0) 4653 #define HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK 0xffffffff 4654 #define HWIO_REO_R0_REO2SW6_RING_STATUS_SHFT 0 4655 #define HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x) \ 4656 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK) 4657 #define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, mask) \ 4658 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), mask) 4659 #define HWIO_REO_R0_REO2SW6_RING_STATUS_OUT(x, val) \ 4660 out_dword( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), val) 4661 #define HWIO_REO_R0_REO2SW6_RING_STATUS_OUTM(x, mask, val) \ 4662 do {\ 4663 HWIO_INTLOCK(); \ 4664 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x)); \ 4665 HWIO_INTFREE();\ 4666 } while (0) 4667 4668 #define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4669 #define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4670 4671 #define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4672 #define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4673 4674 //// Register REO_R0_REO2SW6_RING_MISC //// 4675 4676 #define HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x) (x+0x000003b4) 4677 #define HWIO_REO_R0_REO2SW6_RING_MISC_PHYS(x) (x+0x000003b4) 4678 #define HWIO_REO_R0_REO2SW6_RING_MISC_RMSK 0x03ffffff 4679 #define HWIO_REO_R0_REO2SW6_RING_MISC_SHFT 0 4680 #define HWIO_REO_R0_REO2SW6_RING_MISC_IN(x) \ 4681 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MISC_RMSK) 4682 #define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, mask) \ 4683 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), mask) 4684 #define HWIO_REO_R0_REO2SW6_RING_MISC_OUT(x, val) \ 4685 out_dword( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), val) 4686 #define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x, mask, val) \ 4687 do {\ 4688 HWIO_INTLOCK(); \ 4689 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MISC_IN(x)); \ 4690 HWIO_INTFREE();\ 4691 } while (0) 4692 4693 #define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4694 #define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_SHFT 0x16 4695 4696 #define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4697 #define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_SHFT 0xe 4698 4699 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4700 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4701 4702 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4703 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4704 4705 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4706 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4707 4708 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4709 #define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_SHFT 0x6 4710 4711 #define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4712 #define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4713 4714 #define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4715 #define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4716 4717 #define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4718 #define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4719 4720 #define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4721 #define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_SHFT 0x2 4722 4723 #define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4724 #define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4725 4726 #define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4727 #define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4728 4729 //// Register REO_R0_REO2SW6_RING_HP_ADDR_LSB //// 4730 4731 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) 4732 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) 4733 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK 0xffffffff 4734 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_SHFT 0 4735 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x) \ 4736 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK) 4737 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, mask) \ 4738 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), mask) 4739 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUT(x, val) \ 4740 out_dword( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), val) 4741 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4742 do {\ 4743 HWIO_INTLOCK(); \ 4744 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x)); \ 4745 HWIO_INTFREE();\ 4746 } while (0) 4747 4748 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4749 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4750 4751 //// Register REO_R0_REO2SW6_RING_HP_ADDR_MSB //// 4752 4753 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) 4754 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) 4755 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK 0x000000ff 4756 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_SHFT 0 4757 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x) \ 4758 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK) 4759 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, mask) \ 4760 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), mask) 4761 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUT(x, val) \ 4762 out_dword( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), val) 4763 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4764 do {\ 4765 HWIO_INTLOCK(); \ 4766 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x)); \ 4767 HWIO_INTFREE();\ 4768 } while (0) 4769 4770 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4771 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4772 4773 //// Register REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP //// 4774 4775 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) 4776 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) 4777 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4778 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SHFT 0 4779 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x) \ 4780 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK) 4781 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4782 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4783 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4784 out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4785 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4786 do {\ 4787 HWIO_INTLOCK(); \ 4788 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x)); \ 4789 HWIO_INTFREE();\ 4790 } while (0) 4791 4792 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4793 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4794 4795 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4796 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4797 4798 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4799 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4800 4801 //// Register REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS //// 4802 4803 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) 4804 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) 4805 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4806 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_SHFT 0 4807 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x) \ 4808 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK) 4809 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4810 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4811 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4812 out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4813 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4814 do {\ 4815 HWIO_INTLOCK(); \ 4816 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x)); \ 4817 HWIO_INTFREE();\ 4818 } while (0) 4819 4820 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4821 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4822 4823 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4824 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4825 4826 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4827 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4828 4829 //// Register REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER //// 4830 4831 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) 4832 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) 4833 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4834 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_SHFT 0 4835 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4836 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK) 4837 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4838 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4839 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4840 out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4841 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4842 do {\ 4843 HWIO_INTLOCK(); \ 4844 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4845 HWIO_INTFREE();\ 4846 } while (0) 4847 4848 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4849 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4850 4851 //// Register REO_R0_REO2SW6_RING_MSI1_BASE_LSB //// 4852 4853 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) 4854 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) 4855 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4856 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_SHFT 0 4857 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x) \ 4858 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK) 4859 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, mask) \ 4860 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), mask) 4861 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUT(x, val) \ 4862 out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), val) 4863 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4864 do {\ 4865 HWIO_INTLOCK(); \ 4866 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x)); \ 4867 HWIO_INTFREE();\ 4868 } while (0) 4869 4870 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4871 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4872 4873 //// Register REO_R0_REO2SW6_RING_MSI1_BASE_MSB //// 4874 4875 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) 4876 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) 4877 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4878 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_SHFT 0 4879 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x) \ 4880 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK) 4881 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, mask) \ 4882 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), mask) 4883 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUT(x, val) \ 4884 out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), val) 4885 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4886 do {\ 4887 HWIO_INTLOCK(); \ 4888 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x)); \ 4889 HWIO_INTFREE();\ 4890 } while (0) 4891 4892 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4893 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4894 4895 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4896 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4897 4898 //// Register REO_R0_REO2SW6_RING_MSI1_DATA //// 4899 4900 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) 4901 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) 4902 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK 0xffffffff 4903 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_SHFT 0 4904 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x) \ 4905 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK) 4906 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, mask) \ 4907 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), mask) 4908 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUT(x, val) \ 4909 out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), val) 4910 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x, mask, val) \ 4911 do {\ 4912 HWIO_INTLOCK(); \ 4913 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x)); \ 4914 HWIO_INTFREE();\ 4915 } while (0) 4916 4917 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4918 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_SHFT 0x0 4919 4920 //// Register REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET //// 4921 4922 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) 4923 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) 4924 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4925 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_SHFT 0 4926 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x) \ 4927 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK) 4928 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4929 in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4930 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4931 out_dword( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4932 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4933 do {\ 4934 HWIO_INTLOCK(); \ 4935 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x)); \ 4936 HWIO_INTFREE();\ 4937 } while (0) 4938 4939 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4940 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4941 4942 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4943 4944 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4945 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4946 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4947 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4948 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 4949 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 4950 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 4951 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 4952 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 4953 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 4954 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 4955 do {\ 4956 HWIO_INTLOCK(); \ 4957 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 4958 HWIO_INTFREE();\ 4959 } while (0) 4960 4961 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4962 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4963 4964 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 4965 4966 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400) 4967 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400) 4968 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff 4969 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 4970 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 4971 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 4972 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 4973 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 4974 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 4975 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 4976 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 4977 do {\ 4978 HWIO_INTLOCK(); \ 4979 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 4980 HWIO_INTFREE();\ 4981 } while (0) 4982 4983 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 4984 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4985 4986 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4987 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4988 4989 //// Register REO_R0_REO2TCL_RING_ID //// 4990 4991 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404) 4992 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404) 4993 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 4994 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 4995 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 4996 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 4997 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 4998 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 4999 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 5000 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 5001 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 5002 do {\ 5003 HWIO_INTLOCK(); \ 5004 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 5005 HWIO_INTFREE();\ 5006 } while (0) 5007 5008 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 5009 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 5010 5011 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5012 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 5013 5014 //// Register REO_R0_REO2TCL_RING_STATUS //// 5015 5016 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408) 5017 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408) 5018 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 5019 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 5020 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 5021 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 5022 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 5023 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 5024 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 5025 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 5026 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 5027 do {\ 5028 HWIO_INTLOCK(); \ 5029 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 5030 HWIO_INTFREE();\ 5031 } while (0) 5032 5033 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5034 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5035 5036 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5037 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5038 5039 //// Register REO_R0_REO2TCL_RING_MISC //// 5040 5041 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c) 5042 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c) 5043 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff 5044 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 5045 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 5046 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 5047 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 5048 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 5049 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 5050 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 5051 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 5052 do {\ 5053 HWIO_INTLOCK(); \ 5054 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 5055 HWIO_INTFREE();\ 5056 } while (0) 5057 5058 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5059 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 5060 5061 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5062 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe 5063 5064 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5065 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5066 5067 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5068 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5069 5070 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5071 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5072 5073 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5074 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 5075 5076 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5077 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5078 5079 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5080 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5081 5082 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5083 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5084 5085 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5086 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 5087 5088 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5089 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5090 5091 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5092 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5093 5094 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 5095 5096 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 5097 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 5098 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 5099 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 5100 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 5101 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 5102 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 5103 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 5104 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 5105 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 5106 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5107 do {\ 5108 HWIO_INTLOCK(); \ 5109 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 5110 HWIO_INTFREE();\ 5111 } while (0) 5112 5113 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5114 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5115 5116 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 5117 5118 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 5119 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 5120 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 5121 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 5122 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 5123 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 5124 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 5125 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 5126 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 5127 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 5128 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5129 do {\ 5130 HWIO_INTLOCK(); \ 5131 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 5132 HWIO_INTFREE();\ 5133 } while (0) 5134 5135 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5136 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5137 5138 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 5139 5140 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 5141 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 5142 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5143 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 5144 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 5145 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 5146 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5147 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5148 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5149 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5150 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5151 do {\ 5152 HWIO_INTLOCK(); \ 5153 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 5154 HWIO_INTFREE();\ 5155 } while (0) 5156 5157 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5158 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5159 5160 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5161 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5162 5163 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5164 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5165 5166 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 5167 5168 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 5169 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 5170 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5171 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 5172 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 5173 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 5174 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5175 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5176 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5177 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5178 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5179 do {\ 5180 HWIO_INTLOCK(); \ 5181 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 5182 HWIO_INTFREE();\ 5183 } while (0) 5184 5185 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5186 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5187 5188 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5189 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5190 5191 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5192 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5193 5194 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 5195 5196 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 5197 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 5198 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5199 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 5200 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5201 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 5202 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5203 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5204 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5205 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5206 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5207 do {\ 5208 HWIO_INTLOCK(); \ 5209 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5210 HWIO_INTFREE();\ 5211 } while (0) 5212 5213 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5214 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5215 5216 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 5217 5218 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 5219 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 5220 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5221 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 5222 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 5223 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 5224 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 5225 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 5226 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 5227 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 5228 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5229 do {\ 5230 HWIO_INTLOCK(); \ 5231 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 5232 HWIO_INTFREE();\ 5233 } while (0) 5234 5235 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5236 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5237 5238 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 5239 5240 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 5241 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 5242 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5243 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 5244 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 5245 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 5246 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 5247 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 5248 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 5249 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 5250 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5251 do {\ 5252 HWIO_INTLOCK(); \ 5253 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 5254 HWIO_INTFREE();\ 5255 } while (0) 5256 5257 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5258 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5259 5260 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5261 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5262 5263 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 5264 5265 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 5266 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 5267 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 5268 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 5269 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 5270 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 5271 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 5272 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 5273 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 5274 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 5275 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 5276 do {\ 5277 HWIO_INTLOCK(); \ 5278 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 5279 HWIO_INTFREE();\ 5280 } while (0) 5281 5282 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5283 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 5284 5285 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 5286 5287 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 5288 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 5289 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5290 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 5291 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 5292 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 5293 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5294 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5295 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5296 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5297 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5298 do {\ 5299 HWIO_INTLOCK(); \ 5300 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 5301 HWIO_INTFREE();\ 5302 } while (0) 5303 5304 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5305 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5306 5307 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 5308 5309 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454) 5310 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454) 5311 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 5312 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 5313 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 5314 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 5315 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 5316 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 5317 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 5318 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 5319 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 5320 do {\ 5321 HWIO_INTLOCK(); \ 5322 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 5323 HWIO_INTFREE();\ 5324 } while (0) 5325 5326 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5327 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5328 5329 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 5330 5331 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458) 5332 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458) 5333 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff 5334 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 5335 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 5336 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 5337 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 5338 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 5339 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 5340 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 5341 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 5342 do {\ 5343 HWIO_INTLOCK(); \ 5344 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 5345 HWIO_INTFREE();\ 5346 } while (0) 5347 5348 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 5349 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5350 5351 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5352 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5353 5354 //// Register REO_R0_REO2FW_RING_ID //// 5355 5356 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c) 5357 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c) 5358 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 5359 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 5360 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 5361 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 5362 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 5363 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 5364 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 5365 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 5366 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 5367 do {\ 5368 HWIO_INTLOCK(); \ 5369 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 5370 HWIO_INTFREE();\ 5371 } while (0) 5372 5373 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 5374 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 5375 5376 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5377 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 5378 5379 //// Register REO_R0_REO2FW_RING_STATUS //// 5380 5381 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460) 5382 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460) 5383 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 5384 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 5385 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 5386 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 5387 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 5388 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 5389 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 5390 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 5391 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 5392 do {\ 5393 HWIO_INTLOCK(); \ 5394 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 5395 HWIO_INTFREE();\ 5396 } while (0) 5397 5398 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5399 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5400 5401 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5402 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5403 5404 //// Register REO_R0_REO2FW_RING_MISC //// 5405 5406 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464) 5407 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464) 5408 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff 5409 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 5410 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 5411 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 5412 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 5413 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 5414 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 5415 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 5416 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 5417 do {\ 5418 HWIO_INTLOCK(); \ 5419 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 5420 HWIO_INTFREE();\ 5421 } while (0) 5422 5423 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5424 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 5425 5426 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5427 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 5428 5429 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5430 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5431 5432 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5433 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5434 5435 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5436 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5437 5438 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5439 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 5440 5441 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5442 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5443 5444 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5445 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5446 5447 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5448 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5449 5450 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5451 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 5452 5453 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5454 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5455 5456 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5457 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5458 5459 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 5460 5461 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 5462 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 5463 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 5464 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 5465 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 5466 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 5467 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 5468 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 5469 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 5470 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 5471 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5472 do {\ 5473 HWIO_INTLOCK(); \ 5474 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 5475 HWIO_INTFREE();\ 5476 } while (0) 5477 5478 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5479 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5480 5481 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 5482 5483 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 5484 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 5485 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 5486 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 5487 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 5488 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 5489 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 5490 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 5491 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 5492 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 5493 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5494 do {\ 5495 HWIO_INTLOCK(); \ 5496 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 5497 HWIO_INTFREE();\ 5498 } while (0) 5499 5500 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5501 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5502 5503 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 5504 5505 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 5506 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 5507 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5508 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 5509 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 5510 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 5511 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5512 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5513 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5514 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5515 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5516 do {\ 5517 HWIO_INTLOCK(); \ 5518 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 5519 HWIO_INTFREE();\ 5520 } while (0) 5521 5522 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5523 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5524 5525 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5526 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5527 5528 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5529 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5530 5531 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 5532 5533 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 5534 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 5535 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5536 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 5537 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 5538 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 5539 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5540 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5541 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5542 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5543 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5544 do {\ 5545 HWIO_INTLOCK(); \ 5546 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 5547 HWIO_INTFREE();\ 5548 } while (0) 5549 5550 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5551 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5552 5553 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5554 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5555 5556 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5557 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5558 5559 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 5560 5561 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 5562 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 5563 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5564 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 5565 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5566 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 5567 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5568 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5569 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5570 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5571 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5572 do {\ 5573 HWIO_INTLOCK(); \ 5574 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5575 HWIO_INTFREE();\ 5576 } while (0) 5577 5578 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5579 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5580 5581 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 5582 5583 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) 5584 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) 5585 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5586 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 5587 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 5588 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 5589 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 5590 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 5591 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 5592 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 5593 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5594 do {\ 5595 HWIO_INTLOCK(); \ 5596 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 5597 HWIO_INTFREE();\ 5598 } while (0) 5599 5600 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5601 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5602 5603 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 5604 5605 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) 5606 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) 5607 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5608 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 5609 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 5610 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 5611 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 5612 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 5613 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 5614 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 5615 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5616 do {\ 5617 HWIO_INTLOCK(); \ 5618 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 5619 HWIO_INTFREE();\ 5620 } while (0) 5621 5622 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5623 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5624 5625 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5626 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5627 5628 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 5629 5630 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) 5631 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) 5632 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 5633 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 5634 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 5635 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 5636 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 5637 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 5638 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 5639 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 5640 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 5641 do {\ 5642 HWIO_INTLOCK(); \ 5643 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 5644 HWIO_INTFREE();\ 5645 } while (0) 5646 5647 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5648 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 5649 5650 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 5651 5652 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 5653 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 5654 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5655 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 5656 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 5657 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 5658 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5659 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5660 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5661 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5662 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5663 do {\ 5664 HWIO_INTLOCK(); \ 5665 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 5666 HWIO_INTFREE();\ 5667 } while (0) 5668 5669 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5670 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5671 5672 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 5673 5674 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 5675 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 5676 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 5677 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 5678 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 5679 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 5680 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 5681 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 5682 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 5683 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 5684 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 5685 do {\ 5686 HWIO_INTLOCK(); \ 5687 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 5688 HWIO_INTFREE();\ 5689 } while (0) 5690 5691 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5692 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5693 5694 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 5695 5696 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 5697 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 5698 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 5699 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 5700 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 5701 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 5702 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 5703 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 5704 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 5705 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 5706 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 5707 do {\ 5708 HWIO_INTLOCK(); \ 5709 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 5710 HWIO_INTFREE();\ 5711 } while (0) 5712 5713 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5714 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5715 5716 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5717 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5718 5719 //// Register REO_R0_REO_RELEASE_RING_ID //// 5720 5721 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4) 5722 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4) 5723 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 5724 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 5725 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 5726 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 5727 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 5728 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 5729 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 5730 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 5731 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 5732 do {\ 5733 HWIO_INTLOCK(); \ 5734 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 5735 HWIO_INTFREE();\ 5736 } while (0) 5737 5738 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 5739 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 5740 5741 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5742 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5743 5744 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5745 5746 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8) 5747 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8) 5748 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5749 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5750 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5751 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5752 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5753 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5754 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5755 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5756 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5757 do {\ 5758 HWIO_INTLOCK(); \ 5759 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5760 HWIO_INTFREE();\ 5761 } while (0) 5762 5763 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5764 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5765 5766 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5767 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5768 5769 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5770 5771 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc) 5772 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc) 5773 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff 5774 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5775 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5776 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5777 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5778 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5779 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5780 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5781 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5782 do {\ 5783 HWIO_INTLOCK(); \ 5784 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5785 HWIO_INTFREE();\ 5786 } while (0) 5787 5788 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5789 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 5790 5791 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5792 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe 5793 5794 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5795 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5796 5797 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5798 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5799 5800 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5801 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5802 5803 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5804 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 5805 5806 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5807 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5808 5809 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5810 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5811 5812 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5813 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5814 5815 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5816 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5817 5818 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5819 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5820 5821 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5822 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5823 5824 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5825 5826 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5827 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5828 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5829 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5830 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5831 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5832 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5833 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5834 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5835 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5836 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5837 do {\ 5838 HWIO_INTLOCK(); \ 5839 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5840 HWIO_INTFREE();\ 5841 } while (0) 5842 5843 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5844 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5845 5846 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5847 5848 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5849 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5850 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5851 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5852 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5853 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5854 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5855 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5856 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5857 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5858 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5859 do {\ 5860 HWIO_INTLOCK(); \ 5861 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5862 HWIO_INTFREE();\ 5863 } while (0) 5864 5865 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5866 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5867 5868 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5869 5870 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5871 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5872 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5873 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5874 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5875 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5876 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5877 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5878 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5879 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5880 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5881 do {\ 5882 HWIO_INTLOCK(); \ 5883 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5884 HWIO_INTFREE();\ 5885 } while (0) 5886 5887 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5888 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5889 5890 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5891 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5892 5893 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5894 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5895 5896 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5897 5898 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5899 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5900 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5901 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5902 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5903 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5904 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5905 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5906 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5907 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5908 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5909 do {\ 5910 HWIO_INTLOCK(); \ 5911 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5912 HWIO_INTFREE();\ 5913 } while (0) 5914 5915 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5916 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5917 5918 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5919 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5920 5921 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5922 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5923 5924 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5925 5926 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5927 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5928 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5929 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5930 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5931 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5932 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5933 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5934 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5935 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5936 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5937 do {\ 5938 HWIO_INTLOCK(); \ 5939 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5940 HWIO_INTFREE();\ 5941 } while (0) 5942 5943 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5944 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5945 5946 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB //// 5947 5948 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) 5949 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) 5950 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5951 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 5952 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ 5953 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK) 5954 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ 5955 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 5956 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ 5957 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) 5958 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5959 do {\ 5960 HWIO_INTLOCK(); \ 5961 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ 5962 HWIO_INTFREE();\ 5963 } while (0) 5964 5965 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5966 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5967 5968 //// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB //// 5969 5970 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) 5971 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) 5972 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5973 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 5974 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ 5975 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK) 5976 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ 5977 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 5978 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ 5979 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) 5980 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5981 do {\ 5982 HWIO_INTLOCK(); \ 5983 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ 5984 HWIO_INTFREE();\ 5985 } while (0) 5986 5987 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5988 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5989 5990 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5991 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5992 5993 //// Register REO_R0_REO_RELEASE_RING_MSI1_DATA //// 5994 5995 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) 5996 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) 5997 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff 5998 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0 5999 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ 6000 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK) 6001 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ 6002 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 6003 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \ 6004 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val) 6005 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ 6006 do {\ 6007 HWIO_INTLOCK(); \ 6008 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \ 6009 HWIO_INTFREE();\ 6010 } while (0) 6011 6012 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6013 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 6014 6015 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 6016 6017 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 6018 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 6019 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 6020 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 6021 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 6022 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 6023 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 6024 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 6025 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 6026 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 6027 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 6028 do {\ 6029 HWIO_INTLOCK(); \ 6030 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 6031 HWIO_INTFREE();\ 6032 } while (0) 6033 6034 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 6035 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6036 6037 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 6038 6039 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504) 6040 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504) 6041 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 6042 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 6043 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 6044 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 6045 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 6046 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 6047 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 6048 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 6049 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 6050 do {\ 6051 HWIO_INTLOCK(); \ 6052 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 6053 HWIO_INTFREE();\ 6054 } while (0) 6055 6056 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 6057 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 6058 6059 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 6060 6061 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508) 6062 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508) 6063 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 6064 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 6065 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 6066 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 6067 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 6068 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 6069 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 6070 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 6071 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 6072 do {\ 6073 HWIO_INTLOCK(); \ 6074 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 6075 HWIO_INTFREE();\ 6076 } while (0) 6077 6078 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 6079 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 6080 6081 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 6082 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 6083 6084 //// Register REO_R0_REO_STATUS_RING_ID //// 6085 6086 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c) 6087 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c) 6088 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 6089 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 6090 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 6091 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 6092 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 6093 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 6094 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 6095 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 6096 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 6097 do {\ 6098 HWIO_INTLOCK(); \ 6099 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 6100 HWIO_INTFREE();\ 6101 } while (0) 6102 6103 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 6104 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 6105 6106 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 6107 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 6108 6109 //// Register REO_R0_REO_STATUS_RING_STATUS //// 6110 6111 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510) 6112 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510) 6113 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 6114 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 6115 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 6116 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 6117 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 6118 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 6119 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 6120 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 6121 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 6122 do {\ 6123 HWIO_INTLOCK(); \ 6124 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 6125 HWIO_INTFREE();\ 6126 } while (0) 6127 6128 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 6129 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 6130 6131 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 6132 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 6133 6134 //// Register REO_R0_REO_STATUS_RING_MISC //// 6135 6136 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514) 6137 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514) 6138 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff 6139 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 6140 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 6141 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 6142 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 6143 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 6144 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 6145 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 6146 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 6147 do {\ 6148 HWIO_INTLOCK(); \ 6149 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 6150 HWIO_INTFREE();\ 6151 } while (0) 6152 6153 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 6154 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 6155 6156 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 6157 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 6158 6159 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 6160 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 6161 6162 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 6163 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 6164 6165 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 6166 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 6167 6168 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 6169 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 6170 6171 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 6172 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 6173 6174 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 6175 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 6176 6177 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 6178 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 6179 6180 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 6181 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 6182 6183 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 6184 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 6185 6186 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 6187 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 6188 6189 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 6190 6191 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518) 6192 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518) 6193 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 6194 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 6195 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 6196 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 6197 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 6198 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 6199 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 6200 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 6201 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 6202 do {\ 6203 HWIO_INTLOCK(); \ 6204 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 6205 HWIO_INTFREE();\ 6206 } while (0) 6207 6208 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 6209 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 6210 6211 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 6212 6213 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c) 6214 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c) 6215 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 6216 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 6217 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 6218 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 6219 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 6220 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 6221 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 6222 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 6223 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 6224 do {\ 6225 HWIO_INTLOCK(); \ 6226 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 6227 HWIO_INTFREE();\ 6228 } while (0) 6229 6230 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 6231 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 6232 6233 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 6234 6235 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528) 6236 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528) 6237 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 6238 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 6239 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 6240 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 6241 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 6242 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 6243 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 6244 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 6245 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 6246 do {\ 6247 HWIO_INTLOCK(); \ 6248 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 6249 HWIO_INTFREE();\ 6250 } while (0) 6251 6252 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 6253 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 6254 6255 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 6256 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 6257 6258 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 6259 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 6260 6261 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 6262 6263 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c) 6264 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c) 6265 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 6266 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 6267 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 6268 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 6269 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 6270 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 6271 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 6272 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 6273 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 6274 do {\ 6275 HWIO_INTLOCK(); \ 6276 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 6277 HWIO_INTFREE();\ 6278 } while (0) 6279 6280 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 6281 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 6282 6283 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 6284 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 6285 6286 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 6287 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 6288 6289 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 6290 6291 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530) 6292 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530) 6293 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 6294 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 6295 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 6296 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 6297 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 6298 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 6299 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 6300 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 6301 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 6302 do {\ 6303 HWIO_INTLOCK(); \ 6304 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 6305 HWIO_INTFREE();\ 6306 } while (0) 6307 6308 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 6309 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 6310 6311 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 6312 6313 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c) 6314 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c) 6315 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 6316 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 6317 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 6318 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 6319 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 6320 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 6321 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 6322 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 6323 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 6324 do {\ 6325 HWIO_INTLOCK(); \ 6326 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 6327 HWIO_INTFREE();\ 6328 } while (0) 6329 6330 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 6331 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 6332 6333 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 6334 6335 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550) 6336 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550) 6337 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 6338 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 6339 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 6340 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 6341 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 6342 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 6343 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 6344 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 6345 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 6346 do {\ 6347 HWIO_INTLOCK(); \ 6348 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 6349 HWIO_INTFREE();\ 6350 } while (0) 6351 6352 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 6353 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 6354 6355 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 6356 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 6357 6358 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 6359 6360 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554) 6361 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554) 6362 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 6363 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 6364 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 6365 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 6366 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 6367 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 6368 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 6369 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 6370 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 6371 do {\ 6372 HWIO_INTLOCK(); \ 6373 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 6374 HWIO_INTFREE();\ 6375 } while (0) 6376 6377 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 6378 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 6379 6380 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 6381 6382 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558) 6383 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558) 6384 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 6385 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 6386 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 6387 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 6388 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 6389 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 6390 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 6391 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 6392 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 6393 do {\ 6394 HWIO_INTLOCK(); \ 6395 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 6396 HWIO_INTFREE();\ 6397 } while (0) 6398 6399 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 6400 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 6401 6402 //// Register REO_R0_WATCHDOG_TIMEOUT //// 6403 6404 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c) 6405 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c) 6406 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff 6407 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 6408 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 6409 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 6410 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 6411 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 6412 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 6413 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 6414 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 6415 do {\ 6416 HWIO_INTLOCK(); \ 6417 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 6418 HWIO_INTFREE();\ 6419 } while (0) 6420 6421 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000 6422 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc 6423 6424 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 6425 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 6426 6427 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 6428 6429 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560) 6430 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560) 6431 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 6432 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 6433 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 6434 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 6435 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 6436 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 6437 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 6438 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 6439 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 6440 do {\ 6441 HWIO_INTLOCK(); \ 6442 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 6443 HWIO_INTFREE();\ 6444 } while (0) 6445 6446 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 6447 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 6448 6449 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 6450 6451 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564) 6452 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564) 6453 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 6454 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 6455 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 6456 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 6457 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 6458 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 6459 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 6460 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 6461 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 6462 do {\ 6463 HWIO_INTLOCK(); \ 6464 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 6465 HWIO_INTFREE();\ 6466 } while (0) 6467 6468 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 6469 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 6470 6471 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 6472 6473 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568) 6474 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568) 6475 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 6476 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 6477 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 6478 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 6479 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 6480 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 6481 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 6482 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 6483 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 6484 do {\ 6485 HWIO_INTLOCK(); \ 6486 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 6487 HWIO_INTFREE();\ 6488 } while (0) 6489 6490 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 6491 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 6492 6493 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 6494 6495 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c) 6496 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c) 6497 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 6498 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 6499 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 6500 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 6501 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 6502 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 6503 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 6504 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 6505 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 6506 do {\ 6507 HWIO_INTLOCK(); \ 6508 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 6509 HWIO_INTFREE();\ 6510 } while (0) 6511 6512 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 6513 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 6514 6515 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 6516 6517 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570) 6518 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570) 6519 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 6520 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 6521 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 6522 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 6523 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 6524 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 6525 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 6526 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 6527 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 6528 do {\ 6529 HWIO_INTLOCK(); \ 6530 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 6531 HWIO_INTFREE();\ 6532 } while (0) 6533 6534 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 6535 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 6536 6537 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 6538 6539 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574) 6540 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574) 6541 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 6542 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 6543 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 6544 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 6545 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 6546 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 6547 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 6548 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 6549 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 6550 do {\ 6551 HWIO_INTLOCK(); \ 6552 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 6553 HWIO_INTFREE();\ 6554 } while (0) 6555 6556 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6557 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 6558 6559 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 6560 6561 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578) 6562 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578) 6563 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 6564 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 6565 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 6566 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 6567 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 6568 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 6569 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 6570 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 6571 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 6572 do {\ 6573 HWIO_INTLOCK(); \ 6574 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 6575 HWIO_INTFREE();\ 6576 } while (0) 6577 6578 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6579 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 6580 6581 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 6582 6583 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c) 6584 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c) 6585 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 6586 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 6587 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 6588 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 6589 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 6590 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 6591 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 6592 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 6593 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 6594 do {\ 6595 HWIO_INTLOCK(); \ 6596 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 6597 HWIO_INTFREE();\ 6598 } while (0) 6599 6600 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6601 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 6602 6603 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 6604 6605 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580) 6606 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580) 6607 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 6608 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 6609 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 6610 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 6611 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 6612 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 6613 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 6614 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 6615 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 6616 do {\ 6617 HWIO_INTLOCK(); \ 6618 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 6619 HWIO_INTFREE();\ 6620 } while (0) 6621 6622 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6623 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 6624 6625 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 6626 6627 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584) 6628 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584) 6629 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 6630 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 6631 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 6632 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 6633 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 6634 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 6635 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 6636 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 6637 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 6638 do {\ 6639 HWIO_INTLOCK(); \ 6640 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 6641 HWIO_INTFREE();\ 6642 } while (0) 6643 6644 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6645 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 6646 6647 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 6648 6649 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588) 6650 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588) 6651 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 6652 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 6653 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 6654 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 6655 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 6656 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 6657 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 6658 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 6659 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 6660 do {\ 6661 HWIO_INTLOCK(); \ 6662 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 6663 HWIO_INTFREE();\ 6664 } while (0) 6665 6666 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6667 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 6668 6669 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 6670 6671 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c) 6672 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c) 6673 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 6674 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 6675 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 6676 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 6677 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 6678 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 6679 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 6680 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 6681 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 6682 do {\ 6683 HWIO_INTLOCK(); \ 6684 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 6685 HWIO_INTFREE();\ 6686 } while (0) 6687 6688 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6689 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 6690 6691 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 6692 6693 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590) 6694 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590) 6695 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 6696 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 6697 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 6698 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 6699 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 6700 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 6701 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 6702 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 6703 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 6704 do {\ 6705 HWIO_INTLOCK(); \ 6706 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 6707 HWIO_INTFREE();\ 6708 } while (0) 6709 6710 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6711 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 6712 6713 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 6714 6715 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594) 6716 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594) 6717 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 6718 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 6719 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 6720 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 6721 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 6722 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 6723 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 6724 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 6725 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 6726 do {\ 6727 HWIO_INTLOCK(); \ 6728 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 6729 HWIO_INTFREE();\ 6730 } while (0) 6731 6732 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6733 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 6734 6735 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 6736 6737 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598) 6738 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598) 6739 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 6740 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6741 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6742 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6743 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6744 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6745 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6746 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6747 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6748 do {\ 6749 HWIO_INTLOCK(); \ 6750 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6751 HWIO_INTFREE();\ 6752 } while (0) 6753 6754 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6755 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6756 6757 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6758 6759 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c) 6760 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c) 6761 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6762 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6763 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6764 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6765 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6766 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6767 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6768 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6769 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6770 do {\ 6771 HWIO_INTLOCK(); \ 6772 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6773 HWIO_INTFREE();\ 6774 } while (0) 6775 6776 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6777 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6778 6779 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6780 6781 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0) 6782 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0) 6783 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6784 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6785 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6786 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6787 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6788 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6789 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6790 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6791 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6792 do {\ 6793 HWIO_INTLOCK(); \ 6794 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6795 HWIO_INTFREE();\ 6796 } while (0) 6797 6798 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6799 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6800 6801 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6802 6803 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4) 6804 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4) 6805 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6806 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6807 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6808 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6809 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6810 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6811 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6812 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6813 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6814 do {\ 6815 HWIO_INTLOCK(); \ 6816 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6817 HWIO_INTFREE();\ 6818 } while (0) 6819 6820 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6821 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6822 6823 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6824 6825 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8) 6826 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8) 6827 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6828 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6829 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6830 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6831 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6832 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6833 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6834 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6835 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6836 do {\ 6837 HWIO_INTLOCK(); \ 6838 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6839 HWIO_INTFREE();\ 6840 } while (0) 6841 6842 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6843 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6844 6845 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6846 6847 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac) 6848 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac) 6849 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6850 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6851 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6852 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6853 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6854 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6855 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6856 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6857 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6858 do {\ 6859 HWIO_INTLOCK(); \ 6860 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6861 HWIO_INTFREE();\ 6862 } while (0) 6863 6864 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6865 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6866 6867 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6868 6869 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0) 6870 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0) 6871 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6872 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6873 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6874 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6875 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6876 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6877 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6878 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6879 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6880 do {\ 6881 HWIO_INTLOCK(); \ 6882 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6883 HWIO_INTFREE();\ 6884 } while (0) 6885 6886 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6887 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6888 6889 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6890 6891 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4) 6892 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4) 6893 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6894 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6895 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6896 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6897 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6898 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6899 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6900 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6901 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6902 do {\ 6903 HWIO_INTLOCK(); \ 6904 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6905 HWIO_INTFREE();\ 6906 } while (0) 6907 6908 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6909 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6910 6911 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6912 6913 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8) 6914 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8) 6915 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6916 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6917 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6918 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6919 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6920 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6921 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6922 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6923 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6924 do {\ 6925 HWIO_INTLOCK(); \ 6926 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6927 HWIO_INTFREE();\ 6928 } while (0) 6929 6930 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6931 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6932 6933 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6934 6935 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc) 6936 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc) 6937 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6938 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6939 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6940 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6941 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6942 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6943 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6944 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6945 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6946 do {\ 6947 HWIO_INTLOCK(); \ 6948 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6949 HWIO_INTFREE();\ 6950 } while (0) 6951 6952 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6953 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6954 6955 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6956 6957 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0) 6958 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0) 6959 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6960 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6961 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6962 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6963 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6964 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6965 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6966 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6967 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6968 do {\ 6969 HWIO_INTLOCK(); \ 6970 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6971 HWIO_INTFREE();\ 6972 } while (0) 6973 6974 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6975 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6976 6977 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6978 6979 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4) 6980 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4) 6981 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6982 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6983 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6984 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6985 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6986 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6987 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6988 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6989 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6990 do {\ 6991 HWIO_INTLOCK(); \ 6992 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6993 HWIO_INTFREE();\ 6994 } while (0) 6995 6996 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6997 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6998 6999 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 7000 7001 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8) 7002 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8) 7003 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 7004 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 7005 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 7006 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 7007 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 7008 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 7009 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 7010 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 7011 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 7012 do {\ 7013 HWIO_INTLOCK(); \ 7014 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 7015 HWIO_INTFREE();\ 7016 } while (0) 7017 7018 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 7019 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 7020 7021 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 7022 7023 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc) 7024 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc) 7025 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 7026 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 7027 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 7028 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 7029 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 7030 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 7031 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 7032 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 7033 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 7034 do {\ 7035 HWIO_INTLOCK(); \ 7036 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 7037 HWIO_INTFREE();\ 7038 } while (0) 7039 7040 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 7041 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 7042 7043 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 7044 7045 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0) 7046 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0) 7047 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 7048 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 7049 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 7050 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 7051 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 7052 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 7053 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 7054 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 7055 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 7056 do {\ 7057 HWIO_INTLOCK(); \ 7058 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 7059 HWIO_INTFREE();\ 7060 } while (0) 7061 7062 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 7063 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 7064 7065 //// Register REO_R0_AGING_CONTROL //// 7066 7067 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4) 7068 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4) 7069 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 7070 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 7071 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 7072 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 7073 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 7074 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 7075 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 7076 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 7077 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 7078 do {\ 7079 HWIO_INTLOCK(); \ 7080 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 7081 HWIO_INTFREE();\ 7082 } while (0) 7083 7084 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 7085 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 7086 7087 //// Register REO_R0_MISC_CTL //// 7088 7089 #define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8) 7090 #define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8) 7091 #define HWIO_REO_R0_MISC_CTL_RMSK 0x001fffff 7092 #define HWIO_REO_R0_MISC_CTL_SHFT 0 7093 #define HWIO_REO_R0_MISC_CTL_IN(x) \ 7094 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK) 7095 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ 7096 in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) 7097 #define HWIO_REO_R0_MISC_CTL_OUT(x, val) \ 7098 out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val) 7099 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ 7100 do {\ 7101 HWIO_INTLOCK(); \ 7102 out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \ 7103 HWIO_INTFREE();\ 7104 } while (0) 7105 7106 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x001e0000 7107 #define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 0x11 7108 7109 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000 7110 #define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10 7111 7112 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x00008000 7113 #define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 0xf 7114 7115 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x00007fff 7116 #define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0 7117 7118 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 7119 7120 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc) 7121 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc) 7122 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 7123 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 7124 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 7125 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 7126 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 7127 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 7128 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 7129 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 7130 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 7131 do {\ 7132 HWIO_INTLOCK(); \ 7133 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 7134 HWIO_INTFREE();\ 7135 } while (0) 7136 7137 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 7138 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 7139 7140 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 7141 7142 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0) 7143 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0) 7144 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 7145 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 7146 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 7147 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 7148 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 7149 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 7150 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 7151 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 7152 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 7153 do {\ 7154 HWIO_INTLOCK(); \ 7155 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 7156 HWIO_INTFREE();\ 7157 } while (0) 7158 7159 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 7160 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 7161 7162 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 7163 7164 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4) 7165 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4) 7166 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 7167 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 7168 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 7169 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 7170 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 7171 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 7172 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 7173 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 7174 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 7175 do {\ 7176 HWIO_INTLOCK(); \ 7177 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 7178 HWIO_INTFREE();\ 7179 } while (0) 7180 7181 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 7182 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 7183 7184 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 7185 7186 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8) 7187 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8) 7188 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 7189 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 7190 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 7191 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 7192 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 7193 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 7194 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 7195 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 7196 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 7197 do {\ 7198 HWIO_INTLOCK(); \ 7199 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 7200 HWIO_INTFREE();\ 7201 } while (0) 7202 7203 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 7204 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 7205 7206 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 7207 7208 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec) 7209 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec) 7210 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 7211 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 7212 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 7213 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 7214 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 7215 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 7216 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 7217 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 7218 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 7219 do {\ 7220 HWIO_INTLOCK(); \ 7221 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 7222 HWIO_INTFREE();\ 7223 } while (0) 7224 7225 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 7226 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 7227 7228 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 7229 7230 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0) 7231 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0) 7232 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 7233 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 7234 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 7235 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 7236 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 7237 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 7238 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 7239 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 7240 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 7241 do {\ 7242 HWIO_INTLOCK(); \ 7243 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 7244 HWIO_INTFREE();\ 7245 } while (0) 7246 7247 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 7248 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 7249 7250 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 7251 7252 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4) 7253 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4) 7254 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 7255 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 7256 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 7257 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 7258 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 7259 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 7260 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 7261 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 7262 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 7263 do {\ 7264 HWIO_INTLOCK(); \ 7265 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 7266 HWIO_INTFREE();\ 7267 } while (0) 7268 7269 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 7270 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 7271 7272 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 7273 7274 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8) 7275 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8) 7276 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 7277 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 7278 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 7279 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 7280 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 7281 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 7282 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 7283 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 7284 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 7285 do {\ 7286 HWIO_INTLOCK(); \ 7287 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 7288 HWIO_INTFREE();\ 7289 } while (0) 7290 7291 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 7292 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 7293 7294 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 7295 7296 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc) 7297 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc) 7298 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 7299 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 7300 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 7301 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 7302 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 7303 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 7304 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 7305 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 7306 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 7307 do {\ 7308 HWIO_INTLOCK(); \ 7309 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 7310 HWIO_INTFREE();\ 7311 } while (0) 7312 7313 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 7314 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 7315 7316 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 7317 7318 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600) 7319 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600) 7320 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 7321 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 7322 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 7323 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 7324 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 7325 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 7326 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 7327 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 7328 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 7329 do {\ 7330 HWIO_INTLOCK(); \ 7331 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 7332 HWIO_INTFREE();\ 7333 } while (0) 7334 7335 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 7336 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 7337 7338 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 7339 7340 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604) 7341 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604) 7342 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 7343 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 7344 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 7345 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 7346 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 7347 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 7348 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 7349 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 7350 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 7351 do {\ 7352 HWIO_INTLOCK(); \ 7353 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 7354 HWIO_INTFREE();\ 7355 } while (0) 7356 7357 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 7358 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 7359 7360 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 7361 7362 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608) 7363 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608) 7364 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 7365 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 7366 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 7367 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 7368 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 7369 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 7370 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 7371 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 7372 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 7373 do {\ 7374 HWIO_INTLOCK(); \ 7375 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 7376 HWIO_INTFREE();\ 7377 } while (0) 7378 7379 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 7380 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 7381 7382 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 7383 7384 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c) 7385 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c) 7386 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 7387 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 7388 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 7389 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 7390 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 7391 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 7392 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 7393 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 7394 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 7395 do {\ 7396 HWIO_INTLOCK(); \ 7397 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 7398 HWIO_INTFREE();\ 7399 } while (0) 7400 7401 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 7402 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 7403 7404 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 7405 7406 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610) 7407 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610) 7408 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 7409 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 7410 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 7411 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 7412 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 7413 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 7414 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 7415 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 7416 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 7417 do {\ 7418 HWIO_INTLOCK(); \ 7419 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 7420 HWIO_INTFREE();\ 7421 } while (0) 7422 7423 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 7424 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 7425 7426 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 7427 7428 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614) 7429 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614) 7430 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 7431 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 7432 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 7433 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 7434 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 7435 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 7436 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 7437 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 7438 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 7439 do {\ 7440 HWIO_INTLOCK(); \ 7441 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 7442 HWIO_INTFREE();\ 7443 } while (0) 7444 7445 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 7446 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 7447 7448 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 7449 7450 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618) 7451 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618) 7452 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 7453 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 7454 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 7455 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 7456 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 7457 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 7458 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 7459 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 7460 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 7461 do {\ 7462 HWIO_INTLOCK(); \ 7463 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 7464 HWIO_INTFREE();\ 7465 } while (0) 7466 7467 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 7468 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 7469 7470 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 7471 7472 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c) 7473 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c) 7474 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 7475 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 7476 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 7477 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 7478 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 7479 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 7480 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 7481 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 7482 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 7483 do {\ 7484 HWIO_INTLOCK(); \ 7485 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 7486 HWIO_INTFREE();\ 7487 } while (0) 7488 7489 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 7490 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 7491 7492 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 7493 7494 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620) 7495 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620) 7496 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 7497 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 7498 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 7499 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 7500 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 7501 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 7502 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 7503 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 7504 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 7505 do {\ 7506 HWIO_INTLOCK(); \ 7507 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 7508 HWIO_INTFREE();\ 7509 } while (0) 7510 7511 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 7512 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 7513 7514 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 7515 7516 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624) 7517 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624) 7518 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 7519 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 7520 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 7521 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 7522 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 7523 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 7524 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 7525 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 7526 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 7527 do {\ 7528 HWIO_INTLOCK(); \ 7529 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 7530 HWIO_INTFREE();\ 7531 } while (0) 7532 7533 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 7534 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 7535 7536 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 7537 7538 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628) 7539 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628) 7540 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 7541 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 7542 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 7543 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 7544 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 7545 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 7546 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 7547 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 7548 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 7549 do {\ 7550 HWIO_INTLOCK(); \ 7551 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 7552 HWIO_INTFREE();\ 7553 } while (0) 7554 7555 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 7556 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 7557 7558 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 7559 7560 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c) 7561 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c) 7562 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 7563 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 7564 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 7565 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 7566 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 7567 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 7568 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 7569 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 7570 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 7571 do {\ 7572 HWIO_INTLOCK(); \ 7573 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 7574 HWIO_INTFREE();\ 7575 } while (0) 7576 7577 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 7578 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 7579 7580 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 7581 7582 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630) 7583 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630) 7584 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 7585 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 7586 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 7587 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 7588 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 7589 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 7590 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 7591 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 7592 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 7593 do {\ 7594 HWIO_INTLOCK(); \ 7595 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 7596 HWIO_INTFREE();\ 7597 } while (0) 7598 7599 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 7600 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 7601 7602 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 7603 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 7604 7605 //// Register REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG //// 7606 7607 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000634) 7608 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000634) 7609 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7610 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7611 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7612 in_dword_masked ( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7613 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7614 in_dword_masked ( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7615 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7616 out_dword( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7617 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7618 do {\ 7619 HWIO_INTLOCK(); \ 7620 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7621 HWIO_INTFREE();\ 7622 } while (0) 7623 7624 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7625 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7626 7627 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7628 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7629 7630 //// Register REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG //// 7631 7632 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000638) 7633 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000638) 7634 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7635 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7636 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7637 in_dword_masked ( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7638 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7639 in_dword_masked ( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7640 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7641 out_dword( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7642 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7643 do {\ 7644 HWIO_INTLOCK(); \ 7645 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7646 HWIO_INTFREE();\ 7647 } while (0) 7648 7649 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7650 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7651 7652 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7653 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7654 7655 //// Register REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG //// 7656 7657 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x0000063c) 7658 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x0000063c) 7659 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7660 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7661 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7662 in_dword_masked ( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7663 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7664 in_dword_masked ( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7665 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7666 out_dword( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7667 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7668 do {\ 7669 HWIO_INTLOCK(); \ 7670 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7671 HWIO_INTFREE();\ 7672 } while (0) 7673 7674 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7675 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7676 7677 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7678 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7679 7680 //// Register REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG //// 7681 7682 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000640) 7683 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000640) 7684 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7685 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7686 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7687 in_dword_masked ( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7688 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7689 in_dword_masked ( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7690 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7691 out_dword( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7692 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7693 do {\ 7694 HWIO_INTLOCK(); \ 7695 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7696 HWIO_INTFREE();\ 7697 } while (0) 7698 7699 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7700 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7701 7702 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7703 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7704 7705 //// Register REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG //// 7706 7707 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000644) 7708 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000644) 7709 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7710 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7711 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7712 in_dword_masked ( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7713 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7714 in_dword_masked ( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7715 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7716 out_dword( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7717 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7718 do {\ 7719 HWIO_INTLOCK(); \ 7720 out_dword_masked_ns(HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7721 HWIO_INTFREE();\ 7722 } while (0) 7723 7724 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7725 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7726 7727 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7728 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7729 7730 //// Register REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG //// 7731 7732 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000648) 7733 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000648) 7734 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7735 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7736 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7737 in_dword_masked ( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7738 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7739 in_dword_masked ( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7740 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7741 out_dword( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7742 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7743 do {\ 7744 HWIO_INTLOCK(); \ 7745 out_dword_masked_ns(HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7746 HWIO_INTFREE();\ 7747 } while (0) 7748 7749 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7750 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7751 7752 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7753 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7754 7755 //// Register REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG //// 7756 7757 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x0000064c) 7758 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x0000064c) 7759 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7760 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7761 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7762 in_dword_masked ( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7763 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7764 in_dword_masked ( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7765 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7766 out_dword( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7767 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7768 do {\ 7769 HWIO_INTLOCK(); \ 7770 out_dword_masked_ns(HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7771 HWIO_INTFREE();\ 7772 } while (0) 7773 7774 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7775 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7776 7777 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7778 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7779 7780 //// Register REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG //// 7781 7782 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000650) 7783 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000650) 7784 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f 7785 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 7786 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ 7787 in_dword_masked ( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_RMSK) 7788 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ 7789 in_dword_masked ( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) 7790 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ 7791 out_dword( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) 7792 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ 7793 do {\ 7794 HWIO_INTLOCK(); \ 7795 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ 7796 HWIO_INTFREE();\ 7797 } while (0) 7798 7799 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 7800 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 7801 7802 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f 7803 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 7804 7805 //// Register REO_R0_GXI_TESTBUS_LOWER //// 7806 7807 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000654) 7808 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000654) 7809 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 7810 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 7811 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 7812 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 7813 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 7814 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 7815 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 7816 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 7817 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 7818 do {\ 7819 HWIO_INTLOCK(); \ 7820 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 7821 HWIO_INTFREE();\ 7822 } while (0) 7823 7824 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 7825 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 7826 7827 //// Register REO_R0_GXI_TESTBUS_UPPER //// 7828 7829 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000658) 7830 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000658) 7831 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 7832 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 7833 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 7834 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 7835 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 7836 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 7837 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 7838 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 7839 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 7840 do {\ 7841 HWIO_INTLOCK(); \ 7842 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 7843 HWIO_INTFREE();\ 7844 } while (0) 7845 7846 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 7847 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 7848 7849 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 7850 7851 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000065c) 7852 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000065c) 7853 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 7854 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 7855 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 7856 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 7857 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 7858 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 7859 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 7860 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 7861 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 7862 do {\ 7863 HWIO_INTLOCK(); \ 7864 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 7865 HWIO_INTFREE();\ 7866 } while (0) 7867 7868 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 7869 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 7870 7871 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 7872 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 7873 7874 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 7875 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 7876 7877 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 7878 7879 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000660) 7880 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000660) 7881 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 7882 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 7883 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 7884 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 7885 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 7886 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 7887 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 7888 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 7889 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7890 do {\ 7891 HWIO_INTLOCK(); \ 7892 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 7893 HWIO_INTFREE();\ 7894 } while (0) 7895 7896 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7897 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7898 7899 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 7900 7901 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000664) 7902 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000664) 7903 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 7904 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 7905 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 7906 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 7907 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 7908 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 7909 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 7910 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 7911 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 7912 do {\ 7913 HWIO_INTLOCK(); \ 7914 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 7915 HWIO_INTFREE();\ 7916 } while (0) 7917 7918 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 7919 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 7920 7921 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 7922 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 7923 7924 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 7925 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 7926 7927 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 7928 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 7929 7930 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 7931 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 7932 7933 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 7934 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 7935 7936 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 7937 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 7938 7939 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 7940 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 7941 7942 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 7943 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 7944 7945 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 7946 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 7947 7948 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 7949 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 7950 7951 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 7952 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 7953 7954 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 7955 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 7956 7957 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7958 7959 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000668) 7960 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000668) 7961 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7962 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7963 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7964 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7965 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7966 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7967 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7968 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7969 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7970 do {\ 7971 HWIO_INTLOCK(); \ 7972 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7973 HWIO_INTFREE();\ 7974 } while (0) 7975 7976 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7977 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7978 7979 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7980 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7981 7982 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7983 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7984 7985 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7986 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7987 7988 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7989 7990 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000066c) 7991 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000066c) 7992 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7993 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7994 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7995 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7996 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7997 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7998 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7999 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 8000 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 8001 do {\ 8002 HWIO_INTLOCK(); \ 8003 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 8004 HWIO_INTFREE();\ 8005 } while (0) 8006 8007 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 8008 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 8009 8010 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 8011 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 8012 8013 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 8014 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 8015 8016 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 8017 8018 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000670) 8019 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000670) 8020 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 8021 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 8022 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 8023 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 8024 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 8025 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 8026 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 8027 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 8028 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 8029 do {\ 8030 HWIO_INTLOCK(); \ 8031 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 8032 HWIO_INTFREE();\ 8033 } while (0) 8034 8035 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 8036 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 8037 8038 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 8039 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 8040 8041 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 8042 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 8043 8044 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 8045 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 8046 8047 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 8048 8049 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000674) 8050 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000674) 8051 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 8052 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 8053 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 8054 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 8055 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 8056 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 8057 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 8058 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 8059 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 8060 do {\ 8061 HWIO_INTLOCK(); \ 8062 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 8063 HWIO_INTFREE();\ 8064 } while (0) 8065 8066 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 8067 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 8068 8069 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 8070 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 8071 8072 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 8073 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 8074 8075 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 8076 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 8077 8078 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 8079 8080 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000678) 8081 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000678) 8082 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 8083 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 8084 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 8085 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 8086 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 8087 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 8088 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 8089 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 8090 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 8091 do {\ 8092 HWIO_INTLOCK(); \ 8093 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 8094 HWIO_INTFREE();\ 8095 } while (0) 8096 8097 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 8098 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 8099 8100 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 8101 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 8102 8103 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 8104 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 8105 8106 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 8107 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 8108 8109 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 8110 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 8111 8112 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 8113 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 8114 8115 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 8116 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 8117 8118 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 8119 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 8120 8121 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 8122 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 8123 8124 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 8125 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 8126 8127 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 8128 8129 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000067c) 8130 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000067c) 8131 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 8132 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 8133 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 8134 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 8135 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 8136 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 8137 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 8138 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 8139 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 8140 do {\ 8141 HWIO_INTLOCK(); \ 8142 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 8143 HWIO_INTFREE();\ 8144 } while (0) 8145 8146 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 8147 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 8148 8149 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 8150 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 8151 8152 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 8153 8154 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000680) 8155 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000680) 8156 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 8157 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 8158 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 8159 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 8160 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 8161 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 8162 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 8163 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 8164 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 8165 do {\ 8166 HWIO_INTLOCK(); \ 8167 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 8168 HWIO_INTFREE();\ 8169 } while (0) 8170 8171 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 8172 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 8173 8174 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 8175 8176 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000684) 8177 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000684) 8178 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 8179 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 8180 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 8181 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 8182 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 8183 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 8184 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 8185 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 8186 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 8187 do {\ 8188 HWIO_INTLOCK(); \ 8189 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 8190 HWIO_INTFREE();\ 8191 } while (0) 8192 8193 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 8194 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 8195 8196 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 8197 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 8198 8199 //// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL //// 8200 8201 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000688) 8202 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000688) 8203 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 8204 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 8205 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 8206 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 8207 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 8208 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 8209 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 8210 out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 8211 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 8212 do {\ 8213 HWIO_INTLOCK(); \ 8214 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 8215 HWIO_INTFREE();\ 8216 } while (0) 8217 8218 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 8219 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 8220 8221 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 8222 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 8223 8224 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 8225 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 8226 8227 //// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL //// 8228 8229 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000068c) 8230 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000068c) 8231 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 8232 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 8233 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 8234 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 8235 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 8236 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 8237 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 8238 out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 8239 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 8240 do {\ 8241 HWIO_INTLOCK(); \ 8242 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 8243 HWIO_INTFREE();\ 8244 } while (0) 8245 8246 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 8247 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 8248 8249 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 8250 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 8251 8252 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 8253 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 8254 8255 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 8256 8257 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000690) 8258 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000690) 8259 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 8260 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 8261 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 8262 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 8263 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 8264 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 8265 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 8266 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 8267 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 8268 do {\ 8269 HWIO_INTLOCK(); \ 8270 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 8271 HWIO_INTFREE();\ 8272 } while (0) 8273 8274 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 8275 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 8276 8277 //// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 8278 8279 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000694) 8280 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000694) 8281 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 8282 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 8283 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 8284 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 8285 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 8286 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 8287 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 8288 out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 8289 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 8290 do {\ 8291 HWIO_INTLOCK(); \ 8292 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 8293 HWIO_INTFREE();\ 8294 } while (0) 8295 8296 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 8297 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 8298 8299 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 8300 8301 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000698) 8302 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000698) 8303 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 8304 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 8305 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 8306 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 8307 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 8308 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 8309 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 8310 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 8311 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 8312 do {\ 8313 HWIO_INTLOCK(); \ 8314 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 8315 HWIO_INTFREE();\ 8316 } while (0) 8317 8318 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 8319 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 8320 8321 //// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 8322 8323 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000069c) 8324 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000069c) 8325 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 8326 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 8327 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 8328 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 8329 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 8330 in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 8331 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 8332 out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 8333 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 8334 do {\ 8335 HWIO_INTLOCK(); \ 8336 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 8337 HWIO_INTFREE();\ 8338 } while (0) 8339 8340 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 8341 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 8342 8343 //// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 8344 8345 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000006a0) 8346 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000006a0) 8347 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 8348 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 8349 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 8350 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 8351 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 8352 in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 8353 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 8354 out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 8355 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 8356 do {\ 8357 HWIO_INTLOCK(); \ 8358 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 8359 HWIO_INTFREE();\ 8360 } while (0) 8361 8362 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 8363 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 8364 8365 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 8366 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 8367 8368 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 8369 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 8370 8371 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 8372 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 8373 8374 //// Register REO_R0_CACHE_CTL_CONFIG //// 8375 8376 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x000006a4) 8377 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x000006a4) 8378 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff 8379 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 8380 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 8381 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 8382 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 8383 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 8384 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 8385 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 8386 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 8387 do {\ 8388 HWIO_INTLOCK(); \ 8389 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 8390 HWIO_INTFREE();\ 8391 } while (0) 8392 8393 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 8394 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18 8395 8396 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000 8397 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17 8398 8399 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000 8400 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16 8401 8402 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000 8403 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15 8404 8405 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000 8406 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14 8407 8408 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000 8409 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13 8410 8411 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000 8412 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12 8413 8414 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000 8415 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11 8416 8417 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00 8418 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9 8419 8420 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff 8421 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 8422 8423 //// Register REO_R0_CACHE_CTL_CONTROL //// 8424 8425 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x000006a8) 8426 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x000006a8) 8427 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003 8428 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 8429 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 8430 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 8431 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 8432 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 8433 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 8434 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 8435 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 8436 do {\ 8437 HWIO_INTLOCK(); \ 8438 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 8439 HWIO_INTFREE();\ 8440 } while (0) 8441 8442 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002 8443 #define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1 8444 8445 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 8446 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 8447 8448 //// Register REO_R0_CACHE_CTL_CONFIG_SET //// 8449 8450 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x000006ac) 8451 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x000006ac) 8452 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff 8453 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0 8454 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ 8455 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK) 8456 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ 8457 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) 8458 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \ 8459 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val) 8460 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ 8461 do {\ 8462 HWIO_INTLOCK(); \ 8463 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \ 8464 HWIO_INTFREE();\ 8465 } while (0) 8466 8467 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x01ffffff 8468 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0x0 8469 8470 //// Register REO_R0_CACHE_CTL_SET_SIZE //// 8471 8472 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x000006b0) 8473 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x000006b0) 8474 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff 8475 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0 8476 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ 8477 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK) 8478 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ 8479 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) 8480 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \ 8481 out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val) 8482 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ 8483 do {\ 8484 HWIO_INTLOCK(); \ 8485 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \ 8486 HWIO_INTFREE();\ 8487 } while (0) 8488 8489 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff 8490 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0 8491 8492 //// Register REO_R0_CLK_GATE_CTRL //// 8493 8494 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x000006b4) 8495 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x000006b4) 8496 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 8497 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 8498 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 8499 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 8500 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 8501 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 8502 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 8503 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 8504 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 8505 do {\ 8506 HWIO_INTLOCK(); \ 8507 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 8508 HWIO_INTFREE();\ 8509 } while (0) 8510 8511 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 8512 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 8513 8514 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 8515 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 8516 8517 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 8518 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 8519 8520 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 8521 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 8522 8523 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 8524 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 8525 8526 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 8527 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 8528 8529 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x00001000 8530 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 0xc 8531 8532 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x00000800 8533 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 0xb 8534 8535 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 8536 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 8537 8538 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 8539 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 8540 8541 //// Register REO_R0_EVENTMASK_IX_0 //// 8542 8543 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x000006b8) 8544 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x000006b8) 8545 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 8546 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 8547 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 8548 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 8549 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 8550 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 8551 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 8552 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 8553 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 8554 do {\ 8555 HWIO_INTLOCK(); \ 8556 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 8557 HWIO_INTFREE();\ 8558 } while (0) 8559 8560 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 8561 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 8562 8563 //// Register REO_R0_EVENTMASK_IX_1 //// 8564 8565 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x000006bc) 8566 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x000006bc) 8567 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 8568 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 8569 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 8570 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 8571 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 8572 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 8573 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 8574 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 8575 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 8576 do {\ 8577 HWIO_INTLOCK(); \ 8578 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 8579 HWIO_INTFREE();\ 8580 } while (0) 8581 8582 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 8583 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 8584 8585 //// Register REO_R0_EVENTMASK_IX_2 //// 8586 8587 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006c0) 8588 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006c0) 8589 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 8590 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 8591 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 8592 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 8593 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 8594 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 8595 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 8596 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 8597 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 8598 do {\ 8599 HWIO_INTLOCK(); \ 8600 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 8601 HWIO_INTFREE();\ 8602 } while (0) 8603 8604 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 8605 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 8606 8607 //// Register REO_R0_EVENTMASK_IX_3 //// 8608 8609 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006c4) 8610 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006c4) 8611 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 8612 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 8613 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 8614 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 8615 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 8616 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 8617 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 8618 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 8619 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 8620 do {\ 8621 HWIO_INTLOCK(); \ 8622 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 8623 HWIO_INTFREE();\ 8624 } while (0) 8625 8626 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 8627 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 8628 8629 //// Register REO_R1_MISC_DEBUG_CTRL //// 8630 8631 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 8632 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 8633 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff 8634 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 8635 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 8636 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 8637 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 8638 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 8639 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 8640 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 8641 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 8642 do {\ 8643 HWIO_INTLOCK(); \ 8644 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 8645 HWIO_INTFREE();\ 8646 } while (0) 8647 8648 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 8649 #define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 0x1f 8650 8651 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 8652 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e 8653 8654 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 8655 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 8656 8657 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 8658 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 8659 8660 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 8661 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 8662 8663 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 8664 8665 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 8666 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 8667 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 8668 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 8669 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 8670 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 8671 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 8672 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 8673 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 8674 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 8675 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 8676 do {\ 8677 HWIO_INTLOCK(); \ 8678 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 8679 HWIO_INTFREE();\ 8680 } while (0) 8681 8682 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 8683 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 8684 8685 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 8686 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 8687 8688 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 8689 8690 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 8691 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 8692 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff 8693 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 8694 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 8695 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 8696 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 8697 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 8698 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 8699 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 8700 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 8701 do {\ 8702 HWIO_INTLOCK(); \ 8703 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 8704 HWIO_INTFREE();\ 8705 } while (0) 8706 8707 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800 8708 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb 8709 8710 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400 8711 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa 8712 8713 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200 8714 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9 8715 8716 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff 8717 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 8718 8719 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 8720 8721 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 8722 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 8723 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 8724 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 8725 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 8726 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 8727 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 8728 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 8729 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 8730 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 8731 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 8732 do {\ 8733 HWIO_INTLOCK(); \ 8734 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 8735 HWIO_INTFREE();\ 8736 } while (0) 8737 8738 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 8739 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 8740 8741 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 8742 8743 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 8744 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 8745 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 8746 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 8747 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 8748 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 8749 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 8750 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 8751 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 8752 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 8753 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 8754 do {\ 8755 HWIO_INTLOCK(); \ 8756 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 8757 HWIO_INTFREE();\ 8758 } while (0) 8759 8760 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 8761 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 8762 8763 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 8764 8765 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 8766 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 8767 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 8768 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 8769 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 8770 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 8771 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 8772 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 8773 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 8774 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 8775 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 8776 do {\ 8777 HWIO_INTLOCK(); \ 8778 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 8779 HWIO_INTFREE();\ 8780 } while (0) 8781 8782 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 8783 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 8784 8785 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 8786 8787 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 8788 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 8789 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff 8790 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 8791 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 8792 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 8793 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 8794 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 8795 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 8796 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 8797 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 8798 do {\ 8799 HWIO_INTLOCK(); \ 8800 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 8801 HWIO_INTFREE();\ 8802 } while (0) 8803 8804 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff 8805 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 8806 8807 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 8808 8809 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 8810 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 8811 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 8812 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 8813 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 8814 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 8815 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 8816 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 8817 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 8818 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 8819 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 8820 do {\ 8821 HWIO_INTLOCK(); \ 8822 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 8823 HWIO_INTFREE();\ 8824 } while (0) 8825 8826 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 8827 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 8828 8829 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 8830 8831 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 8832 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 8833 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff 8834 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 8835 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 8836 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 8837 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 8838 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 8839 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 8840 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 8841 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 8842 do {\ 8843 HWIO_INTLOCK(); \ 8844 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 8845 HWIO_INTFREE();\ 8846 } while (0) 8847 8848 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00 8849 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa 8850 8851 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff 8852 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 8853 8854 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 //// 8855 8856 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024) 8857 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024) 8858 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff 8859 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0 8860 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ 8861 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK) 8862 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ 8863 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) 8864 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \ 8865 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val) 8866 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ 8867 do {\ 8868 HWIO_INTLOCK(); \ 8869 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \ 8870 HWIO_INTFREE();\ 8871 } while (0) 8872 8873 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00 8874 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa 8875 8876 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff 8877 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0 8878 8879 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 //// 8880 8881 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028) 8882 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028) 8883 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff 8884 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0 8885 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ 8886 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK) 8887 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ 8888 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) 8889 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \ 8890 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val) 8891 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ 8892 do {\ 8893 HWIO_INTLOCK(); \ 8894 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \ 8895 HWIO_INTFREE();\ 8896 } while (0) 8897 8898 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00 8899 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa 8900 8901 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff 8902 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0 8903 8904 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 //// 8905 8906 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c) 8907 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c) 8908 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff 8909 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0 8910 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ 8911 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK) 8912 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ 8913 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) 8914 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \ 8915 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val) 8916 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ 8917 do {\ 8918 HWIO_INTLOCK(); \ 8919 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \ 8920 HWIO_INTFREE();\ 8921 } while (0) 8922 8923 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00 8924 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa 8925 8926 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff 8927 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0 8928 8929 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW //// 8930 8931 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030) 8932 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030) 8933 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff 8934 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0 8935 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ 8936 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK) 8937 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ 8938 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) 8939 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \ 8940 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val) 8941 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ 8942 do {\ 8943 HWIO_INTLOCK(); \ 8944 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \ 8945 HWIO_INTFREE();\ 8946 } while (0) 8947 8948 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff 8949 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0 8950 8951 //// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH //// 8952 8953 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034) 8954 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034) 8955 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff 8956 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0 8957 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ 8958 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK) 8959 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ 8960 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) 8961 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \ 8962 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val) 8963 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ 8964 do {\ 8965 HWIO_INTLOCK(); \ 8966 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \ 8967 HWIO_INTFREE();\ 8968 } while (0) 8969 8970 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff 8971 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0 8972 8973 //// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER //// 8974 8975 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038) 8976 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038) 8977 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff 8978 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0 8979 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ 8980 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK) 8981 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ 8982 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) 8983 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \ 8984 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val) 8985 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ 8986 do {\ 8987 HWIO_INTLOCK(); \ 8988 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \ 8989 HWIO_INTFREE();\ 8990 } while (0) 8991 8992 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00 8993 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa 8994 8995 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff 8996 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0 8997 8998 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 8999 9000 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c) 9001 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c) 9002 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 9003 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 9004 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 9005 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 9006 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 9007 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 9008 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 9009 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 9010 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 9011 do {\ 9012 HWIO_INTLOCK(); \ 9013 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 9014 HWIO_INTFREE();\ 9015 } while (0) 9016 9017 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 9018 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 9019 9020 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 //// 9021 9022 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) (x+0x00002040) 9023 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) (x+0x00002040) 9024 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x000007ff 9025 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT 0 9026 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ 9027 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK) 9028 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \ 9029 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask) 9030 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val) \ 9031 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val) 9032 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \ 9033 do {\ 9034 HWIO_INTLOCK(); \ 9035 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \ 9036 HWIO_INTFREE();\ 9037 } while (0) 9038 9039 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x000007f8 9040 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 0x3 9041 9042 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004 9043 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 0x2 9044 9045 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002 9046 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 0x1 9047 9048 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x00000001 9049 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0x0 9050 9051 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 //// 9052 9053 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) (x+0x00002044) 9054 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) (x+0x00002044) 9055 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff 9056 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT 0 9057 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ 9058 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK) 9059 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \ 9060 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask) 9061 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val) \ 9062 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val) 9063 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \ 9064 do {\ 9065 HWIO_INTLOCK(); \ 9066 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \ 9067 HWIO_INTFREE();\ 9068 } while (0) 9069 9070 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff 9071 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0x0 9072 9073 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 //// 9074 9075 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) (x+0x00002048) 9076 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) (x+0x00002048) 9077 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0x000000ff 9078 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT 0 9079 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ 9080 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK) 9081 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \ 9082 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask) 9083 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val) \ 9084 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val) 9085 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \ 9086 do {\ 9087 HWIO_INTLOCK(); \ 9088 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \ 9089 HWIO_INTFREE();\ 9090 } while (0) 9091 9092 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff 9093 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0x0 9094 9095 //// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS //// 9096 9097 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) (x+0x0000204c) 9098 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) (x+0x0000204c) 9099 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff 9100 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT 0 9101 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ 9102 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK) 9103 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \ 9104 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask) 9105 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val) \ 9106 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val) 9107 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \ 9108 do {\ 9109 HWIO_INTLOCK(); \ 9110 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \ 9111 HWIO_INTFREE();\ 9112 } while (0) 9113 9114 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 9115 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 0x16 9116 9117 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x003ff000 9118 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 0xc 9119 9120 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800 9121 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 0xb 9122 9123 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600 9124 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 0x9 9125 9126 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0 9127 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 0x5 9128 9129 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c 9130 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 0x2 9131 9132 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002 9133 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 0x1 9134 9135 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x00000001 9136 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0x0 9137 9138 //// Register REO_R1_END_OF_TEST_CHECK //// 9139 9140 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002050) 9141 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002050) 9142 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 9143 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 9144 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 9145 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 9146 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 9147 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 9148 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 9149 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 9150 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 9151 do {\ 9152 HWIO_INTLOCK(); \ 9153 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 9154 HWIO_INTFREE();\ 9155 } while (0) 9156 9157 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 9158 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 9159 9160 //// Register REO_R1_SM_ALL_IDLE //// 9161 9162 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002054) 9163 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002054) 9164 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 9165 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 9166 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 9167 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 9168 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 9169 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 9170 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 9171 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 9172 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 9173 do {\ 9174 HWIO_INTLOCK(); \ 9175 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 9176 HWIO_INTFREE();\ 9177 } while (0) 9178 9179 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 9180 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 9181 9182 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 9183 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 9184 9185 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 9186 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 9187 9188 //// Register REO_R1_TESTBUS_CTRL //// 9189 9190 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002058) 9191 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002058) 9192 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 9193 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 9194 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 9195 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 9196 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 9197 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 9198 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 9199 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 9200 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 9201 do {\ 9202 HWIO_INTLOCK(); \ 9203 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 9204 HWIO_INTFREE();\ 9205 } while (0) 9206 9207 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 9208 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 9209 9210 //// Register REO_R1_TESTBUS_LOWER //// 9211 9212 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000205c) 9213 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000205c) 9214 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 9215 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 9216 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 9217 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 9218 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 9219 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 9220 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 9221 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 9222 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 9223 do {\ 9224 HWIO_INTLOCK(); \ 9225 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 9226 HWIO_INTFREE();\ 9227 } while (0) 9228 9229 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 9230 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 9231 9232 //// Register REO_R1_TESTBUS_HIGHER //// 9233 9234 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002060) 9235 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002060) 9236 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 9237 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 9238 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 9239 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 9240 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 9241 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 9242 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 9243 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 9244 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 9245 do {\ 9246 HWIO_INTLOCK(); \ 9247 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 9248 HWIO_INTFREE();\ 9249 } while (0) 9250 9251 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 9252 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 9253 9254 //// Register REO_R1_SM_STATES_IX_0 //// 9255 9256 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002064) 9257 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002064) 9258 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 9259 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 9260 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 9261 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 9262 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 9263 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 9264 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 9265 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 9266 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 9267 do {\ 9268 HWIO_INTLOCK(); \ 9269 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 9270 HWIO_INTFREE();\ 9271 } while (0) 9272 9273 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 9274 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 9275 9276 //// Register REO_R1_SM_STATES_IX_1 //// 9277 9278 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002068) 9279 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002068) 9280 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 9281 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 9282 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 9283 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 9284 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 9285 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 9286 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 9287 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 9288 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 9289 do {\ 9290 HWIO_INTLOCK(); \ 9291 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 9292 HWIO_INTFREE();\ 9293 } while (0) 9294 9295 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 9296 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 9297 9298 //// Register REO_R1_SM_STATES_IX_2 //// 9299 9300 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000206c) 9301 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000206c) 9302 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 9303 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 9304 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 9305 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 9306 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 9307 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 9308 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 9309 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 9310 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 9311 do {\ 9312 HWIO_INTLOCK(); \ 9313 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 9314 HWIO_INTFREE();\ 9315 } while (0) 9316 9317 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 9318 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 9319 9320 //// Register REO_R1_SM_STATES_IX_3 //// 9321 9322 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002070) 9323 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002070) 9324 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 9325 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 9326 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 9327 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 9328 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 9329 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 9330 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 9331 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 9332 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 9333 do {\ 9334 HWIO_INTLOCK(); \ 9335 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 9336 HWIO_INTFREE();\ 9337 } while (0) 9338 9339 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 9340 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 9341 9342 //// Register REO_R1_SM_STATES_IX_4 //// 9343 9344 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002074) 9345 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002074) 9346 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 9347 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 9348 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 9349 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 9350 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 9351 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 9352 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 9353 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 9354 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 9355 do {\ 9356 HWIO_INTLOCK(); \ 9357 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 9358 HWIO_INTFREE();\ 9359 } while (0) 9360 9361 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 9362 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 9363 9364 //// Register REO_R1_SM_STATES_IX_5 //// 9365 9366 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002078) 9367 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002078) 9368 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 9369 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 9370 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 9371 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 9372 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 9373 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 9374 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 9375 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 9376 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 9377 do {\ 9378 HWIO_INTLOCK(); \ 9379 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 9380 HWIO_INTFREE();\ 9381 } while (0) 9382 9383 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 9384 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 9385 9386 //// Register REO_R1_SM_STATES_IX_6 //// 9387 9388 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000207c) 9389 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000207c) 9390 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 9391 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 9392 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 9393 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 9394 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 9395 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 9396 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 9397 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 9398 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 9399 do {\ 9400 HWIO_INTLOCK(); \ 9401 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 9402 HWIO_INTFREE();\ 9403 } while (0) 9404 9405 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 9406 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 9407 9408 //// Register REO_R1_IDLE_STATES_IX_0 //// 9409 9410 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002080) 9411 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002080) 9412 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 9413 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 9414 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 9415 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 9416 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 9417 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 9418 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 9419 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 9420 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 9421 do {\ 9422 HWIO_INTLOCK(); \ 9423 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 9424 HWIO_INTFREE();\ 9425 } while (0) 9426 9427 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 9428 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 9429 9430 //// Register REO_R1_INVALID_APB_ACCESS //// 9431 9432 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002084) 9433 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002084) 9434 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 9435 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 9436 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 9437 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 9438 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 9439 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 9440 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 9441 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 9442 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 9443 do {\ 9444 HWIO_INTLOCK(); \ 9445 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 9446 HWIO_INTFREE();\ 9447 } while (0) 9448 9449 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 9450 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 9451 9452 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 9453 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 9454 9455 //// Register REO_R2_RXDMA2REO0_RING_HP //// 9456 9457 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 9458 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 9459 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 9460 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 9461 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 9462 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 9463 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 9464 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 9465 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 9466 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 9467 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 9468 do {\ 9469 HWIO_INTLOCK(); \ 9470 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 9471 HWIO_INTFREE();\ 9472 } while (0) 9473 9474 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9475 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 9476 9477 //// Register REO_R2_RXDMA2REO0_RING_TP //// 9478 9479 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 9480 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 9481 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 9482 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 9483 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 9484 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 9485 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 9486 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 9487 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 9488 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 9489 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 9490 do {\ 9491 HWIO_INTLOCK(); \ 9492 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 9493 HWIO_INTFREE();\ 9494 } while (0) 9495 9496 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9497 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 9498 9499 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 9500 9501 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003008) 9502 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003008) 9503 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 9504 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 9505 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 9506 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 9507 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 9508 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 9509 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 9510 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 9511 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 9512 do {\ 9513 HWIO_INTLOCK(); \ 9514 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 9515 HWIO_INTFREE();\ 9516 } while (0) 9517 9518 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9519 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 9520 9521 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 9522 9523 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000300c) 9524 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000300c) 9525 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 9526 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 9527 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 9528 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 9529 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 9530 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 9531 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 9532 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 9533 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 9534 do {\ 9535 HWIO_INTLOCK(); \ 9536 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 9537 HWIO_INTFREE();\ 9538 } while (0) 9539 9540 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9541 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 9542 9543 //// Register REO_R2_REO_CMD_RING_HP //// 9544 9545 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003010) 9546 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003010) 9547 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 9548 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 9549 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 9550 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 9551 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 9552 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 9553 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 9554 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 9555 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 9556 do {\ 9557 HWIO_INTLOCK(); \ 9558 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 9559 HWIO_INTFREE();\ 9560 } while (0) 9561 9562 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9563 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 9564 9565 //// Register REO_R2_REO_CMD_RING_TP //// 9566 9567 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003014) 9568 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003014) 9569 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 9570 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 9571 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 9572 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 9573 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 9574 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 9575 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 9576 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 9577 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 9578 do {\ 9579 HWIO_INTLOCK(); \ 9580 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 9581 HWIO_INTFREE();\ 9582 } while (0) 9583 9584 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9585 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 9586 9587 //// Register REO_R2_SW2REO_RING_HP //// 9588 9589 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003018) 9590 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003018) 9591 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 9592 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 9593 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 9594 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 9595 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 9596 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 9597 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 9598 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 9599 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 9600 do {\ 9601 HWIO_INTLOCK(); \ 9602 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 9603 HWIO_INTFREE();\ 9604 } while (0) 9605 9606 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9607 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 9608 9609 //// Register REO_R2_SW2REO_RING_TP //// 9610 9611 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000301c) 9612 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000301c) 9613 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 9614 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 9615 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 9616 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 9617 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 9618 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 9619 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 9620 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 9621 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 9622 do {\ 9623 HWIO_INTLOCK(); \ 9624 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 9625 HWIO_INTFREE();\ 9626 } while (0) 9627 9628 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9629 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 9630 9631 //// Register REO_R2_SW2REO1_RING_HP //// 9632 9633 #define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003020) 9634 #define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003020) 9635 #define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff 9636 #define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0 9637 #define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ 9638 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK) 9639 #define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ 9640 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) 9641 #define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \ 9642 out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val) 9643 #define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ 9644 do {\ 9645 HWIO_INTLOCK(); \ 9646 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \ 9647 HWIO_INTFREE();\ 9648 } while (0) 9649 9650 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 9651 #define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0 9652 9653 //// Register REO_R2_SW2REO1_RING_TP //// 9654 9655 #define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003024) 9656 #define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003024) 9657 #define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff 9658 #define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0 9659 #define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ 9660 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK) 9661 #define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ 9662 in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) 9663 #define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \ 9664 out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val) 9665 #define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ 9666 do {\ 9667 HWIO_INTLOCK(); \ 9668 out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \ 9669 HWIO_INTFREE();\ 9670 } while (0) 9671 9672 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 9673 #define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0 9674 9675 //// Register REO_R2_REO2SW1_RING_HP //// 9676 9677 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003028) 9678 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003028) 9679 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff 9680 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 9681 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 9682 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 9683 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 9684 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 9685 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 9686 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 9687 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 9688 do {\ 9689 HWIO_INTLOCK(); \ 9690 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 9691 HWIO_INTFREE();\ 9692 } while (0) 9693 9694 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff 9695 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 9696 9697 //// Register REO_R2_REO2SW1_RING_TP //// 9698 9699 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000302c) 9700 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000302c) 9701 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff 9702 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 9703 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 9704 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 9705 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 9706 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 9707 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 9708 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 9709 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 9710 do {\ 9711 HWIO_INTLOCK(); \ 9712 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 9713 HWIO_INTFREE();\ 9714 } while (0) 9715 9716 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff 9717 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 9718 9719 //// Register REO_R2_REO2SW2_RING_HP //// 9720 9721 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003030) 9722 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003030) 9723 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff 9724 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 9725 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 9726 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 9727 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 9728 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 9729 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 9730 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 9731 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 9732 do {\ 9733 HWIO_INTLOCK(); \ 9734 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 9735 HWIO_INTFREE();\ 9736 } while (0) 9737 9738 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff 9739 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 9740 9741 //// Register REO_R2_REO2SW2_RING_TP //// 9742 9743 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003034) 9744 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003034) 9745 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff 9746 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 9747 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 9748 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 9749 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 9750 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 9751 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 9752 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 9753 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 9754 do {\ 9755 HWIO_INTLOCK(); \ 9756 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 9757 HWIO_INTFREE();\ 9758 } while (0) 9759 9760 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff 9761 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 9762 9763 //// Register REO_R2_REO2SW3_RING_HP //// 9764 9765 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003038) 9766 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003038) 9767 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff 9768 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 9769 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 9770 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 9771 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 9772 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 9773 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 9774 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 9775 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 9776 do {\ 9777 HWIO_INTLOCK(); \ 9778 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 9779 HWIO_INTFREE();\ 9780 } while (0) 9781 9782 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff 9783 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 9784 9785 //// Register REO_R2_REO2SW3_RING_TP //// 9786 9787 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000303c) 9788 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000303c) 9789 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff 9790 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 9791 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 9792 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 9793 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 9794 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 9795 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 9796 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 9797 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 9798 do {\ 9799 HWIO_INTLOCK(); \ 9800 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 9801 HWIO_INTFREE();\ 9802 } while (0) 9803 9804 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff 9805 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 9806 9807 //// Register REO_R2_REO2SW4_RING_HP //// 9808 9809 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003040) 9810 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003040) 9811 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff 9812 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 9813 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 9814 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 9815 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 9816 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 9817 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 9818 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 9819 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 9820 do {\ 9821 HWIO_INTLOCK(); \ 9822 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 9823 HWIO_INTFREE();\ 9824 } while (0) 9825 9826 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff 9827 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 9828 9829 //// Register REO_R2_REO2SW4_RING_TP //// 9830 9831 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003044) 9832 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003044) 9833 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff 9834 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 9835 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 9836 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 9837 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 9838 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 9839 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 9840 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 9841 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 9842 do {\ 9843 HWIO_INTLOCK(); \ 9844 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 9845 HWIO_INTFREE();\ 9846 } while (0) 9847 9848 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff 9849 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 9850 9851 //// Register REO_R2_REO2SW5_RING_HP //// 9852 9853 #define HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x) (x+0x00003048) 9854 #define HWIO_REO_R2_REO2SW5_RING_HP_PHYS(x) (x+0x00003048) 9855 #define HWIO_REO_R2_REO2SW5_RING_HP_RMSK 0x000fffff 9856 #define HWIO_REO_R2_REO2SW5_RING_HP_SHFT 0 9857 #define HWIO_REO_R2_REO2SW5_RING_HP_IN(x) \ 9858 in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW5_RING_HP_RMSK) 9859 #define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, mask) \ 9860 in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), mask) 9861 #define HWIO_REO_R2_REO2SW5_RING_HP_OUT(x, val) \ 9862 out_dword( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), val) 9863 #define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x, mask, val) \ 9864 do {\ 9865 HWIO_INTLOCK(); \ 9866 out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW5_RING_HP_IN(x)); \ 9867 HWIO_INTFREE();\ 9868 } while (0) 9869 9870 #define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_BMSK 0x000fffff 9871 #define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_SHFT 0x0 9872 9873 //// Register REO_R2_REO2SW5_RING_TP //// 9874 9875 #define HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x) (x+0x0000304c) 9876 #define HWIO_REO_R2_REO2SW5_RING_TP_PHYS(x) (x+0x0000304c) 9877 #define HWIO_REO_R2_REO2SW5_RING_TP_RMSK 0x000fffff 9878 #define HWIO_REO_R2_REO2SW5_RING_TP_SHFT 0 9879 #define HWIO_REO_R2_REO2SW5_RING_TP_IN(x) \ 9880 in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW5_RING_TP_RMSK) 9881 #define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, mask) \ 9882 in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), mask) 9883 #define HWIO_REO_R2_REO2SW5_RING_TP_OUT(x, val) \ 9884 out_dword( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), val) 9885 #define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x, mask, val) \ 9886 do {\ 9887 HWIO_INTLOCK(); \ 9888 out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW5_RING_TP_IN(x)); \ 9889 HWIO_INTFREE();\ 9890 } while (0) 9891 9892 #define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_BMSK 0x000fffff 9893 #define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_SHFT 0x0 9894 9895 //// Register REO_R2_REO2SW6_RING_HP //// 9896 9897 #define HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x) (x+0x00003050) 9898 #define HWIO_REO_R2_REO2SW6_RING_HP_PHYS(x) (x+0x00003050) 9899 #define HWIO_REO_R2_REO2SW6_RING_HP_RMSK 0x000fffff 9900 #define HWIO_REO_R2_REO2SW6_RING_HP_SHFT 0 9901 #define HWIO_REO_R2_REO2SW6_RING_HP_IN(x) \ 9902 in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW6_RING_HP_RMSK) 9903 #define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, mask) \ 9904 in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), mask) 9905 #define HWIO_REO_R2_REO2SW6_RING_HP_OUT(x, val) \ 9906 out_dword( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), val) 9907 #define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x, mask, val) \ 9908 do {\ 9909 HWIO_INTLOCK(); \ 9910 out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW6_RING_HP_IN(x)); \ 9911 HWIO_INTFREE();\ 9912 } while (0) 9913 9914 #define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_BMSK 0x000fffff 9915 #define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_SHFT 0x0 9916 9917 //// Register REO_R2_REO2SW6_RING_TP //// 9918 9919 #define HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x) (x+0x00003054) 9920 #define HWIO_REO_R2_REO2SW6_RING_TP_PHYS(x) (x+0x00003054) 9921 #define HWIO_REO_R2_REO2SW6_RING_TP_RMSK 0x000fffff 9922 #define HWIO_REO_R2_REO2SW6_RING_TP_SHFT 0 9923 #define HWIO_REO_R2_REO2SW6_RING_TP_IN(x) \ 9924 in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW6_RING_TP_RMSK) 9925 #define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, mask) \ 9926 in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), mask) 9927 #define HWIO_REO_R2_REO2SW6_RING_TP_OUT(x, val) \ 9928 out_dword( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), val) 9929 #define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x, mask, val) \ 9930 do {\ 9931 HWIO_INTLOCK(); \ 9932 out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW6_RING_TP_IN(x)); \ 9933 HWIO_INTFREE();\ 9934 } while (0) 9935 9936 #define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_BMSK 0x000fffff 9937 #define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_SHFT 0x0 9938 9939 //// Register REO_R2_REO2TCL_RING_HP //// 9940 9941 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058) 9942 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058) 9943 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff 9944 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 9945 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 9946 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 9947 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 9948 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 9949 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 9950 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 9951 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 9952 do {\ 9953 HWIO_INTLOCK(); \ 9954 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 9955 HWIO_INTFREE();\ 9956 } while (0) 9957 9958 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff 9959 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 9960 9961 //// Register REO_R2_REO2TCL_RING_TP //// 9962 9963 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c) 9964 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c) 9965 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff 9966 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 9967 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 9968 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 9969 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 9970 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 9971 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 9972 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 9973 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 9974 do {\ 9975 HWIO_INTLOCK(); \ 9976 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 9977 HWIO_INTFREE();\ 9978 } while (0) 9979 9980 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff 9981 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 9982 9983 //// Register REO_R2_REO2FW_RING_HP //// 9984 9985 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060) 9986 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060) 9987 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff 9988 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 9989 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 9990 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 9991 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 9992 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 9993 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 9994 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 9995 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 9996 do {\ 9997 HWIO_INTLOCK(); \ 9998 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 9999 HWIO_INTFREE();\ 10000 } while (0) 10001 10002 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff 10003 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 10004 10005 //// Register REO_R2_REO2FW_RING_TP //// 10006 10007 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064) 10008 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064) 10009 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff 10010 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 10011 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 10012 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 10013 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 10014 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 10015 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 10016 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 10017 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 10018 do {\ 10019 HWIO_INTLOCK(); \ 10020 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 10021 HWIO_INTFREE();\ 10022 } while (0) 10023 10024 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff 10025 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 10026 10027 //// Register REO_R2_REO_RELEASE_RING_HP //// 10028 10029 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068) 10030 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068) 10031 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 10032 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 10033 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 10034 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 10035 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 10036 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 10037 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 10038 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 10039 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 10040 do {\ 10041 HWIO_INTLOCK(); \ 10042 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 10043 HWIO_INTFREE();\ 10044 } while (0) 10045 10046 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 10047 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 10048 10049 //// Register REO_R2_REO_RELEASE_RING_TP //// 10050 10051 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c) 10052 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c) 10053 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 10054 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 10055 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 10056 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 10057 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 10058 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 10059 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 10060 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 10061 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 10062 do {\ 10063 HWIO_INTLOCK(); \ 10064 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 10065 HWIO_INTFREE();\ 10066 } while (0) 10067 10068 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 10069 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 10070 10071 //// Register REO_R2_REO_STATUS_RING_HP //// 10072 10073 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070) 10074 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070) 10075 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 10076 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 10077 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 10078 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 10079 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 10080 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 10081 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 10082 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 10083 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 10084 do {\ 10085 HWIO_INTLOCK(); \ 10086 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 10087 HWIO_INTFREE();\ 10088 } while (0) 10089 10090 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 10091 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 10092 10093 //// Register REO_R2_REO_STATUS_RING_TP //// 10094 10095 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074) 10096 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074) 10097 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 10098 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 10099 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 10100 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 10101 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 10102 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 10103 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 10104 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 10105 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 10106 do {\ 10107 HWIO_INTLOCK(); \ 10108 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 10109 HWIO_INTFREE();\ 10110 } while (0) 10111 10112 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 10113 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 10114 10115 10116 #endif 10117 10118