1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/12/2019 22 // User Name:pparekh 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 29 #define __MAC_TCL_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "mac_tcl_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block MAC_TCL_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 45 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 48 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 49 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 50 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 51 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 52 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 53 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 55 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 56 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 65 66 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 67 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 68 69 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 70 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 73 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 74 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 75 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 76 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 77 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 78 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 80 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 81 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 82 do {\ 83 HWIO_INTLOCK(); \ 84 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 85 HWIO_INTFREE();\ 86 } while (0) 87 88 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 90 91 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 92 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 93 94 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 95 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 98 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 99 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 100 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 101 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 102 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 103 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 105 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 106 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 107 do {\ 108 HWIO_INTLOCK(); \ 109 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 110 HWIO_INTFREE();\ 111 } while (0) 112 113 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 115 116 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 117 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 118 119 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 120 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 123 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 124 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 125 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 126 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 127 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 128 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 130 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 131 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 132 do {\ 133 HWIO_INTLOCK(); \ 134 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 135 HWIO_INTFREE();\ 136 } while (0) 137 138 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 140 141 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 142 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 143 144 //// Register TCL_R0_SW2TCL_CREDIT_RING_CTRL //// 145 146 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) (x+0x00000010) 147 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) (x+0x00000010) 148 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x0003ffe0 149 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_SHFT 5 150 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ 151 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK) 152 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, mask) \ 153 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask) 154 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, val) \ 155 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), val) 156 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x, mask, val) \ 157 do {\ 158 HWIO_INTLOCK(); \ 159 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)); \ 160 HWIO_INTFREE();\ 161 } while (0) 162 163 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 164 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 165 166 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x00000020 167 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 0x5 168 169 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 170 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 173 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x001fffff 174 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 175 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 176 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 177 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 178 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 180 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 181 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 182 do {\ 183 HWIO_INTLOCK(); \ 184 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 185 HWIO_INTFREE();\ 186 } while (0) 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x00100000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 0x14 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x00001000 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 0xc 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x00000080 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 0x7 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 226 227 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 229 230 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 232 233 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 234 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 235 236 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 237 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 238 239 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 240 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 241 242 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 243 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 244 245 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 246 247 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 248 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 249 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x0000ffff 250 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 251 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 252 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 253 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 254 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 255 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 256 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 257 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 258 do {\ 259 HWIO_INTLOCK(); \ 260 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 261 HWIO_INTFREE();\ 262 } while (0) 263 264 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0x0000c000 265 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 0xe 266 267 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 268 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd 269 270 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 271 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc 272 273 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 274 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 275 276 //// Register TCL_R0_TCL2FW_RING_CTRL //// 277 278 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 279 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 280 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 281 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 282 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 283 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 284 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 285 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 286 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 287 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 288 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 289 do {\ 290 HWIO_INTLOCK(); \ 291 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 292 HWIO_INTFREE();\ 293 } while (0) 294 295 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 296 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 297 298 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 299 300 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 301 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 302 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 303 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 304 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 305 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 306 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 307 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 308 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 309 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 310 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 311 do {\ 312 HWIO_INTLOCK(); \ 313 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 314 HWIO_INTFREE();\ 315 } while (0) 316 317 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 318 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 319 320 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 321 322 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 323 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 324 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 325 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 326 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 327 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 328 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 329 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 330 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 331 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 332 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 333 do {\ 334 HWIO_INTLOCK(); \ 335 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 336 HWIO_INTFREE();\ 337 } while (0) 338 339 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 340 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 341 342 //// Register TCL_R0_GEN_CTRL //// 343 344 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 345 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 346 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb 347 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 348 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 349 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 350 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 351 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 352 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 353 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 354 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 355 do {\ 356 HWIO_INTLOCK(); \ 357 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 358 HWIO_INTFREE();\ 359 } while (0) 360 361 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 362 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 363 364 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 365 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 366 367 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 368 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 369 370 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 371 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 372 373 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 374 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 375 376 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 377 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 378 379 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 380 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 381 382 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 383 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 384 385 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 386 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 387 388 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 389 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 390 391 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 392 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 393 394 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 395 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 396 397 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 398 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 399 400 //// Register TCL_R0_DSCP_TID_MAP_n //// 401 402 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) 403 #define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) 404 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 405 #define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 406 #define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 407 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ 408 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) 409 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ 410 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) 411 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ 412 out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) 413 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ 414 do {\ 415 HWIO_INTLOCK(); \ 416 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ 417 HWIO_INTFREE();\ 418 } while (0) 419 420 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff 421 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 422 423 //// Register TCL_R0_PCP_TID_MAP //// 424 425 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) 426 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) 427 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 428 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 429 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 430 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 431 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 432 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 433 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 434 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 435 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 436 do {\ 437 HWIO_INTLOCK(); \ 438 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 439 HWIO_INTFREE();\ 440 } while (0) 441 442 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 443 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 444 445 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 446 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 447 448 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 449 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 450 451 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 452 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 453 454 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 455 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 456 457 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 458 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 459 460 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 461 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 462 463 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 464 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 465 466 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 467 468 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) 469 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) 470 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 471 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 472 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 473 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 474 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 475 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 476 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 477 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 478 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 479 do {\ 480 HWIO_INTLOCK(); \ 481 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 482 HWIO_INTFREE();\ 483 } while (0) 484 485 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 486 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 487 488 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 489 490 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) 491 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) 492 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 493 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 494 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 495 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 496 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 497 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 498 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 499 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 500 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 501 do {\ 502 HWIO_INTLOCK(); \ 503 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 504 HWIO_INTFREE();\ 505 } while (0) 506 507 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 508 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 509 510 //// Register TCL_R0_ASE_HASH_KEY_64 //// 511 512 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) 513 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) 514 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 515 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 516 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 517 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 518 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 519 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 520 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 521 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 522 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 523 do {\ 524 HWIO_INTLOCK(); \ 525 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 526 HWIO_INTFREE();\ 527 } while (0) 528 529 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 530 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 531 532 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 533 534 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004bc) 535 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004bc) 536 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc 537 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 538 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 539 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 540 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 541 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 542 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 543 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 544 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 545 do {\ 546 HWIO_INTLOCK(); \ 547 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 548 HWIO_INTFREE();\ 549 } while (0) 550 551 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000 552 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17 553 554 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 555 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 556 557 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 558 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 559 560 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 561 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe 562 563 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 564 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 565 566 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 567 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 568 569 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 570 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 571 572 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 573 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 574 575 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 576 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 577 578 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 579 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 580 581 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 582 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 583 584 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 585 586 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c0) 587 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c0) 588 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 589 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 590 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 591 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 592 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 593 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 594 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 595 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 596 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 597 do {\ 598 HWIO_INTLOCK(); \ 599 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 600 HWIO_INTFREE();\ 601 } while (0) 602 603 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 604 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 605 606 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 607 608 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004c4) 609 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004c4) 610 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 611 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 612 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 613 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 614 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 615 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 616 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 617 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 618 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 619 do {\ 620 HWIO_INTLOCK(); \ 621 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 622 HWIO_INTFREE();\ 623 } while (0) 624 625 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 626 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 627 628 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 629 630 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c8) 631 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c8) 632 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 633 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 634 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 635 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 636 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 637 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 638 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 639 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 640 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 641 do {\ 642 HWIO_INTLOCK(); \ 643 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 644 HWIO_INTFREE();\ 645 } while (0) 646 647 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 648 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 649 650 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 651 652 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004cc) 653 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004cc) 654 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 655 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 656 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 657 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 658 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 659 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 660 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 661 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 662 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 663 do {\ 664 HWIO_INTLOCK(); \ 665 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 666 HWIO_INTFREE();\ 667 } while (0) 668 669 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 670 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 671 672 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 673 674 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004d0) 675 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004d0) 676 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 677 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 678 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 679 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 680 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 681 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 682 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 683 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 684 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 685 do {\ 686 HWIO_INTLOCK(); \ 687 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 688 HWIO_INTFREE();\ 689 } while (0) 690 691 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 692 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 693 694 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 695 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 696 697 //// Register TCL_R0_TID_MAP_PRTY //// 698 699 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004d4) 700 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004d4) 701 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 702 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 703 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 704 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 705 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 706 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 707 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 708 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 709 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 710 do {\ 711 HWIO_INTLOCK(); \ 712 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 713 HWIO_INTFREE();\ 714 } while (0) 715 716 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 717 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 718 719 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 720 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 721 722 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 723 724 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000004d8) 725 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000004d8) 726 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 727 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 728 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 729 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 730 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 731 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 732 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 733 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 734 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 735 do {\ 736 HWIO_INTLOCK(); \ 737 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 738 HWIO_INTFREE();\ 739 } while (0) 740 741 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 742 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 743 744 //// Register TCL_R0_WATCHDOG //// 745 746 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000004dc) 747 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000004dc) 748 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 749 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 750 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 751 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 752 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 753 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 754 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 755 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 756 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 757 do {\ 758 HWIO_INTLOCK(); \ 759 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 760 HWIO_INTFREE();\ 761 } while (0) 762 763 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 764 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 765 766 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 767 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 768 769 //// Register TCL_R0_LCE_RULE_n //// 770 771 #define HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n) (base+0x4E0+0x4*n) 772 #define HWIO_TCL_R0_LCE_RULE_n_PHYS(base, n) (base+0x4E0+0x4*n) 773 #define HWIO_TCL_R0_LCE_RULE_n_RMSK 0x007fffff 774 #define HWIO_TCL_R0_LCE_RULE_n_SHFT 0 775 #define HWIO_TCL_R0_LCE_RULE_n_MAXn 25 776 #define HWIO_TCL_R0_LCE_RULE_n_INI(base, n) \ 777 in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), HWIO_TCL_R0_LCE_RULE_n_RMSK) 778 #define HWIO_TCL_R0_LCE_RULE_n_INMI(base, n, mask) \ 779 in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask) 780 #define HWIO_TCL_R0_LCE_RULE_n_OUTI(base, n, val) \ 781 out_dword( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), val) 782 #define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base, n, mask, val) \ 783 do {\ 784 HWIO_INTLOCK(); \ 785 out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_RULE_n_INI(base, n)); \ 786 HWIO_INTFREE();\ 787 } while (0) 788 789 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x00400000 790 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 0x16 791 792 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x00200000 793 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 0x15 794 795 #define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x00180000 796 #define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 0x13 797 798 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x00040000 799 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 0x12 800 801 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x00020000 802 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 0x11 803 804 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x00010000 805 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 0x10 806 807 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0x0000ffff 808 #define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0x0 809 810 //// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n //// 811 812 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n) (base+0x548+0x4*n) 813 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base, n) (base+0x548+0x4*n) 814 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff 815 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_SHFT 0 816 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 25 817 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n) \ 818 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK) 819 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base, n, mask) \ 820 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask) 821 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base, n, val) \ 822 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), val) 823 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base, n, mask, val) \ 824 do {\ 825 HWIO_INTLOCK(); \ 826 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n)); \ 827 HWIO_INTFREE();\ 828 } while (0) 829 830 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff 831 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0x0 832 833 //// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n //// 834 835 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n) (base+0x5B0+0x4*n) 836 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base, n) (base+0x5B0+0x4*n) 837 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0x000000ff 838 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_SHFT 0 839 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 25 840 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n) \ 841 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK) 842 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base, n, mask) \ 843 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask) 844 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base, n, val) \ 845 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), val) 846 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base, n, mask, val) \ 847 do {\ 848 HWIO_INTLOCK(); \ 849 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n)); \ 850 HWIO_INTFREE();\ 851 } while (0) 852 853 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0x000000ff 854 #define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0x0 855 856 //// Register TCL_R0_LCE_CLFY_INFO_HANDLER_n //// 857 858 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n) (base+0x618+0x4*n) 859 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base, n) (base+0x618+0x4*n) 860 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x003fffff 861 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_SHFT 0 862 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 25 863 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n) \ 864 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK) 865 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base, n, mask) \ 866 in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask) 867 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base, n, val) \ 868 out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), val) 869 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base, n, mask, val) \ 870 do {\ 871 HWIO_INTLOCK(); \ 872 out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n)); \ 873 HWIO_INTFREE();\ 874 } while (0) 875 876 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x00200000 877 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 0x15 878 879 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x001fffe0 880 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 0x5 881 882 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x00000010 883 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 0x4 884 885 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x00000008 886 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 0x3 887 888 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x00000004 889 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 0x2 890 891 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x00000003 892 #define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0x0 893 894 //// Register TCL_R0_CLKGATE_DISABLE //// 895 896 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000680) 897 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000680) 898 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 899 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 900 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 901 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 902 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 903 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 904 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 905 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 906 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 907 do {\ 908 HWIO_INTLOCK(); \ 909 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 910 HWIO_INTFREE();\ 911 } while (0) 912 913 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 914 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 915 916 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 917 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 918 919 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 920 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 921 922 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 923 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 924 925 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 926 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 927 928 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 929 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 930 931 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 932 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 933 934 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 935 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 936 937 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 938 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 939 940 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 941 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 942 943 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 944 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 945 946 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 947 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 948 949 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 950 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 951 952 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 953 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 954 955 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 956 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 957 958 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 959 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 960 961 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 962 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 963 964 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 965 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 966 967 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 968 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 969 970 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 971 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 972 973 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 974 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 975 976 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 977 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 978 979 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 980 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 981 982 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 983 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 984 985 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 986 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 987 988 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 989 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 990 991 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 992 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 993 994 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 995 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 996 997 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 998 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 999 1000 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 1001 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 1002 1003 #define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_BMSK 0x00000002 1004 #define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_SHFT 0x1 1005 1006 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 1007 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 1008 1009 //// Register TCL_R0_CREDIT_COUNT //// 1010 1011 #define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) (x+0x00000684) 1012 #define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) (x+0x00000684) 1013 #define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x0001ffff 1014 #define HWIO_TCL_R0_CREDIT_COUNT_SHFT 0 1015 #define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \ 1016 in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CREDIT_COUNT_RMSK) 1017 #define HWIO_TCL_R0_CREDIT_COUNT_INM(x, mask) \ 1018 in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask) 1019 #define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, val) \ 1020 out_dword( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), val) 1021 #define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x, mask, val) \ 1022 do {\ 1023 HWIO_INTLOCK(); \ 1024 out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CREDIT_COUNT_IN(x)); \ 1025 HWIO_INTFREE();\ 1026 } while (0) 1027 1028 #define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x00010000 1029 #define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 0x10 1030 1031 #define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0x0000ffff 1032 #define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0x0 1033 1034 //// Register TCL_R0_CURRENT_CREDIT_COUNT //// 1035 1036 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) (x+0x00000688) 1037 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) (x+0x00000688) 1038 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0x0000ffff 1039 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_SHFT 0 1040 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \ 1041 in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK) 1042 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, mask) \ 1043 in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask) 1044 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUT(x, val) \ 1045 out_dword( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), val) 1046 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUTM(x, mask, val) \ 1047 do {\ 1048 HWIO_INTLOCK(); \ 1049 out_dword_masked_ns(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x)); \ 1050 HWIO_INTFREE();\ 1051 } while (0) 1052 1053 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0x0000ffff 1054 #define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0x0 1055 1056 //// Register TCL_R0_S_PARE_REGISTER //// 1057 1058 #define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) (x+0x0000068c) 1059 #define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) (x+0x0000068c) 1060 #define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff 1061 #define HWIO_TCL_R0_S_PARE_REGISTER_SHFT 0 1062 #define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ 1063 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), HWIO_TCL_R0_S_PARE_REGISTER_RMSK) 1064 #define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, mask) \ 1065 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask) 1066 #define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, val) \ 1067 out_dword( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), val) 1068 #define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x, mask, val) \ 1069 do {\ 1070 HWIO_INTLOCK(); \ 1071 out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R0_S_PARE_REGISTER_IN(x)); \ 1072 HWIO_INTFREE();\ 1073 } while (0) 1074 1075 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff 1076 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0 1077 1078 //// Register TCL_R0_MISC_CTRL //// 1079 1080 #define HWIO_TCL_R0_MISC_CTRL_ADDR(x) (x+0x00000690) 1081 #define HWIO_TCL_R0_MISC_CTRL_PHYS(x) (x+0x00000690) 1082 #define HWIO_TCL_R0_MISC_CTRL_RMSK 0x00000003 1083 #define HWIO_TCL_R0_MISC_CTRL_SHFT 0 1084 #define HWIO_TCL_R0_MISC_CTRL_IN(x) \ 1085 in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), HWIO_TCL_R0_MISC_CTRL_RMSK) 1086 #define HWIO_TCL_R0_MISC_CTRL_INM(x, mask) \ 1087 in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask) 1088 #define HWIO_TCL_R0_MISC_CTRL_OUT(x, val) \ 1089 out_dword( HWIO_TCL_R0_MISC_CTRL_ADDR(x), val) 1090 #define HWIO_TCL_R0_MISC_CTRL_OUTM(x, mask, val) \ 1091 do {\ 1092 HWIO_INTLOCK(); \ 1093 out_dword_masked_ns(HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_MISC_CTRL_IN(x)); \ 1094 HWIO_INTFREE();\ 1095 } while (0) 1096 1097 #define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_BMSK 0x00000002 1098 #define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_SHFT 0x1 1099 1100 #define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_BMSK 0x00000001 1101 #define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_SHFT 0x0 1102 1103 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 1104 1105 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000694) 1106 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000694) 1107 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 1108 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1109 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1110 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1111 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1112 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1113 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1114 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1115 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1116 do {\ 1117 HWIO_INTLOCK(); \ 1118 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1119 HWIO_INTFREE();\ 1120 } while (0) 1121 1122 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1123 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1124 1125 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1126 1127 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000698) 1128 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000698) 1129 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff 1130 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1131 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1132 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1133 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1134 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1135 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1136 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1137 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1138 do {\ 1139 HWIO_INTLOCK(); \ 1140 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1141 HWIO_INTFREE();\ 1142 } while (0) 1143 1144 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1145 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1146 1147 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1148 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1149 1150 //// Register TCL_R0_SW2TCL1_RING_ID //// 1151 1152 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x0000069c) 1153 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x0000069c) 1154 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1155 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1156 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1157 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1158 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1159 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1160 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1161 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1162 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1163 do {\ 1164 HWIO_INTLOCK(); \ 1165 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1166 HWIO_INTFREE();\ 1167 } while (0) 1168 1169 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1170 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1171 1172 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1173 1174 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000006a0) 1175 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000006a0) 1176 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1177 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1178 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1179 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1180 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1181 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1182 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1183 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1184 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1185 do {\ 1186 HWIO_INTLOCK(); \ 1187 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1188 HWIO_INTFREE();\ 1189 } while (0) 1190 1191 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1192 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1193 1194 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1195 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1196 1197 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1198 1199 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000006a4) 1200 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000006a4) 1201 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1202 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1203 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1204 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1205 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1206 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1207 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1208 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1209 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1210 do {\ 1211 HWIO_INTLOCK(); \ 1212 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1213 HWIO_INTFREE();\ 1214 } while (0) 1215 1216 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1217 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1218 1219 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1220 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1221 1222 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1223 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1224 1225 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1226 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1227 1228 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1229 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1230 1231 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1232 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1233 1234 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1235 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1236 1237 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1238 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1239 1240 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1241 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1242 1243 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1244 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1245 1246 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1247 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1248 1249 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1250 1251 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006b0) 1252 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006b0) 1253 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1254 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1255 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1256 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1257 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1258 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1259 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1260 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1261 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1262 do {\ 1263 HWIO_INTLOCK(); \ 1264 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1265 HWIO_INTFREE();\ 1266 } while (0) 1267 1268 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1269 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1270 1271 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1272 1273 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006b4) 1274 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006b4) 1275 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1276 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1277 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1278 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1279 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1280 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1281 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1282 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1283 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1284 do {\ 1285 HWIO_INTLOCK(); \ 1286 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1287 HWIO_INTFREE();\ 1288 } while (0) 1289 1290 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1291 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1292 1293 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1294 1295 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006c4) 1296 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006c4) 1297 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1298 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1299 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1300 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1301 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1302 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1303 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1304 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1305 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1306 do {\ 1307 HWIO_INTLOCK(); \ 1308 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1309 HWIO_INTFREE();\ 1310 } while (0) 1311 1312 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1313 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1314 1315 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1316 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1317 1318 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1319 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1320 1321 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1322 1323 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006c8) 1324 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006c8) 1325 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1326 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1327 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1328 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1329 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1330 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1331 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1332 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1333 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1334 do {\ 1335 HWIO_INTLOCK(); \ 1336 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1337 HWIO_INTFREE();\ 1338 } while (0) 1339 1340 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1341 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1342 1343 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1344 1345 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006cc) 1346 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006cc) 1347 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1348 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1349 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1350 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1351 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1352 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1353 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1354 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1355 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1356 do {\ 1357 HWIO_INTLOCK(); \ 1358 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1359 HWIO_INTFREE();\ 1360 } while (0) 1361 1362 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1363 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1364 1365 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1366 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1367 1368 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1369 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1370 1371 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1372 1373 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006d0) 1374 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006d0) 1375 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1376 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1377 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1378 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1379 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1380 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1381 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1382 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1383 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1384 do {\ 1385 HWIO_INTLOCK(); \ 1386 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1387 HWIO_INTFREE();\ 1388 } while (0) 1389 1390 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1391 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1392 1393 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1394 1395 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006d4) 1396 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006d4) 1397 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1398 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1399 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1400 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1401 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1402 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1403 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1404 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1405 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1406 do {\ 1407 HWIO_INTLOCK(); \ 1408 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1409 HWIO_INTFREE();\ 1410 } while (0) 1411 1412 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1413 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1414 1415 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1416 1417 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006d8) 1418 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006d8) 1419 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1420 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1421 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1422 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1423 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1424 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1425 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1426 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1427 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1428 do {\ 1429 HWIO_INTLOCK(); \ 1430 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1431 HWIO_INTFREE();\ 1432 } while (0) 1433 1434 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1435 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1436 1437 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1438 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1439 1440 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1441 1442 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006dc) 1443 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006dc) 1444 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1445 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1446 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1447 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1448 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1449 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1450 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1451 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1452 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1453 do {\ 1454 HWIO_INTLOCK(); \ 1455 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1456 HWIO_INTFREE();\ 1457 } while (0) 1458 1459 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1460 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1461 1462 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1463 1464 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006e0) 1465 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006e0) 1466 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1467 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1468 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1469 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1470 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1471 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1472 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1473 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1474 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1475 do {\ 1476 HWIO_INTLOCK(); \ 1477 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1478 HWIO_INTFREE();\ 1479 } while (0) 1480 1481 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1482 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1483 1484 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1485 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1486 1487 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1488 1489 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006e4) 1490 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006e4) 1491 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1492 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1493 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1494 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1495 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1496 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1497 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1498 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1499 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1500 do {\ 1501 HWIO_INTLOCK(); \ 1502 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1503 HWIO_INTFREE();\ 1504 } while (0) 1505 1506 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1507 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1508 1509 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1510 1511 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006e8) 1512 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006e8) 1513 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1514 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1515 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1516 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1517 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1518 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1519 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1520 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1521 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1522 do {\ 1523 HWIO_INTLOCK(); \ 1524 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1525 HWIO_INTFREE();\ 1526 } while (0) 1527 1528 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1529 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1530 1531 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 1532 1533 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006ec) 1534 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006ec) 1535 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 1536 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 1537 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 1538 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 1539 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 1540 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 1541 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 1542 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 1543 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 1544 do {\ 1545 HWIO_INTLOCK(); \ 1546 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 1547 HWIO_INTFREE();\ 1548 } while (0) 1549 1550 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1551 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1552 1553 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 1554 1555 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006f0) 1556 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006f0) 1557 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff 1558 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 1559 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 1560 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 1561 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 1562 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 1563 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 1564 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 1565 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 1566 do {\ 1567 HWIO_INTLOCK(); \ 1568 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 1569 HWIO_INTFREE();\ 1570 } while (0) 1571 1572 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1573 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1574 1575 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1576 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1577 1578 //// Register TCL_R0_SW2TCL2_RING_ID //// 1579 1580 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006f4) 1581 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006f4) 1582 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 1583 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 1584 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 1585 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 1586 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 1587 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 1588 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 1589 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 1590 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 1591 do {\ 1592 HWIO_INTLOCK(); \ 1593 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 1594 HWIO_INTFREE();\ 1595 } while (0) 1596 1597 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1598 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 1599 1600 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 1601 1602 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006f8) 1603 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006f8) 1604 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 1605 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 1606 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 1607 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 1608 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 1609 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 1610 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 1611 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 1612 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 1613 do {\ 1614 HWIO_INTLOCK(); \ 1615 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 1616 HWIO_INTFREE();\ 1617 } while (0) 1618 1619 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1620 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1621 1622 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1623 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1624 1625 //// Register TCL_R0_SW2TCL2_RING_MISC //// 1626 1627 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006fc) 1628 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006fc) 1629 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 1630 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 1631 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 1632 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 1633 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 1634 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 1635 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 1636 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 1637 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 1638 do {\ 1639 HWIO_INTLOCK(); \ 1640 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 1641 HWIO_INTFREE();\ 1642 } while (0) 1643 1644 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1645 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1646 1647 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1648 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1649 1650 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1651 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1652 1653 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1654 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1655 1656 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1657 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1658 1659 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1660 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1661 1662 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1663 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1664 1665 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1666 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1667 1668 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1669 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 1670 1671 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1672 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1673 1674 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1675 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1676 1677 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 1678 1679 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000708) 1680 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000708) 1681 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1682 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 1683 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 1684 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 1685 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 1686 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 1687 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 1688 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 1689 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1690 do {\ 1691 HWIO_INTLOCK(); \ 1692 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 1693 HWIO_INTFREE();\ 1694 } while (0) 1695 1696 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1697 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1698 1699 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 1700 1701 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000070c) 1702 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000070c) 1703 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1704 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 1705 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 1706 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 1707 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 1708 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 1709 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 1710 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 1711 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1712 do {\ 1713 HWIO_INTLOCK(); \ 1714 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 1715 HWIO_INTFREE();\ 1716 } while (0) 1717 1718 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1719 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1720 1721 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 1722 1723 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000071c) 1724 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000071c) 1725 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1726 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1727 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1728 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1729 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1730 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1731 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1732 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1733 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1734 do {\ 1735 HWIO_INTLOCK(); \ 1736 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1737 HWIO_INTFREE();\ 1738 } while (0) 1739 1740 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1741 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1742 1743 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1744 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1745 1746 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1747 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1748 1749 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 1750 1751 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000720) 1752 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000720) 1753 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1754 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1755 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1756 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1757 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1758 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1759 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1760 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1761 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1762 do {\ 1763 HWIO_INTLOCK(); \ 1764 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1765 HWIO_INTFREE();\ 1766 } while (0) 1767 1768 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1769 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1770 1771 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 1772 1773 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000724) 1774 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000724) 1775 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1776 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 1777 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 1778 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 1779 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1780 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1781 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1782 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1783 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1784 do {\ 1785 HWIO_INTLOCK(); \ 1786 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1787 HWIO_INTFREE();\ 1788 } while (0) 1789 1790 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1791 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1792 1793 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1794 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1795 1796 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1797 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1798 1799 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 1800 1801 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000728) 1802 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000728) 1803 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1804 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1805 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1806 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1807 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1808 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1809 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1810 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1811 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1812 do {\ 1813 HWIO_INTLOCK(); \ 1814 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1815 HWIO_INTFREE();\ 1816 } while (0) 1817 1818 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1819 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1820 1821 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 1822 1823 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000072c) 1824 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000072c) 1825 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1826 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1827 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1828 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1829 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1830 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1831 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1832 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1833 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1834 do {\ 1835 HWIO_INTLOCK(); \ 1836 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1837 HWIO_INTFREE();\ 1838 } while (0) 1839 1840 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1841 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1842 1843 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 1844 1845 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000730) 1846 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000730) 1847 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1848 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1849 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1850 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1851 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1852 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1853 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1854 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1855 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1856 do {\ 1857 HWIO_INTLOCK(); \ 1858 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1859 HWIO_INTFREE();\ 1860 } while (0) 1861 1862 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1863 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1864 1865 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1866 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1867 1868 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 1869 1870 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000734) 1871 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000734) 1872 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1873 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 1874 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 1875 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 1876 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1877 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1878 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1879 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 1880 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1881 do {\ 1882 HWIO_INTLOCK(); \ 1883 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 1884 HWIO_INTFREE();\ 1885 } while (0) 1886 1887 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1888 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1889 1890 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 1891 1892 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000738) 1893 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000738) 1894 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1895 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 1896 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 1897 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 1898 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1899 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1900 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1901 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 1902 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1903 do {\ 1904 HWIO_INTLOCK(); \ 1905 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 1906 HWIO_INTFREE();\ 1907 } while (0) 1908 1909 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1910 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1911 1912 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1913 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1914 1915 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 1916 1917 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000073c) 1918 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000073c) 1919 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 1920 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 1921 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 1922 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 1923 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 1924 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 1925 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 1926 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 1927 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1928 do {\ 1929 HWIO_INTLOCK(); \ 1930 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 1931 HWIO_INTFREE();\ 1932 } while (0) 1933 1934 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1935 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 1936 1937 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 1938 1939 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000740) 1940 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000740) 1941 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1942 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 1943 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 1944 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 1945 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1946 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1947 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1948 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1949 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1950 do {\ 1951 HWIO_INTLOCK(); \ 1952 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1953 HWIO_INTFREE();\ 1954 } while (0) 1955 1956 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1957 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1958 1959 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 1960 1961 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000744) 1962 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000744) 1963 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 1964 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 1965 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 1966 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 1967 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 1968 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 1969 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 1970 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 1971 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 1972 do {\ 1973 HWIO_INTLOCK(); \ 1974 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 1975 HWIO_INTFREE();\ 1976 } while (0) 1977 1978 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1979 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1980 1981 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 1982 1983 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000748) 1984 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000748) 1985 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff 1986 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 1987 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 1988 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 1989 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 1990 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 1991 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 1992 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 1993 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 1994 do {\ 1995 HWIO_INTLOCK(); \ 1996 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 1997 HWIO_INTFREE();\ 1998 } while (0) 1999 2000 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2001 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2002 2003 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2004 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2005 2006 //// Register TCL_R0_SW2TCL3_RING_ID //// 2007 2008 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000074c) 2009 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000074c) 2010 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 2011 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 2012 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 2013 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 2014 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 2015 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 2016 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 2017 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 2018 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 2019 do {\ 2020 HWIO_INTLOCK(); \ 2021 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 2022 HWIO_INTFREE();\ 2023 } while (0) 2024 2025 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2026 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 2027 2028 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 2029 2030 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000750) 2031 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000750) 2032 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 2033 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 2034 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 2035 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 2036 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 2037 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 2038 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 2039 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 2040 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 2041 do {\ 2042 HWIO_INTLOCK(); \ 2043 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 2044 HWIO_INTFREE();\ 2045 } while (0) 2046 2047 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2048 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2049 2050 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2051 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2052 2053 //// Register TCL_R0_SW2TCL3_RING_MISC //// 2054 2055 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000754) 2056 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000754) 2057 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 2058 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 2059 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 2060 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 2061 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 2062 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 2063 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 2064 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 2065 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 2066 do {\ 2067 HWIO_INTLOCK(); \ 2068 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 2069 HWIO_INTFREE();\ 2070 } while (0) 2071 2072 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2073 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 2074 2075 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2076 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2077 2078 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2079 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2080 2081 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2082 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2083 2084 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2085 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 2086 2087 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2088 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2089 2090 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2091 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2092 2093 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2094 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2095 2096 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2097 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 2098 2099 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2100 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2101 2102 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2103 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2104 2105 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 2106 2107 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000760) 2108 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000760) 2109 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2110 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2111 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2112 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2113 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2114 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2115 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2116 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2117 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2118 do {\ 2119 HWIO_INTLOCK(); \ 2120 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2121 HWIO_INTFREE();\ 2122 } while (0) 2123 2124 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2125 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2126 2127 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2128 2129 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000764) 2130 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000764) 2131 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2132 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2133 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2134 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2135 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2136 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2137 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2138 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2139 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2140 do {\ 2141 HWIO_INTLOCK(); \ 2142 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2143 HWIO_INTFREE();\ 2144 } while (0) 2145 2146 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2147 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2148 2149 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2150 2151 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000774) 2152 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000774) 2153 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2154 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2155 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2156 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2157 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2158 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2159 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2160 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2161 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2162 do {\ 2163 HWIO_INTLOCK(); \ 2164 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2165 HWIO_INTFREE();\ 2166 } while (0) 2167 2168 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2169 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2170 2171 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2172 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2173 2174 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2175 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2176 2177 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2178 2179 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000778) 2180 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000778) 2181 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2182 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2183 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2184 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2185 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2186 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2187 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2188 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2189 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2190 do {\ 2191 HWIO_INTLOCK(); \ 2192 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2193 HWIO_INTFREE();\ 2194 } while (0) 2195 2196 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2197 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2198 2199 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2200 2201 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000077c) 2202 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000077c) 2203 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2204 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2205 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2206 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2207 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2208 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2209 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2210 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2211 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2212 do {\ 2213 HWIO_INTLOCK(); \ 2214 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2215 HWIO_INTFREE();\ 2216 } while (0) 2217 2218 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2219 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2220 2221 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2222 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2223 2224 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2225 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2226 2227 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2228 2229 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000780) 2230 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000780) 2231 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2232 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2233 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2234 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2235 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2236 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2237 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2238 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2239 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2240 do {\ 2241 HWIO_INTLOCK(); \ 2242 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2243 HWIO_INTFREE();\ 2244 } while (0) 2245 2246 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2247 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2248 2249 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2250 2251 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000784) 2252 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000784) 2253 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2254 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2255 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2256 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2257 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2258 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2259 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2260 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2261 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2262 do {\ 2263 HWIO_INTLOCK(); \ 2264 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2265 HWIO_INTFREE();\ 2266 } while (0) 2267 2268 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2269 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2270 2271 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2272 2273 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000788) 2274 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000788) 2275 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2276 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2277 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2278 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2279 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2280 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2281 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2282 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2283 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2284 do {\ 2285 HWIO_INTLOCK(); \ 2286 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2287 HWIO_INTFREE();\ 2288 } while (0) 2289 2290 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2291 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2292 2293 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2294 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2295 2296 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2297 2298 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000078c) 2299 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000078c) 2300 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2301 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2302 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2303 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2304 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2305 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2306 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2307 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2308 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2309 do {\ 2310 HWIO_INTLOCK(); \ 2311 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2312 HWIO_INTFREE();\ 2313 } while (0) 2314 2315 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2316 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2317 2318 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2319 2320 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000790) 2321 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000790) 2322 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2323 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2324 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2325 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2326 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2327 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2328 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2329 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2330 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2331 do {\ 2332 HWIO_INTLOCK(); \ 2333 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2334 HWIO_INTFREE();\ 2335 } while (0) 2336 2337 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2338 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2339 2340 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2341 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2342 2343 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2344 2345 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000794) 2346 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000794) 2347 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2348 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2349 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2350 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2351 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2352 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2353 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2354 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2355 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2356 do {\ 2357 HWIO_INTLOCK(); \ 2358 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2359 HWIO_INTFREE();\ 2360 } while (0) 2361 2362 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2363 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2364 2365 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2366 2367 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000798) 2368 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000798) 2369 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2370 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2371 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2372 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2373 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2374 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2375 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2376 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2377 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2378 do {\ 2379 HWIO_INTLOCK(); \ 2380 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2381 HWIO_INTFREE();\ 2382 } while (0) 2383 2384 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2385 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2386 2387 //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB //// 2388 2389 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x0000079c) 2390 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x0000079c) 2391 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff 2392 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_SHFT 0 2393 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ 2394 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK) 2395 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, mask) \ 2396 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask) 2397 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, val) \ 2398 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), val) 2399 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x, mask, val) \ 2400 do {\ 2401 HWIO_INTLOCK(); \ 2402 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)); \ 2403 HWIO_INTFREE();\ 2404 } while (0) 2405 2406 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2407 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2408 2409 //// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB //// 2410 2411 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x000007a0) 2412 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x000007a0) 2413 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0x0fffffff 2414 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_SHFT 0 2415 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ 2416 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK) 2417 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, mask) \ 2418 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask) 2419 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, val) \ 2420 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), val) 2421 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x, mask, val) \ 2422 do {\ 2423 HWIO_INTLOCK(); \ 2424 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)); \ 2425 HWIO_INTFREE();\ 2426 } while (0) 2427 2428 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2429 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2430 2431 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2432 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2433 2434 //// Register TCL_R0_SW2TCL_CREDIT_RING_ID //// 2435 2436 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x000007a4) 2437 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x000007a4) 2438 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0x000000ff 2439 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_SHFT 0 2440 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ 2441 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK) 2442 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, mask) \ 2443 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask) 2444 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, val) \ 2445 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), val) 2446 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x, mask, val) \ 2447 do {\ 2448 HWIO_INTLOCK(); \ 2449 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)); \ 2450 HWIO_INTFREE();\ 2451 } while (0) 2452 2453 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2454 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0x0 2455 2456 //// Register TCL_R0_SW2TCL_CREDIT_RING_STATUS //// 2457 2458 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x000007a8) 2459 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x000007a8) 2460 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff 2461 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_SHFT 0 2462 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ 2463 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK) 2464 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, mask) \ 2465 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask) 2466 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUT(x, val) \ 2467 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), val) 2468 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUTM(x, mask, val) \ 2469 do {\ 2470 HWIO_INTLOCK(); \ 2471 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x)); \ 2472 HWIO_INTFREE();\ 2473 } while (0) 2474 2475 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2476 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2477 2478 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2479 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2480 2481 //// Register TCL_R0_SW2TCL_CREDIT_RING_MISC //// 2482 2483 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x000007ac) 2484 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x000007ac) 2485 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x003fffff 2486 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SHFT 0 2487 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ 2488 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK) 2489 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, mask) \ 2490 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask) 2491 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, val) \ 2492 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), val) 2493 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x, mask, val) \ 2494 do {\ 2495 HWIO_INTLOCK(); \ 2496 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)); \ 2497 HWIO_INTFREE();\ 2498 } while (0) 2499 2500 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2501 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 0xe 2502 2503 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2504 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2505 2506 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2507 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2508 2509 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2510 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2511 2512 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2513 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 0x6 2514 2515 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2516 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2517 2518 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2519 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2520 2521 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2522 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2523 2524 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2525 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 0x2 2526 2527 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2528 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2529 2530 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2531 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2532 2533 //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB //// 2534 2535 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007b8) 2536 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007b8) 2537 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff 2538 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_SHFT 0 2539 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ 2540 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK) 2541 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, mask) \ 2542 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask) 2543 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, val) \ 2544 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), val) 2545 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2546 do {\ 2547 HWIO_INTLOCK(); \ 2548 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)); \ 2549 HWIO_INTFREE();\ 2550 } while (0) 2551 2552 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2553 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2554 2555 //// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB //// 2556 2557 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007bc) 2558 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007bc) 2559 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0x000000ff 2560 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_SHFT 0 2561 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ 2562 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK) 2563 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, mask) \ 2564 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask) 2565 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, val) \ 2566 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), val) 2567 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2568 do {\ 2569 HWIO_INTLOCK(); \ 2570 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)); \ 2571 HWIO_INTFREE();\ 2572 } while (0) 2573 2574 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2575 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2576 2577 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 //// 2578 2579 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007cc) 2580 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007cc) 2581 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2582 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2583 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2584 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2585 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2586 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2587 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2588 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2589 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2590 do {\ 2591 HWIO_INTLOCK(); \ 2592 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2593 HWIO_INTFREE();\ 2594 } while (0) 2595 2596 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2597 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2598 2599 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2600 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2601 2602 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2603 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2604 2605 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 //// 2606 2607 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007d0) 2608 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007d0) 2609 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2610 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2611 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2612 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2613 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2614 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2615 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2616 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2617 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2618 do {\ 2619 HWIO_INTLOCK(); \ 2620 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2621 HWIO_INTFREE();\ 2622 } while (0) 2623 2624 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2625 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2626 2627 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS //// 2628 2629 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007d4) 2630 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007d4) 2631 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2632 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_SHFT 0 2633 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ 2634 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK) 2635 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2636 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2637 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2638 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2639 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2640 do {\ 2641 HWIO_INTLOCK(); \ 2642 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x)); \ 2643 HWIO_INTFREE();\ 2644 } while (0) 2645 2646 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2647 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2648 2649 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2650 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2651 2652 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2653 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2654 2655 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER //// 2656 2657 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007d8) 2658 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007d8) 2659 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2660 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2661 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2662 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2663 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2664 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2665 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2666 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2667 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2668 do {\ 2669 HWIO_INTLOCK(); \ 2670 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2671 HWIO_INTFREE();\ 2672 } while (0) 2673 2674 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2675 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2676 2677 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER //// 2678 2679 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007dc) 2680 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007dc) 2681 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2682 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2683 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2684 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2685 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2686 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2687 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2688 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2689 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2690 do {\ 2691 HWIO_INTLOCK(); \ 2692 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2693 HWIO_INTFREE();\ 2694 } while (0) 2695 2696 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2697 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2698 2699 //// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS //// 2700 2701 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007e0) 2702 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007e0) 2703 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2704 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2705 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2706 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2707 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2708 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2709 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2710 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2711 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2712 do {\ 2713 HWIO_INTLOCK(); \ 2714 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2715 HWIO_INTFREE();\ 2716 } while (0) 2717 2718 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2719 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2720 2721 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2722 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2723 2724 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB //// 2725 2726 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007e4) 2727 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007e4) 2728 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2729 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_SHFT 0 2730 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ 2731 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK) 2732 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, mask) \ 2733 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask) 2734 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, val) \ 2735 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), val) 2736 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2737 do {\ 2738 HWIO_INTLOCK(); \ 2739 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)); \ 2740 HWIO_INTFREE();\ 2741 } while (0) 2742 2743 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2744 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2745 2746 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB //// 2747 2748 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007e8) 2749 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007e8) 2750 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2751 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_SHFT 0 2752 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ 2753 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK) 2754 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, mask) \ 2755 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask) 2756 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, val) \ 2757 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), val) 2758 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2759 do {\ 2760 HWIO_INTLOCK(); \ 2761 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)); \ 2762 HWIO_INTFREE();\ 2763 } while (0) 2764 2765 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2766 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2767 2768 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2769 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2770 2771 //// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA //// 2772 2773 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x000007ec) 2774 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x000007ec) 2775 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff 2776 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_SHFT 0 2777 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ 2778 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK) 2779 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, mask) \ 2780 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask) 2781 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, val) \ 2782 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), val) 2783 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x, mask, val) \ 2784 do {\ 2785 HWIO_INTLOCK(); \ 2786 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)); \ 2787 HWIO_INTFREE();\ 2788 } while (0) 2789 2790 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2791 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0x0 2792 2793 //// Register TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET //// 2794 2795 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007f0) 2796 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007f0) 2797 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2798 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_SHFT 0 2799 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ 2800 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK) 2801 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2802 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2803 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2804 out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2805 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2806 do {\ 2807 HWIO_INTLOCK(); \ 2808 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)); \ 2809 HWIO_INTFREE();\ 2810 } while (0) 2811 2812 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2813 #define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2814 2815 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 2816 2817 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007f4) 2818 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007f4) 2819 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 2820 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 2821 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 2822 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 2823 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 2824 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 2825 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 2826 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 2827 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 2828 do {\ 2829 HWIO_INTLOCK(); \ 2830 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 2831 HWIO_INTFREE();\ 2832 } while (0) 2833 2834 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2835 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2836 2837 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 2838 2839 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007f8) 2840 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007f8) 2841 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 2842 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 2843 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 2844 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 2845 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 2846 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 2847 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 2848 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 2849 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 2850 do {\ 2851 HWIO_INTLOCK(); \ 2852 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 2853 HWIO_INTFREE();\ 2854 } while (0) 2855 2856 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2857 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2858 2859 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2860 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2861 2862 //// Register TCL_R0_FW2TCL1_RING_ID //// 2863 2864 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007fc) 2865 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007fc) 2866 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 2867 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 2868 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 2869 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 2870 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 2871 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 2872 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 2873 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 2874 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 2875 do {\ 2876 HWIO_INTLOCK(); \ 2877 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 2878 HWIO_INTFREE();\ 2879 } while (0) 2880 2881 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2882 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 2883 2884 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 2885 2886 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000800) 2887 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000800) 2888 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 2889 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 2890 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 2891 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 2892 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 2893 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 2894 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 2895 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 2896 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 2897 do {\ 2898 HWIO_INTLOCK(); \ 2899 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 2900 HWIO_INTFREE();\ 2901 } while (0) 2902 2903 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2904 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2905 2906 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2907 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2908 2909 //// Register TCL_R0_FW2TCL1_RING_MISC //// 2910 2911 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000804) 2912 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000804) 2913 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 2914 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 2915 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 2916 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 2917 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 2918 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 2919 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 2920 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 2921 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 2922 do {\ 2923 HWIO_INTLOCK(); \ 2924 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 2925 HWIO_INTFREE();\ 2926 } while (0) 2927 2928 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2929 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2930 2931 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2932 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2933 2934 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2935 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2936 2937 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2938 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2939 2940 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2941 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2942 2943 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2944 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2945 2946 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2947 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2948 2949 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2950 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2951 2952 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2953 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 2954 2955 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2956 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2957 2958 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2959 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2960 2961 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 2962 2963 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000810) 2964 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000810) 2965 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2966 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 2967 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 2968 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 2969 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 2970 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 2971 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 2972 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 2973 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2974 do {\ 2975 HWIO_INTLOCK(); \ 2976 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 2977 HWIO_INTFREE();\ 2978 } while (0) 2979 2980 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2981 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2982 2983 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 2984 2985 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000814) 2986 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000814) 2987 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2988 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 2989 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 2990 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 2991 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 2992 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 2993 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 2994 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 2995 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2996 do {\ 2997 HWIO_INTLOCK(); \ 2998 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 2999 HWIO_INTFREE();\ 3000 } while (0) 3001 3002 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3003 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3004 3005 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 3006 3007 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000824) 3008 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000824) 3009 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3010 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3011 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3012 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3013 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3014 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3015 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3016 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3017 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3018 do {\ 3019 HWIO_INTLOCK(); \ 3020 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3021 HWIO_INTFREE();\ 3022 } while (0) 3023 3024 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3025 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3026 3027 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3028 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3029 3030 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3031 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3032 3033 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 3034 3035 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000828) 3036 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000828) 3037 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3038 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3039 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3040 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3041 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3042 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3043 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3044 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3045 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3046 do {\ 3047 HWIO_INTLOCK(); \ 3048 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3049 HWIO_INTFREE();\ 3050 } while (0) 3051 3052 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3053 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3054 3055 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 3056 3057 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000082c) 3058 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000082c) 3059 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3060 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 3061 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 3062 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 3063 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3064 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3065 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3066 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3067 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3068 do {\ 3069 HWIO_INTLOCK(); \ 3070 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3071 HWIO_INTFREE();\ 3072 } while (0) 3073 3074 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3075 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3076 3077 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3078 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3079 3080 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3081 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3082 3083 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 3084 3085 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000830) 3086 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000830) 3087 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3088 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3089 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3090 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3091 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3092 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3093 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3094 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3095 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3096 do {\ 3097 HWIO_INTLOCK(); \ 3098 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3099 HWIO_INTFREE();\ 3100 } while (0) 3101 3102 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3103 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3104 3105 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 3106 3107 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000834) 3108 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000834) 3109 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3110 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3111 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3112 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3113 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3114 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3115 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3116 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3117 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3118 do {\ 3119 HWIO_INTLOCK(); \ 3120 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3121 HWIO_INTFREE();\ 3122 } while (0) 3123 3124 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3125 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3126 3127 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3128 3129 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000838) 3130 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000838) 3131 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3132 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3133 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3134 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3135 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3136 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3137 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3138 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3139 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3140 do {\ 3141 HWIO_INTLOCK(); \ 3142 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3143 HWIO_INTFREE();\ 3144 } while (0) 3145 3146 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3147 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3148 3149 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3150 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3151 3152 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3153 3154 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000083c) 3155 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000083c) 3156 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3157 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3158 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3159 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3160 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3161 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3162 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3163 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3164 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3165 do {\ 3166 HWIO_INTLOCK(); \ 3167 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3168 HWIO_INTFREE();\ 3169 } while (0) 3170 3171 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3172 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3173 3174 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3175 3176 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000840) 3177 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000840) 3178 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3179 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3180 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3181 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3182 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3183 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3184 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3185 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3186 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3187 do {\ 3188 HWIO_INTLOCK(); \ 3189 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3190 HWIO_INTFREE();\ 3191 } while (0) 3192 3193 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3194 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3195 3196 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3197 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3198 3199 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3200 3201 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000844) 3202 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000844) 3203 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3204 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3205 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3206 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3207 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3208 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3209 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3210 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3211 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3212 do {\ 3213 HWIO_INTLOCK(); \ 3214 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3215 HWIO_INTFREE();\ 3216 } while (0) 3217 3218 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3219 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3220 3221 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3222 3223 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000848) 3224 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000848) 3225 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3226 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3227 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3228 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3229 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3230 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3231 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3232 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3233 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3234 do {\ 3235 HWIO_INTLOCK(); \ 3236 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3237 HWIO_INTFREE();\ 3238 } while (0) 3239 3240 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3241 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3242 3243 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3244 3245 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000084c) 3246 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000084c) 3247 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3248 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3249 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3250 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3251 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3252 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3253 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3254 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3255 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3256 do {\ 3257 HWIO_INTLOCK(); \ 3258 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3259 HWIO_INTFREE();\ 3260 } while (0) 3261 3262 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3263 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3264 3265 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3266 3267 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000850) 3268 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000850) 3269 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3270 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3271 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3272 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3273 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3274 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3275 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3276 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3277 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3278 do {\ 3279 HWIO_INTLOCK(); \ 3280 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3281 HWIO_INTFREE();\ 3282 } while (0) 3283 3284 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3285 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3286 3287 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3288 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3289 3290 //// Register TCL_R0_TCL2TQM_RING_ID //// 3291 3292 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000854) 3293 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000854) 3294 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3295 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3296 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3297 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3298 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3299 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3300 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3301 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3302 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3303 do {\ 3304 HWIO_INTLOCK(); \ 3305 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3306 HWIO_INTFREE();\ 3307 } while (0) 3308 3309 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3310 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3311 3312 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3313 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3314 3315 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3316 3317 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000858) 3318 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000858) 3319 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3320 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3321 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3322 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3323 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3324 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3325 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3326 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3327 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3328 do {\ 3329 HWIO_INTLOCK(); \ 3330 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3331 HWIO_INTFREE();\ 3332 } while (0) 3333 3334 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3335 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3336 3337 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3338 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3339 3340 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3341 3342 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000085c) 3343 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000085c) 3344 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3345 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3346 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3347 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3348 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3349 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3350 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3351 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3352 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3353 do {\ 3354 HWIO_INTLOCK(); \ 3355 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3356 HWIO_INTFREE();\ 3357 } while (0) 3358 3359 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3360 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3361 3362 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3363 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3364 3365 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3366 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3367 3368 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3369 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3370 3371 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3372 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3373 3374 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3375 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3376 3377 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3378 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3379 3380 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3381 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3382 3383 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3384 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3385 3386 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3387 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3388 3389 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3390 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3391 3392 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3393 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3394 3395 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3396 3397 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000860) 3398 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000860) 3399 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3400 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3401 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3402 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3403 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3404 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3405 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3406 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3407 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3408 do {\ 3409 HWIO_INTLOCK(); \ 3410 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3411 HWIO_INTFREE();\ 3412 } while (0) 3413 3414 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3415 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3416 3417 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3418 3419 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000864) 3420 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000864) 3421 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3422 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3423 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3424 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3425 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3426 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3427 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3428 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3429 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3430 do {\ 3431 HWIO_INTLOCK(); \ 3432 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3433 HWIO_INTFREE();\ 3434 } while (0) 3435 3436 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3437 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3438 3439 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3440 3441 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000870) 3442 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000870) 3443 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3444 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3445 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3446 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3447 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3448 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3449 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3450 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3451 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3452 do {\ 3453 HWIO_INTLOCK(); \ 3454 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3455 HWIO_INTFREE();\ 3456 } while (0) 3457 3458 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3459 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3460 3461 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3462 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3463 3464 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3465 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3466 3467 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3468 3469 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000874) 3470 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000874) 3471 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3472 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3473 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3474 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3475 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3476 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3477 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3478 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3479 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3480 do {\ 3481 HWIO_INTLOCK(); \ 3482 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3483 HWIO_INTFREE();\ 3484 } while (0) 3485 3486 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3487 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3488 3489 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3490 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3491 3492 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3493 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3494 3495 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3496 3497 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000878) 3498 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000878) 3499 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3500 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3501 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3502 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3503 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3504 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3505 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3506 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3507 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3508 do {\ 3509 HWIO_INTLOCK(); \ 3510 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3511 HWIO_INTFREE();\ 3512 } while (0) 3513 3514 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3515 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3516 3517 //// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB //// 3518 3519 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000894) 3520 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000894) 3521 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3522 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_SHFT 0 3523 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ 3524 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK) 3525 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, mask) \ 3526 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask) 3527 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, val) \ 3528 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), val) 3529 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3530 do {\ 3531 HWIO_INTLOCK(); \ 3532 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)); \ 3533 HWIO_INTFREE();\ 3534 } while (0) 3535 3536 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3537 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3538 3539 //// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB //// 3540 3541 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000898) 3542 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000898) 3543 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3544 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_SHFT 0 3545 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ 3546 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK) 3547 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, mask) \ 3548 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask) 3549 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, val) \ 3550 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), val) 3551 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3552 do {\ 3553 HWIO_INTLOCK(); \ 3554 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)); \ 3555 HWIO_INTFREE();\ 3556 } while (0) 3557 3558 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3559 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3560 3561 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3562 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3563 3564 //// Register TCL_R0_TCL2TQM_RING_MSI1_DATA //// 3565 3566 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) (x+0x0000089c) 3567 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) (x+0x0000089c) 3568 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff 3569 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_SHFT 0 3570 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ 3571 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK) 3572 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_INM(x, mask) \ 3573 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask) 3574 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, val) \ 3575 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), val) 3576 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x, mask, val) \ 3577 do {\ 3578 HWIO_INTLOCK(); \ 3579 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x)); \ 3580 HWIO_INTFREE();\ 3581 } while (0) 3582 3583 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3584 #define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0x0 3585 3586 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3587 3588 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008a0) 3589 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008a0) 3590 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3591 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3592 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3593 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3594 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3595 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3596 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3597 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3598 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3599 do {\ 3600 HWIO_INTLOCK(); \ 3601 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3602 HWIO_INTFREE();\ 3603 } while (0) 3604 3605 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3606 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3607 3608 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3609 3610 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000008a4) 3611 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000008a4) 3612 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3613 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3614 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3615 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3616 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3617 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3618 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3619 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3620 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3621 do {\ 3622 HWIO_INTLOCK(); \ 3623 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3624 HWIO_INTFREE();\ 3625 } while (0) 3626 3627 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3628 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3629 3630 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3631 3632 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000008a8) 3633 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000008a8) 3634 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3635 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3636 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3637 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3638 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3639 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3640 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3641 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3642 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3643 do {\ 3644 HWIO_INTLOCK(); \ 3645 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3646 HWIO_INTFREE();\ 3647 } while (0) 3648 3649 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3650 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3651 3652 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3653 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3654 3655 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3656 3657 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000008ac) 3658 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000008ac) 3659 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3660 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3661 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3662 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3663 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3664 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3665 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 3666 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 3667 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 3668 do {\ 3669 HWIO_INTLOCK(); \ 3670 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 3671 HWIO_INTFREE();\ 3672 } while (0) 3673 3674 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 3675 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 3676 3677 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3678 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 3679 3680 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 3681 3682 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008b0) 3683 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008b0) 3684 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 3685 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 3686 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 3687 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 3688 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 3689 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 3690 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 3691 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 3692 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 3693 do {\ 3694 HWIO_INTLOCK(); \ 3695 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 3696 HWIO_INTFREE();\ 3697 } while (0) 3698 3699 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3700 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3701 3702 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3703 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3704 3705 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 3706 3707 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008b4) 3708 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008b4) 3709 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 3710 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 3711 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 3712 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 3713 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 3714 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 3715 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 3716 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 3717 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 3718 do {\ 3719 HWIO_INTLOCK(); \ 3720 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 3721 HWIO_INTFREE();\ 3722 } while (0) 3723 3724 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3725 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 3726 3727 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3728 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3729 3730 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3731 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3732 3733 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3734 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3735 3736 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3737 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3738 3739 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3740 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3741 3742 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3743 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3744 3745 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3746 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3747 3748 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3749 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3750 3751 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3752 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 3753 3754 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3755 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3756 3757 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3758 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3759 3760 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 3761 3762 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008b8) 3763 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008b8) 3764 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3765 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 3766 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 3767 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 3768 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 3769 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 3770 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 3771 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 3772 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3773 do {\ 3774 HWIO_INTLOCK(); \ 3775 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 3776 HWIO_INTFREE();\ 3777 } while (0) 3778 3779 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3780 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3781 3782 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 3783 3784 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008bc) 3785 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008bc) 3786 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3787 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 3788 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 3789 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 3790 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 3791 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 3792 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 3793 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 3794 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3795 do {\ 3796 HWIO_INTLOCK(); \ 3797 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 3798 HWIO_INTFREE();\ 3799 } while (0) 3800 3801 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3802 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3803 3804 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 3805 3806 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008c8) 3807 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008c8) 3808 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3809 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 3810 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 3811 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 3812 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3813 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3814 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3815 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3816 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3817 do {\ 3818 HWIO_INTLOCK(); \ 3819 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3820 HWIO_INTFREE();\ 3821 } while (0) 3822 3823 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3824 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3825 3826 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3827 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3828 3829 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3830 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3831 3832 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 3833 3834 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008cc) 3835 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008cc) 3836 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3837 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 3838 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 3839 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 3840 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3841 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3842 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3843 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3844 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3845 do {\ 3846 HWIO_INTLOCK(); \ 3847 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3848 HWIO_INTFREE();\ 3849 } while (0) 3850 3851 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3852 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3853 3854 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3855 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3856 3857 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3858 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3859 3860 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 3861 3862 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008d0) 3863 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008d0) 3864 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3865 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3866 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3867 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 3868 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3869 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3870 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3871 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3872 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3873 do {\ 3874 HWIO_INTLOCK(); \ 3875 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3876 HWIO_INTFREE();\ 3877 } while (0) 3878 3879 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3880 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3881 3882 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 3883 3884 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008ec) 3885 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008ec) 3886 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3887 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 3888 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 3889 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 3890 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3891 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3892 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3893 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 3894 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3895 do {\ 3896 HWIO_INTLOCK(); \ 3897 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 3898 HWIO_INTFREE();\ 3899 } while (0) 3900 3901 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3902 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3903 3904 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 3905 3906 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008f0) 3907 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008f0) 3908 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3909 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 3910 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 3911 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 3912 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3913 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3914 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3915 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 3916 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3917 do {\ 3918 HWIO_INTLOCK(); \ 3919 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 3920 HWIO_INTFREE();\ 3921 } while (0) 3922 3923 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3924 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3925 3926 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3927 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3928 3929 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 3930 3931 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008f4) 3932 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008f4) 3933 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 3934 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 3935 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 3936 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 3937 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 3938 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 3939 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 3940 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 3941 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3942 do {\ 3943 HWIO_INTLOCK(); \ 3944 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 3945 HWIO_INTFREE();\ 3946 } while (0) 3947 3948 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3949 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 3950 3951 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 3952 3953 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008f8) 3954 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008f8) 3955 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3956 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 3957 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 3958 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 3959 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3960 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3961 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3962 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3963 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3964 do {\ 3965 HWIO_INTLOCK(); \ 3966 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3967 HWIO_INTFREE();\ 3968 } while (0) 3969 3970 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3971 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3972 3973 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 3974 3975 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008fc) 3976 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008fc) 3977 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 3978 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 3979 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 3980 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 3981 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 3982 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 3983 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 3984 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 3985 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 3986 do {\ 3987 HWIO_INTLOCK(); \ 3988 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 3989 HWIO_INTFREE();\ 3990 } while (0) 3991 3992 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3993 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3994 3995 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 3996 3997 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000900) 3998 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000900) 3999 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 4000 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 4001 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 4002 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 4003 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 4004 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 4005 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 4006 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 4007 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 4008 do {\ 4009 HWIO_INTLOCK(); \ 4010 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 4011 HWIO_INTFREE();\ 4012 } while (0) 4013 4014 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4015 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4016 4017 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4018 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4019 4020 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 4021 4022 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000904) 4023 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000904) 4024 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 4025 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 4026 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 4027 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 4028 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 4029 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 4030 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 4031 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 4032 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 4033 do {\ 4034 HWIO_INTLOCK(); \ 4035 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 4036 HWIO_INTFREE();\ 4037 } while (0) 4038 4039 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 4040 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 4041 4042 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4043 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 4044 4045 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 4046 4047 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000908) 4048 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000908) 4049 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 4050 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 4051 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 4052 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 4053 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 4054 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 4055 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 4056 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 4057 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 4058 do {\ 4059 HWIO_INTLOCK(); \ 4060 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 4061 HWIO_INTFREE();\ 4062 } while (0) 4063 4064 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4065 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4066 4067 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4068 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4069 4070 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 4071 4072 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000090c) 4073 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000090c) 4074 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 4075 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 4076 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 4077 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 4078 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 4079 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 4080 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 4081 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 4082 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 4083 do {\ 4084 HWIO_INTLOCK(); \ 4085 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 4086 HWIO_INTFREE();\ 4087 } while (0) 4088 4089 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4090 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 4091 4092 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4093 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 4094 4095 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4096 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4097 4098 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4099 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4100 4101 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4102 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4103 4104 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4105 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 4106 4107 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4108 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4109 4110 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4111 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4112 4113 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4114 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4115 4116 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4117 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 4118 4119 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4120 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4121 4122 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4123 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4124 4125 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 4126 4127 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000910) 4128 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000910) 4129 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4130 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 4131 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 4132 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 4133 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 4134 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 4135 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 4136 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 4137 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4138 do {\ 4139 HWIO_INTLOCK(); \ 4140 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 4141 HWIO_INTFREE();\ 4142 } while (0) 4143 4144 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4145 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4146 4147 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 4148 4149 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000914) 4150 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000914) 4151 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4152 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 4153 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 4154 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 4155 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 4156 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 4157 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 4158 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 4159 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4160 do {\ 4161 HWIO_INTLOCK(); \ 4162 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 4163 HWIO_INTFREE();\ 4164 } while (0) 4165 4166 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4167 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4168 4169 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 4170 4171 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000920) 4172 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000920) 4173 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4174 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 4175 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 4176 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 4177 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4178 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4179 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4180 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4181 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4182 do {\ 4183 HWIO_INTLOCK(); \ 4184 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4185 HWIO_INTFREE();\ 4186 } while (0) 4187 4188 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4189 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4190 4191 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4192 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4193 4194 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4195 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4196 4197 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4198 4199 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000924) 4200 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000924) 4201 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4202 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4203 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4204 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4205 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4206 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4207 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4208 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4209 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4210 do {\ 4211 HWIO_INTLOCK(); \ 4212 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4213 HWIO_INTFREE();\ 4214 } while (0) 4215 4216 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4217 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4218 4219 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4220 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4221 4222 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4223 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4224 4225 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4226 4227 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000928) 4228 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000928) 4229 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4230 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4231 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4232 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4233 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4234 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4235 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4236 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4237 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4238 do {\ 4239 HWIO_INTLOCK(); \ 4240 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4241 HWIO_INTFREE();\ 4242 } while (0) 4243 4244 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4245 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4246 4247 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4248 4249 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000944) 4250 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000944) 4251 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4252 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4253 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4254 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4255 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4256 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4257 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4258 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4259 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4260 do {\ 4261 HWIO_INTLOCK(); \ 4262 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4263 HWIO_INTFREE();\ 4264 } while (0) 4265 4266 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4267 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4268 4269 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4270 4271 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000948) 4272 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000948) 4273 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4274 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4275 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4276 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4277 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4278 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4279 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4280 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4281 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4282 do {\ 4283 HWIO_INTLOCK(); \ 4284 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4285 HWIO_INTFREE();\ 4286 } while (0) 4287 4288 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4289 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4290 4291 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4292 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4293 4294 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4295 4296 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000094c) 4297 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000094c) 4298 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4299 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4300 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4301 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4302 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4303 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4304 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4305 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4306 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4307 do {\ 4308 HWIO_INTLOCK(); \ 4309 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4310 HWIO_INTFREE();\ 4311 } while (0) 4312 4313 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4314 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4315 4316 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4317 4318 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000950) 4319 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000950) 4320 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4321 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4322 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4323 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4324 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4325 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4326 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4327 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4328 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4329 do {\ 4330 HWIO_INTLOCK(); \ 4331 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4332 HWIO_INTFREE();\ 4333 } while (0) 4334 4335 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4336 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4337 4338 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4339 4340 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000954) 4341 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000954) 4342 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4343 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4344 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4345 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4346 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4347 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4348 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4349 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4350 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4351 do {\ 4352 HWIO_INTLOCK(); \ 4353 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4354 HWIO_INTFREE();\ 4355 } while (0) 4356 4357 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4358 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4359 4360 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4361 4362 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000958) 4363 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000958) 4364 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4365 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4366 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4367 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4368 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4369 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4370 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4371 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4372 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4373 do {\ 4374 HWIO_INTLOCK(); \ 4375 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4376 HWIO_INTFREE();\ 4377 } while (0) 4378 4379 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4380 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4381 4382 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4383 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4384 4385 //// Register TCL_R0_TCL2FW_RING_ID //// 4386 4387 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000095c) 4388 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000095c) 4389 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4390 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4391 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4392 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4393 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4394 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4395 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4396 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4397 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4398 do {\ 4399 HWIO_INTLOCK(); \ 4400 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4401 HWIO_INTFREE();\ 4402 } while (0) 4403 4404 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4405 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4406 4407 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4408 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4409 4410 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4411 4412 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000960) 4413 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000960) 4414 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4415 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4416 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4417 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4418 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4419 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4420 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4421 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4422 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4423 do {\ 4424 HWIO_INTLOCK(); \ 4425 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4426 HWIO_INTFREE();\ 4427 } while (0) 4428 4429 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4430 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4431 4432 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4433 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4434 4435 //// Register TCL_R0_TCL2FW_RING_MISC //// 4436 4437 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000964) 4438 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000964) 4439 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4440 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4441 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4442 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4443 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4444 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4445 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4446 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4447 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4448 do {\ 4449 HWIO_INTLOCK(); \ 4450 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4451 HWIO_INTFREE();\ 4452 } while (0) 4453 4454 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4455 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4456 4457 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4458 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4459 4460 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4461 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4462 4463 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4464 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4465 4466 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4467 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4468 4469 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4470 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4471 4472 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4473 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4474 4475 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4476 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4477 4478 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4479 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4480 4481 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4482 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4483 4484 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4485 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4486 4487 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4488 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4489 4490 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4491 4492 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000968) 4493 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000968) 4494 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4495 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4496 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4497 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4498 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4499 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4500 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4501 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4502 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4503 do {\ 4504 HWIO_INTLOCK(); \ 4505 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4506 HWIO_INTFREE();\ 4507 } while (0) 4508 4509 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4510 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4511 4512 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4513 4514 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000096c) 4515 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000096c) 4516 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4517 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4518 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4519 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4520 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4521 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4522 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4523 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4524 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4525 do {\ 4526 HWIO_INTLOCK(); \ 4527 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4528 HWIO_INTFREE();\ 4529 } while (0) 4530 4531 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4532 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4533 4534 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4535 4536 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000978) 4537 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000978) 4538 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4539 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4540 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4541 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4542 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4543 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4544 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4545 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4546 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4547 do {\ 4548 HWIO_INTLOCK(); \ 4549 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4550 HWIO_INTFREE();\ 4551 } while (0) 4552 4553 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4554 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4555 4556 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4557 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4558 4559 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4560 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4561 4562 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4563 4564 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000097c) 4565 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000097c) 4566 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4567 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4568 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4569 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4570 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4571 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4572 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4573 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4574 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4575 do {\ 4576 HWIO_INTLOCK(); \ 4577 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4578 HWIO_INTFREE();\ 4579 } while (0) 4580 4581 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4582 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4583 4584 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4585 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4586 4587 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4588 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4589 4590 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4591 4592 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000980) 4593 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000980) 4594 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4595 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4596 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4597 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4598 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4599 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4600 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4601 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4602 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4603 do {\ 4604 HWIO_INTLOCK(); \ 4605 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4606 HWIO_INTFREE();\ 4607 } while (0) 4608 4609 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4610 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4611 4612 //// Register TCL_R0_TCL2FW_RING_MSI1_BASE_LSB //// 4613 4614 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000099c) 4615 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000099c) 4616 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4617 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_SHFT 0 4618 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \ 4619 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK) 4620 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 4621 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 4622 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 4623 out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 4624 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4625 do {\ 4626 HWIO_INTLOCK(); \ 4627 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x)); \ 4628 HWIO_INTFREE();\ 4629 } while (0) 4630 4631 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4632 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4633 4634 //// Register TCL_R0_TCL2FW_RING_MSI1_BASE_MSB //// 4635 4636 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009a0) 4637 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009a0) 4638 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4639 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_SHFT 0 4640 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \ 4641 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK) 4642 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 4643 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 4644 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 4645 out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 4646 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4647 do {\ 4648 HWIO_INTLOCK(); \ 4649 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x)); \ 4650 HWIO_INTFREE();\ 4651 } while (0) 4652 4653 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4654 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4655 4656 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4657 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4658 4659 //// Register TCL_R0_TCL2FW_RING_MSI1_DATA //// 4660 4661 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) (x+0x000009a4) 4662 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) (x+0x000009a4) 4663 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff 4664 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_SHFT 0 4665 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \ 4666 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK) 4667 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_INM(x, mask) \ 4668 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask) 4669 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUT(x, val) \ 4670 out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), val) 4671 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 4672 do {\ 4673 HWIO_INTLOCK(); \ 4674 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x)); \ 4675 HWIO_INTFREE();\ 4676 } while (0) 4677 4678 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4679 #define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 4680 4681 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4682 4683 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009a8) 4684 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009a8) 4685 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4686 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4687 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4688 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4689 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4690 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4691 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4692 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4693 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4694 do {\ 4695 HWIO_INTLOCK(); \ 4696 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4697 HWIO_INTFREE();\ 4698 } while (0) 4699 4700 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4701 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4702 4703 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4704 4705 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000009ac) 4706 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000009ac) 4707 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4708 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4709 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4710 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4711 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4712 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4713 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4714 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4715 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4716 do {\ 4717 HWIO_INTLOCK(); \ 4718 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4719 HWIO_INTFREE();\ 4720 } while (0) 4721 4722 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4723 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4724 4725 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4726 4727 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009b0) 4728 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009b0) 4729 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4730 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4731 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4732 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4733 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4734 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4735 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4736 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4737 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4738 do {\ 4739 HWIO_INTLOCK(); \ 4740 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4741 HWIO_INTFREE();\ 4742 } while (0) 4743 4744 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4745 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4746 4747 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4748 4749 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009b4) 4750 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009b4) 4751 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4752 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4753 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4754 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4755 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4756 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4757 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4758 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4759 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4760 do {\ 4761 HWIO_INTLOCK(); \ 4762 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4763 HWIO_INTFREE();\ 4764 } while (0) 4765 4766 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4767 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4768 4769 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4770 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4771 4772 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4773 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4774 4775 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4776 4777 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009b8) 4778 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009b8) 4779 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4780 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4781 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4782 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4783 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4784 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4785 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4786 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4787 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4788 do {\ 4789 HWIO_INTLOCK(); \ 4790 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 4791 HWIO_INTFREE();\ 4792 } while (0) 4793 4794 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 4795 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 4796 4797 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 4798 4799 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009bc) 4800 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009bc) 4801 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 4802 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 4803 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 4804 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 4805 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 4806 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 4807 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 4808 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 4809 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 4810 do {\ 4811 HWIO_INTLOCK(); \ 4812 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 4813 HWIO_INTFREE();\ 4814 } while (0) 4815 4816 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 4817 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 4818 4819 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 4820 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 4821 4822 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 4823 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 4824 4825 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 4826 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 4827 4828 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 4829 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 4830 4831 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 4832 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 4833 4834 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 4835 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 4836 4837 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 4838 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 4839 4840 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 4841 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 4842 4843 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 4844 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 4845 4846 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 4847 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 4848 4849 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 4850 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 4851 4852 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 4853 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 4854 4855 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 4856 4857 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009c0) 4858 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009c0) 4859 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 4860 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 4861 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 4862 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 4863 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 4864 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 4865 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 4866 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 4867 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 4868 do {\ 4869 HWIO_INTLOCK(); \ 4870 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 4871 HWIO_INTFREE();\ 4872 } while (0) 4873 4874 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 4875 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 4876 4877 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 4878 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 4879 4880 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 4881 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 4882 4883 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 4884 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 4885 4886 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 4887 4888 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009c4) 4889 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009c4) 4890 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 4891 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 4892 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 4893 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 4894 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 4895 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 4896 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 4897 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 4898 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 4899 do {\ 4900 HWIO_INTLOCK(); \ 4901 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 4902 HWIO_INTFREE();\ 4903 } while (0) 4904 4905 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 4906 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 4907 4908 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 4909 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 4910 4911 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 4912 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 4913 4914 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 4915 4916 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009c8) 4917 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009c8) 4918 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 4919 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 4920 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 4921 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 4922 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 4923 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 4924 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 4925 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 4926 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 4927 do {\ 4928 HWIO_INTLOCK(); \ 4929 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 4930 HWIO_INTFREE();\ 4931 } while (0) 4932 4933 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 4934 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 4935 4936 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4937 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 4938 4939 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 4940 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 4941 4942 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 4943 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 4944 4945 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 4946 4947 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009cc) 4948 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009cc) 4949 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 4950 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 4951 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 4952 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 4953 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 4954 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 4955 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 4956 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 4957 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 4958 do {\ 4959 HWIO_INTLOCK(); \ 4960 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 4961 HWIO_INTFREE();\ 4962 } while (0) 4963 4964 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 4965 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 4966 4967 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4968 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 4969 4970 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 4971 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 4972 4973 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 4974 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 4975 4976 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 4977 4978 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009d0) 4979 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009d0) 4980 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 4981 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 4982 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 4983 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 4984 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 4985 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 4986 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 4987 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 4988 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 4989 do {\ 4990 HWIO_INTLOCK(); \ 4991 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 4992 HWIO_INTFREE();\ 4993 } while (0) 4994 4995 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 4996 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 4997 4998 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 4999 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 5000 5001 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 5002 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 5003 5004 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 5005 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 5006 5007 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 5008 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 5009 5010 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 5011 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 5012 5013 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 5014 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 5015 5016 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 5017 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 5018 5019 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 5020 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 5021 5022 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 5023 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 5024 5025 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 5026 5027 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009d4) 5028 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009d4) 5029 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 5030 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 5031 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 5032 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 5033 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 5034 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 5035 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 5036 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 5037 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 5038 do {\ 5039 HWIO_INTLOCK(); \ 5040 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 5041 HWIO_INTFREE();\ 5042 } while (0) 5043 5044 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 5045 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 5046 5047 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 5048 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 5049 5050 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 5051 5052 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009d8) 5053 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009d8) 5054 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 5055 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 5056 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 5057 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 5058 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 5059 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 5060 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 5061 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 5062 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 5063 do {\ 5064 HWIO_INTLOCK(); \ 5065 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 5066 HWIO_INTFREE();\ 5067 } while (0) 5068 5069 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 5070 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 5071 5072 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 5073 5074 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009dc) 5075 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009dc) 5076 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 5077 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 5078 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 5079 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 5080 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 5081 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 5082 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 5083 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 5084 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 5085 do {\ 5086 HWIO_INTLOCK(); \ 5087 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 5088 HWIO_INTFREE();\ 5089 } while (0) 5090 5091 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 5092 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 5093 5094 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 5095 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 5096 5097 //// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// 5098 5099 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009e0) 5100 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009e0) 5101 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 5102 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 5103 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 5104 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 5105 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 5106 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 5107 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 5108 out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 5109 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 5110 do {\ 5111 HWIO_INTLOCK(); \ 5112 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 5113 HWIO_INTFREE();\ 5114 } while (0) 5115 5116 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 5117 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 5118 5119 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 5120 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 5121 5122 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 5123 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 5124 5125 //// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// 5126 5127 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009e4) 5128 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009e4) 5129 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 5130 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 5131 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 5132 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 5133 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 5134 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 5135 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 5136 out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 5137 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 5138 do {\ 5139 HWIO_INTLOCK(); \ 5140 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 5141 HWIO_INTFREE();\ 5142 } while (0) 5143 5144 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 5145 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 5146 5147 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 5148 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 5149 5150 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 5151 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 5152 5153 //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// 5154 5155 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009e8) 5156 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009e8) 5157 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 5158 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 5159 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ 5160 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) 5161 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 5162 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 5163 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 5164 out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 5165 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 5166 do {\ 5167 HWIO_INTLOCK(); \ 5168 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ 5169 HWIO_INTFREE();\ 5170 } while (0) 5171 5172 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 5173 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 5174 5175 //// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// 5176 5177 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009ec) 5178 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009ec) 5179 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 5180 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 5181 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ 5182 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) 5183 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 5184 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 5185 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 5186 out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 5187 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 5188 do {\ 5189 HWIO_INTLOCK(); \ 5190 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ 5191 HWIO_INTFREE();\ 5192 } while (0) 5193 5194 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 5195 #define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 5196 5197 //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// 5198 5199 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009f0) 5200 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009f0) 5201 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff 5202 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 5203 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ 5204 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) 5205 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ 5206 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) 5207 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ 5208 out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) 5209 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ 5210 do {\ 5211 HWIO_INTLOCK(); \ 5212 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ 5213 HWIO_INTFREE();\ 5214 } while (0) 5215 5216 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff 5217 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 5218 5219 //// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// 5220 5221 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009f4) 5222 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009f4) 5223 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff 5224 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 5225 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ 5226 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) 5227 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ 5228 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) 5229 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ 5230 out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) 5231 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ 5232 do {\ 5233 HWIO_INTLOCK(); \ 5234 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ 5235 HWIO_INTFREE();\ 5236 } while (0) 5237 5238 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff 5239 #define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 5240 5241 //// Register TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL //// 5242 5243 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000009f8) 5244 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000009f8) 5245 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f 5246 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 5247 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ 5248 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) 5249 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ 5250 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) 5251 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ 5252 out_dword( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) 5253 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ 5254 do {\ 5255 HWIO_INTLOCK(); \ 5256 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ 5257 HWIO_INTFREE();\ 5258 } while (0) 5259 5260 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 5261 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf 5262 5263 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 5264 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 5265 5266 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 5267 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 5268 5269 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f 5270 #define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 5271 5272 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 5273 5274 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009fc) 5275 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009fc) 5276 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5277 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 5278 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 5279 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 5280 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5281 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5282 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5283 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 5284 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5285 do {\ 5286 HWIO_INTLOCK(); \ 5287 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 5288 HWIO_INTFREE();\ 5289 } while (0) 5290 5291 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5292 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5293 5294 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 5295 5296 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000a00) 5297 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000a00) 5298 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5299 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 5300 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 5301 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 5302 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5303 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5304 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5305 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5306 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5307 do {\ 5308 HWIO_INTLOCK(); \ 5309 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 5310 HWIO_INTFREE();\ 5311 } while (0) 5312 5313 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5314 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5315 5316 //// Register TCL_R0_ASE_GST_SIZE //// 5317 5318 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000a04) 5319 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000a04) 5320 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 5321 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 5322 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 5323 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 5324 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 5325 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 5326 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 5327 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 5328 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 5329 do {\ 5330 HWIO_INTLOCK(); \ 5331 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5332 HWIO_INTFREE();\ 5333 } while (0) 5334 5335 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5336 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5337 5338 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5339 5340 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000a08) 5341 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000a08) 5342 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff 5343 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5344 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5345 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5346 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5347 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5348 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5349 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5350 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5351 do {\ 5352 HWIO_INTLOCK(); \ 5353 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5354 HWIO_INTFREE();\ 5355 } while (0) 5356 5357 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5358 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5359 5360 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x00002000 5361 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 0xd 5362 5363 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x00001000 5364 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 0xc 5365 5366 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x00000800 5367 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 0xb 5368 5369 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5370 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5371 5372 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5373 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5374 5375 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5376 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5377 5378 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5379 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5380 5381 //// Register TCL_R0_ASE_WATCHDOG //// 5382 5383 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000a0c) 5384 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000a0c) 5385 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5386 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5387 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5388 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5389 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5390 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5391 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5392 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5393 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5394 do {\ 5395 HWIO_INTLOCK(); \ 5396 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5397 HWIO_INTFREE();\ 5398 } while (0) 5399 5400 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5401 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5402 5403 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5404 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5405 5406 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5407 5408 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000a10) 5409 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000a10) 5410 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5411 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5412 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5413 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5414 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5415 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5416 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5417 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5418 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5419 do {\ 5420 HWIO_INTLOCK(); \ 5421 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5422 HWIO_INTFREE();\ 5423 } while (0) 5424 5425 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5426 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5427 5428 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5429 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5430 5431 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffffe00 5432 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0x9 5433 5434 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000100 5435 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x8 5436 5437 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000080 5438 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x7 5439 5440 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000040 5441 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x6 5442 5443 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000020 5444 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x5 5445 5446 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5447 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5448 5449 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5450 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5451 5452 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5453 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5454 5455 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5456 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5457 5458 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5459 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5460 5461 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5462 5463 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000a14) 5464 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000a14) 5465 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5466 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5467 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5468 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5469 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5470 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5471 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5472 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5473 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5474 do {\ 5475 HWIO_INTLOCK(); \ 5476 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5477 HWIO_INTFREE();\ 5478 } while (0) 5479 5480 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5481 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5482 5483 //// Register TCL_R1_CACHE_FLUSH //// 5484 5485 #define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) (x+0x00001000) 5486 #define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) (x+0x00001000) 5487 #define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x00000003 5488 #define HWIO_TCL_R1_CACHE_FLUSH_SHFT 0 5489 #define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \ 5490 in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), HWIO_TCL_R1_CACHE_FLUSH_RMSK) 5491 #define HWIO_TCL_R1_CACHE_FLUSH_INM(x, mask) \ 5492 in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask) 5493 #define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, val) \ 5494 out_dword( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), val) 5495 #define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x, mask, val) \ 5496 do {\ 5497 HWIO_INTLOCK(); \ 5498 out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask, val, HWIO_TCL_R1_CACHE_FLUSH_IN(x)); \ 5499 HWIO_INTFREE();\ 5500 } while (0) 5501 5502 #define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x00000002 5503 #define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 0x1 5504 5505 #define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x00000001 5506 #define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0x0 5507 5508 //// Register TCL_R1_SM_STATES_IX_0 //// 5509 5510 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001004) 5511 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001004) 5512 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x3fffffff 5513 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5514 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5515 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5516 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5517 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5518 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5519 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5520 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5521 do {\ 5522 HWIO_INTLOCK(); \ 5523 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5524 HWIO_INTFREE();\ 5525 } while (0) 5526 5527 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_BMSK 0x30000000 5528 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_SHFT 0x1c 5529 5530 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x0e000000 5531 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x19 5532 5533 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x01e00000 5534 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5535 5536 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5537 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5538 5539 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5540 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5541 5542 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x00007000 5543 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 0xc 5544 5545 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5546 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5547 5548 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5549 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5550 5551 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5552 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5553 5554 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5555 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5556 5557 //// Register TCL_R1_SM_STATES_IX_1 //// 5558 5559 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001008) 5560 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001008) 5561 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x001fffff 5562 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5563 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5564 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5565 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5566 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5567 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5568 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5569 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5570 do {\ 5571 HWIO_INTLOCK(); \ 5572 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5573 HWIO_INTFREE();\ 5574 } while (0) 5575 5576 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0x001c0000 5577 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 0x12 5578 5579 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 5580 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf 5581 5582 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5583 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5584 5585 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5586 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5587 5588 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5589 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5590 5591 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5592 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5593 5594 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5595 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5596 5597 //// Register TCL_R1_STATUS //// 5598 5599 #define HWIO_TCL_R1_STATUS_ADDR(x) (x+0x0000100c) 5600 #define HWIO_TCL_R1_STATUS_PHYS(x) (x+0x0000100c) 5601 #define HWIO_TCL_R1_STATUS_RMSK 0x07ffffff 5602 #define HWIO_TCL_R1_STATUS_SHFT 0 5603 #define HWIO_TCL_R1_STATUS_IN(x) \ 5604 in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), HWIO_TCL_R1_STATUS_RMSK) 5605 #define HWIO_TCL_R1_STATUS_INM(x, mask) \ 5606 in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), mask) 5607 #define HWIO_TCL_R1_STATUS_OUT(x, val) \ 5608 out_dword( HWIO_TCL_R1_STATUS_ADDR(x), val) 5609 #define HWIO_TCL_R1_STATUS_OUTM(x, mask, val) \ 5610 do {\ 5611 HWIO_INTLOCK(); \ 5612 out_dword_masked_ns(HWIO_TCL_R1_STATUS_ADDR(x), mask, val, HWIO_TCL_R1_STATUS_IN(x)); \ 5613 HWIO_INTFREE();\ 5614 } while (0) 5615 5616 #define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_BMSK 0x04000000 5617 #define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_SHFT 0x1a 5618 5619 #define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_BMSK 0x02000000 5620 #define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_SHFT 0x19 5621 5622 #define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_BMSK 0x01000000 5623 #define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_SHFT 0x18 5624 5625 #define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_BMSK 0x00800000 5626 #define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_SHFT 0x17 5627 5628 #define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x00400000 5629 #define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_SHFT 0x16 5630 5631 #define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_BMSK 0x00200000 5632 #define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_SHFT 0x15 5633 5634 #define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_BMSK 0x00100000 5635 #define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_SHFT 0x14 5636 5637 #define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_BMSK 0x00080000 5638 #define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_SHFT 0x13 5639 5640 #define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_BMSK 0x00040000 5641 #define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_SHFT 0x12 5642 5643 #define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_BMSK 0x00020000 5644 #define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_SHFT 0x11 5645 5646 #define HWIO_TCL_R1_STATUS_ASE_IDLE_BMSK 0x00010000 5647 #define HWIO_TCL_R1_STATUS_ASE_IDLE_SHFT 0x10 5648 5649 #define HWIO_TCL_R1_STATUS_PARSER_IDLE_BMSK 0x00008000 5650 #define HWIO_TCL_R1_STATUS_PARSER_IDLE_SHFT 0xf 5651 5652 #define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_BMSK 0x00004000 5653 #define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_SHFT 0xe 5654 5655 #define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x00002000 5656 #define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 0xd 5657 5658 #define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_BMSK 0x00001000 5659 #define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_SHFT 0xc 5660 5661 #define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x00000800 5662 #define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_SHFT 0xb 5663 5664 #define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x00000400 5665 #define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 0xa 5666 5667 #define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x00000200 5668 #define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_SHFT 0x9 5669 5670 #define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x00000100 5671 #define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_SHFT 0x8 5672 5673 #define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x00000080 5674 #define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_SHFT 0x7 5675 5676 #define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x00000040 5677 #define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_SHFT 0x6 5678 5679 #define HWIO_TCL_R1_STATUS_GXI_IDLE_BMSK 0x00000020 5680 #define HWIO_TCL_R1_STATUS_GXI_IDLE_SHFT 0x5 5681 5682 #define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_BMSK 0x00000010 5683 #define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_SHFT 0x4 5684 5685 #define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x00000008 5686 #define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_SHFT 0x3 5687 5688 #define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x00000004 5689 #define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_SHFT 0x2 5690 5691 #define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_BMSK 0x00000002 5692 #define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_SHFT 0x1 5693 5694 #define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_BMSK 0x00000001 5695 #define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_SHFT 0x0 5696 5697 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5698 5699 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001010) 5700 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001010) 5701 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff 5702 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5703 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5704 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5705 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5706 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5707 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5708 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5709 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5710 do {\ 5711 HWIO_INTLOCK(); \ 5712 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5713 HWIO_INTFREE();\ 5714 } while (0) 5715 5716 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000 5717 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d 5718 5719 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5720 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5721 5722 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5723 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5724 5725 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5726 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5727 5728 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5729 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5730 5731 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5732 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5733 5734 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5735 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5736 5737 //// Register TCL_R1_TESTBUS_LOW //// 5738 5739 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001014) 5740 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001014) 5741 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5742 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5743 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5744 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5745 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5746 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5747 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5748 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5749 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5750 do {\ 5751 HWIO_INTLOCK(); \ 5752 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5753 HWIO_INTFREE();\ 5754 } while (0) 5755 5756 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5757 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5758 5759 //// Register TCL_R1_TESTBUS_HIGH //// 5760 5761 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001018) 5762 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001018) 5763 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5764 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5765 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5766 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5767 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5768 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5769 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5770 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5771 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5772 do {\ 5773 HWIO_INTLOCK(); \ 5774 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5775 HWIO_INTFREE();\ 5776 } while (0) 5777 5778 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5779 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5780 5781 //// Register TCL_R1_EVENTMASK_IX_0 //// 5782 5783 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x0000101c) 5784 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x0000101c) 5785 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5786 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5787 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5788 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5789 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5790 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5791 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5792 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5793 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5794 do {\ 5795 HWIO_INTLOCK(); \ 5796 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5797 HWIO_INTFREE();\ 5798 } while (0) 5799 5800 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5801 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5802 5803 //// Register TCL_R1_EVENTMASK_IX_1 //// 5804 5805 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001020) 5806 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001020) 5807 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5808 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5809 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5810 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5811 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5812 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5813 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5814 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5815 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5816 do {\ 5817 HWIO_INTLOCK(); \ 5818 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5819 HWIO_INTFREE();\ 5820 } while (0) 5821 5822 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5823 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5824 5825 //// Register TCL_R1_EVENTMASK_IX_2 //// 5826 5827 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001024) 5828 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001024) 5829 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5830 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5831 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5832 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5833 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5834 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5835 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5836 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5837 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5838 do {\ 5839 HWIO_INTLOCK(); \ 5840 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5841 HWIO_INTFREE();\ 5842 } while (0) 5843 5844 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5845 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5846 5847 //// Register TCL_R1_EVENTMASK_IX_3 //// 5848 5849 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001028) 5850 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001028) 5851 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5852 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5853 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5854 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5855 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5856 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5857 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5858 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5859 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5860 do {\ 5861 HWIO_INTLOCK(); \ 5862 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5863 HWIO_INTFREE();\ 5864 } while (0) 5865 5866 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5867 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5868 5869 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5870 5871 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x0000102c) 5872 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x0000102c) 5873 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5874 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5875 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5876 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5877 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5878 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5879 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5880 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5881 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5882 do {\ 5883 HWIO_INTLOCK(); \ 5884 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5885 HWIO_INTFREE();\ 5886 } while (0) 5887 5888 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5889 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5890 5891 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5892 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5893 5894 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5895 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5896 5897 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5898 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5899 5900 //// Register TCL_R1_SPARE_REGISTER //// 5901 5902 #define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) (x+0x00001030) 5903 #define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) (x+0x00001030) 5904 #define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff 5905 #define HWIO_TCL_R1_SPARE_REGISTER_SHFT 0 5906 #define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \ 5907 in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), HWIO_TCL_R1_SPARE_REGISTER_RMSK) 5908 #define HWIO_TCL_R1_SPARE_REGISTER_INM(x, mask) \ 5909 in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask) 5910 #define HWIO_TCL_R1_SPARE_REGISTER_OUT(x, val) \ 5911 out_dword( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), val) 5912 #define HWIO_TCL_R1_SPARE_REGISTER_OUTM(x, mask, val) \ 5913 do {\ 5914 HWIO_INTLOCK(); \ 5915 out_dword_masked_ns(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R1_SPARE_REGISTER_IN(x)); \ 5916 HWIO_INTFREE();\ 5917 } while (0) 5918 5919 #define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_BMSK 0xffffffff 5920 #define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_SHFT 0x0 5921 5922 //// Register TCL_R1_END_OF_TEST_CHECK //// 5923 5924 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001034) 5925 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001034) 5926 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5927 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5928 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5929 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5930 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5931 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5932 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5933 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5934 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5935 do {\ 5936 HWIO_INTLOCK(); \ 5937 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5938 HWIO_INTFREE();\ 5939 } while (0) 5940 5941 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5942 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5943 5944 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5945 5946 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001038) 5947 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001038) 5948 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5949 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5950 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5951 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5952 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5953 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5954 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5955 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5956 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5957 do {\ 5958 HWIO_INTLOCK(); \ 5959 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5960 HWIO_INTFREE();\ 5961 } while (0) 5962 5963 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5964 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5965 5966 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5967 5968 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x0000103c) 5969 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x0000103c) 5970 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5971 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5972 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5973 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5974 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5975 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5976 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5977 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5978 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5979 do {\ 5980 HWIO_INTLOCK(); \ 5981 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5982 HWIO_INTFREE();\ 5983 } while (0) 5984 5985 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5986 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5987 5988 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5989 5990 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001040) 5991 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001040) 5992 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5993 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5994 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5995 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5996 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5997 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5998 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5999 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 6000 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 6001 do {\ 6002 HWIO_INTLOCK(); \ 6003 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 6004 HWIO_INTFREE();\ 6005 } while (0) 6006 6007 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 6008 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 6009 6010 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 6011 6012 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001044) 6013 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001044) 6014 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 6015 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 6016 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 6017 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6018 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6019 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6020 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6021 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6022 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6023 do {\ 6024 HWIO_INTLOCK(); \ 6025 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6026 HWIO_INTFREE();\ 6027 } while (0) 6028 6029 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6030 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6031 6032 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6033 6034 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001048) 6035 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001048) 6036 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6037 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6038 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6039 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6040 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6041 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6042 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6043 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6044 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6045 do {\ 6046 HWIO_INTLOCK(); \ 6047 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6048 HWIO_INTFREE();\ 6049 } while (0) 6050 6051 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6052 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6053 6054 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6055 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6056 6057 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 6058 6059 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x0000104c) 6060 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x0000104c) 6061 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6062 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6063 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6064 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6065 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6066 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6067 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6068 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6069 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6070 do {\ 6071 HWIO_INTLOCK(); \ 6072 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6073 HWIO_INTFREE();\ 6074 } while (0) 6075 6076 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6077 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6078 6079 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6080 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6081 6082 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6083 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6084 6085 //// Register TCL_R1_ASE_SM_STATES //// 6086 6087 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001050) 6088 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001050) 6089 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fff0f 6090 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 6091 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 6092 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 6093 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 6094 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 6095 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 6096 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 6097 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 6098 do {\ 6099 HWIO_INTLOCK(); \ 6100 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 6101 HWIO_INTFREE();\ 6102 } while (0) 6103 6104 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6105 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6106 6107 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6108 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6109 6110 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6111 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6112 6113 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6114 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6115 6116 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6117 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6118 6119 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6120 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6121 6122 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6123 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6124 6125 //// Register TCL_R1_ASE_CACHE_DEBUG //// 6126 6127 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001054) 6128 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001054) 6129 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 6130 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 6131 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 6132 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 6133 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 6134 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 6135 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 6136 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 6137 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 6138 do {\ 6139 HWIO_INTLOCK(); \ 6140 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 6141 HWIO_INTFREE();\ 6142 } while (0) 6143 6144 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6145 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6146 6147 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 6148 6149 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001058) 6150 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001058) 6151 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6152 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6153 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6154 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6155 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6156 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6157 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6158 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6159 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6160 do {\ 6161 HWIO_INTLOCK(); \ 6162 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6163 HWIO_INTFREE();\ 6164 } while (0) 6165 6166 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6167 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6168 6169 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6170 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6171 6172 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6173 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6174 6175 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6176 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6177 6178 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 6179 6180 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x105C+0x4*n) 6181 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x105C+0x4*n) 6182 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6183 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 6184 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 6185 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6186 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 6187 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6188 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6189 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6190 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6191 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6192 do {\ 6193 HWIO_INTLOCK(); \ 6194 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6195 HWIO_INTFREE();\ 6196 } while (0) 6197 6198 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6199 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6200 6201 //// Register TCL_R2_SW2TCL1_RING_HP //// 6202 6203 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 6204 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 6205 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff 6206 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 6207 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 6208 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 6209 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 6210 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 6211 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 6212 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 6213 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 6214 do {\ 6215 HWIO_INTLOCK(); \ 6216 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 6217 HWIO_INTFREE();\ 6218 } while (0) 6219 6220 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff 6221 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6222 6223 //// Register TCL_R2_SW2TCL1_RING_TP //// 6224 6225 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 6226 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 6227 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff 6228 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 6229 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 6230 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 6231 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 6232 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 6233 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 6234 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 6235 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 6236 do {\ 6237 HWIO_INTLOCK(); \ 6238 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 6239 HWIO_INTFREE();\ 6240 } while (0) 6241 6242 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff 6243 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6244 6245 //// Register TCL_R2_SW2TCL2_RING_HP //// 6246 6247 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 6248 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 6249 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff 6250 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 6251 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 6252 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 6253 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 6254 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 6255 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 6256 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 6257 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 6258 do {\ 6259 HWIO_INTLOCK(); \ 6260 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 6261 HWIO_INTFREE();\ 6262 } while (0) 6263 6264 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff 6265 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 6266 6267 //// Register TCL_R2_SW2TCL2_RING_TP //// 6268 6269 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 6270 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 6271 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff 6272 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 6273 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 6274 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 6275 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 6276 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 6277 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 6278 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 6279 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 6280 do {\ 6281 HWIO_INTLOCK(); \ 6282 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 6283 HWIO_INTFREE();\ 6284 } while (0) 6285 6286 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff 6287 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 6288 6289 //// Register TCL_R2_SW2TCL3_RING_HP //// 6290 6291 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 6292 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 6293 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff 6294 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 6295 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 6296 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 6297 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 6298 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 6299 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 6300 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 6301 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 6302 do {\ 6303 HWIO_INTLOCK(); \ 6304 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 6305 HWIO_INTFREE();\ 6306 } while (0) 6307 6308 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff 6309 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 6310 6311 //// Register TCL_R2_SW2TCL3_RING_TP //// 6312 6313 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 6314 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 6315 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff 6316 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 6317 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 6318 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 6319 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 6320 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 6321 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 6322 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 6323 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 6324 do {\ 6325 HWIO_INTLOCK(); \ 6326 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 6327 HWIO_INTFREE();\ 6328 } while (0) 6329 6330 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff 6331 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 6332 6333 //// Register TCL_R2_SW2TCL_CREDIT_RING_HP //// 6334 6335 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) (x+0x00002018) 6336 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) (x+0x00002018) 6337 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0x000fffff 6338 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_SHFT 0 6339 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ 6340 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK) 6341 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, mask) \ 6342 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask) 6343 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, val) \ 6344 out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), val) 6345 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x, mask, val) \ 6346 do {\ 6347 HWIO_INTLOCK(); \ 6348 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)); \ 6349 HWIO_INTFREE();\ 6350 } while (0) 6351 6352 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0x000fffff 6353 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0x0 6354 6355 //// Register TCL_R2_SW2TCL_CREDIT_RING_TP //// 6356 6357 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) (x+0x0000201c) 6358 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) (x+0x0000201c) 6359 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0x000fffff 6360 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_SHFT 0 6361 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ 6362 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK) 6363 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, mask) \ 6364 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask) 6365 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, val) \ 6366 out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), val) 6367 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x, mask, val) \ 6368 do {\ 6369 HWIO_INTLOCK(); \ 6370 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)); \ 6371 HWIO_INTFREE();\ 6372 } while (0) 6373 6374 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0x000fffff 6375 #define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0x0 6376 6377 //// Register TCL_R2_FW2TCL1_RING_HP //// 6378 6379 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 6380 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 6381 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 6382 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 6383 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 6384 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 6385 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 6386 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 6387 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 6388 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 6389 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 6390 do {\ 6391 HWIO_INTLOCK(); \ 6392 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 6393 HWIO_INTFREE();\ 6394 } while (0) 6395 6396 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6397 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6398 6399 //// Register TCL_R2_FW2TCL1_RING_TP //// 6400 6401 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 6402 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 6403 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 6404 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 6405 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 6406 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 6407 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 6408 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 6409 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 6410 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 6411 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 6412 do {\ 6413 HWIO_INTLOCK(); \ 6414 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 6415 HWIO_INTFREE();\ 6416 } while (0) 6417 6418 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6419 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6420 6421 //// Register TCL_R2_TCL2TQM_RING_HP //// 6422 6423 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 6424 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 6425 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 6426 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 6427 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 6428 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 6429 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 6430 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 6431 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6432 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6433 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6434 do {\ 6435 HWIO_INTLOCK(); \ 6436 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6437 HWIO_INTFREE();\ 6438 } while (0) 6439 6440 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6441 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6442 6443 //// Register TCL_R2_TCL2TQM_RING_TP //// 6444 6445 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6446 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6447 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6448 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6449 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6450 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6451 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6452 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6453 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6454 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6455 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6456 do {\ 6457 HWIO_INTLOCK(); \ 6458 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 6459 HWIO_INTFREE();\ 6460 } while (0) 6461 6462 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6463 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 6464 6465 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 6466 6467 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 6468 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 6469 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 6470 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 6471 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 6472 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 6473 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 6474 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 6475 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 6476 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 6477 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 6478 do {\ 6479 HWIO_INTLOCK(); \ 6480 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 6481 HWIO_INTFREE();\ 6482 } while (0) 6483 6484 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6485 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 6486 6487 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 6488 6489 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 6490 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 6491 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 6492 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 6493 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 6494 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 6495 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 6496 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 6497 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 6498 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 6499 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 6500 do {\ 6501 HWIO_INTLOCK(); \ 6502 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 6503 HWIO_INTFREE();\ 6504 } while (0) 6505 6506 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6507 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 6508 6509 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 6510 6511 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 6512 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 6513 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 6514 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6515 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6516 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6517 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6518 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6519 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6520 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6521 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6522 do {\ 6523 HWIO_INTLOCK(); \ 6524 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6525 HWIO_INTFREE();\ 6526 } while (0) 6527 6528 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6529 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6530 6531 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6532 6533 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6534 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6535 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6536 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6537 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6538 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6539 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6540 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6541 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6542 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6543 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6544 do {\ 6545 HWIO_INTLOCK(); \ 6546 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6547 HWIO_INTFREE();\ 6548 } while (0) 6549 6550 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6551 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6552 6553 //// Register TCL_R2_TCL2FW_RING_HP //// 6554 6555 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6556 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6557 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6558 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6559 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6560 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6561 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6562 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6563 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6564 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6565 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6566 do {\ 6567 HWIO_INTLOCK(); \ 6568 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6569 HWIO_INTFREE();\ 6570 } while (0) 6571 6572 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6573 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6574 6575 //// Register TCL_R2_TCL2FW_RING_TP //// 6576 6577 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6578 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6579 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6580 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6581 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6582 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6583 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6584 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6585 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6586 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6587 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6588 do {\ 6589 HWIO_INTLOCK(); \ 6590 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6591 HWIO_INTFREE();\ 6592 } while (0) 6593 6594 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6595 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6596 6597 6598 #endif 6599 6600