1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _TX_MSDU_EXTENSION_H_ 25 #define _TX_MSDU_EXTENSION_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] 34 // 1 l2_length[15:0], ip_length[31:16] 35 // 2 tcp_seq_number[31:0] 36 // 3 ip_identification[15:0], udp_length[31:16] 37 // 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] 38 // 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] 39 // 6 buf0_ptr_31_0[31:0] 40 // 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] 41 // 8 buf1_ptr_31_0[31:0] 42 // 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] 43 // 10 buf2_ptr_31_0[31:0] 44 // 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] 45 // 12 buf3_ptr_31_0[31:0] 46 // 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] 47 // 14 buf4_ptr_31_0[31:0] 48 // 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] 49 // 16 buf5_ptr_31_0[31:0] 50 // 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] 51 // 52 // ################ END SUMMARY ################# 53 54 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 55 56 struct tx_msdu_extension { 57 uint32_t tso_enable : 1, //[0] 58 reserved_0a : 6, //[6:1] 59 tcp_flag : 9, //[15:7] 60 tcp_flag_mask : 9, //[24:16] 61 reserved_0b : 7; //[31:25] 62 uint32_t l2_length : 16, //[15:0] 63 ip_length : 16; //[31:16] 64 uint32_t tcp_seq_number : 32; //[31:0] 65 uint32_t ip_identification : 16, //[15:0] 66 udp_length : 16; //[31:16] 67 uint32_t checksum_offset : 14, //[13:0] 68 partial_checksum_en : 1, //[14] 69 reserved_4a : 1, //[15] 70 payload_start_offset : 14, //[29:16] 71 reserved_4b : 2; //[31:30] 72 uint32_t payload_end_offset : 14, //[13:0] 73 reserved_5a : 2, //[15:14] 74 wds : 1, //[16] 75 reserved_5b : 15; //[31:17] 76 uint32_t buf0_ptr_31_0 : 32; //[31:0] 77 uint32_t buf0_ptr_39_32 : 8, //[7:0] 78 reserved_7a : 8, //[15:8] 79 buf0_len : 16; //[31:16] 80 uint32_t buf1_ptr_31_0 : 32; //[31:0] 81 uint32_t buf1_ptr_39_32 : 8, //[7:0] 82 reserved_9a : 8, //[15:8] 83 buf1_len : 16; //[31:16] 84 uint32_t buf2_ptr_31_0 : 32; //[31:0] 85 uint32_t buf2_ptr_39_32 : 8, //[7:0] 86 reserved_11a : 8, //[15:8] 87 buf2_len : 16; //[31:16] 88 uint32_t buf3_ptr_31_0 : 32; //[31:0] 89 uint32_t buf3_ptr_39_32 : 8, //[7:0] 90 reserved_13a : 8, //[15:8] 91 buf3_len : 16; //[31:16] 92 uint32_t buf4_ptr_31_0 : 32; //[31:0] 93 uint32_t buf4_ptr_39_32 : 8, //[7:0] 94 reserved_15a : 8, //[15:8] 95 buf4_len : 16; //[31:16] 96 uint32_t buf5_ptr_31_0 : 32; //[31:0] 97 uint32_t buf5_ptr_39_32 : 8, //[7:0] 98 reserved_17a : 8, //[15:8] 99 buf5_len : 16; //[31:16] 100 }; 101 102 /* 103 104 tso_enable 105 106 Enable transmit segmentation offload <legal all> 107 108 reserved_0a 109 110 FW will set to 0, MAC will ignore. <legal 0> 111 112 tcp_flag 113 114 TCP flags 115 116 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 117 118 tcp_flag_mask 119 120 TCP flag mask. Tcp_flag is inserted into the header 121 based on the mask, if tso is enabled 122 123 reserved_0b 124 125 FW will set to 0, MAC will ignore. <legal 0> 126 127 l2_length 128 129 L2 length for the msdu, if tso is enabled <legal all> 130 131 ip_length 132 133 Ip length for the msdu, if tso is enabled <legal all> 134 135 tcp_seq_number 136 137 Tcp_seq_number for the msdu, if tso is enabled <legal 138 all> 139 140 ip_identification 141 142 Ip_identification for the msdu, if tso is enabled <legal 143 all> 144 145 udp_length 146 147 TXDMA is copies this field into MSDU START TLV 148 149 checksum_offset 150 151 The calculated checksum from start offset to end offset 152 will be added to the checksum at the offset given by this 153 field<legal all> 154 155 partial_checksum_en 156 157 Partial Checksum Enable Bit. 158 159 <legal 0-1> 160 161 reserved_4a 162 163 <Legal 0> 164 165 payload_start_offset 166 167 L4 checksum calculations will start fromt this offset 168 169 <Legal all> 170 171 reserved_4b 172 173 <Legal 0> 174 175 payload_end_offset 176 177 L4 checksum calculations will end at this offset. 178 179 <Legal all> 180 181 reserved_5a 182 183 <Legal 0> 184 185 wds 186 187 If set the current packet is 4-address frame. Required 188 because an aggregate can include some frames with 3 address 189 format and other frames with 4 address format. Used by the 190 OLE during encapsulation. 191 192 Note: there is also global wds tx control in the 193 TX_PEER_ENTRY 194 195 <legal all> 196 197 reserved_5b 198 199 <Legal 0> 200 201 buf0_ptr_31_0 202 203 Lower 32 bits of the first buffer pointer 204 205 206 207 NOTE: SW/FW manages the 'cookie' info related to this 208 buffer together with the 'cookie' info for this 209 MSDU_EXTENSION descriptor 210 211 <legal all> 212 213 buf0_ptr_39_32 214 215 Upper 8 bits of the first buffer pointer <legal all> 216 217 reserved_7a 218 219 <Legal 0> 220 221 buf0_len 222 223 Length of the first buffer <legal all> 224 225 buf1_ptr_31_0 226 227 Lower 32 bits of the second buffer pointer 228 229 230 231 NOTE: SW/FW manages the 'cookie' info related to this 232 buffer together with the 'cookie' info for this 233 MSDU_EXTENSION descriptor 234 235 <legal all> 236 237 buf1_ptr_39_32 238 239 Upper 8 bits of the second buffer pointer <legal all> 240 241 reserved_9a 242 243 <Legal 0> 244 245 buf1_len 246 247 Length of the second buffer <legal all> 248 249 buf2_ptr_31_0 250 251 Lower 32 bits of the third buffer pointer 252 253 NOTE: SW/FW manages the 'cookie' info related to this 254 buffer together with the 'cookie' info for this 255 MSDU_EXTENSION descriptor 256 257 <legal all> 258 259 buf2_ptr_39_32 260 261 Upper 8 bits of the third buffer pointer <legal all> 262 263 reserved_11a 264 265 <Legal 0> 266 267 buf2_len 268 269 Length of the third buffer <legal all> 270 271 buf3_ptr_31_0 272 273 Lower 32 bits of the fourth buffer pointer 274 275 276 277 NOTE: SW/FW manages the 'cookie' info related to this 278 buffer together with the 'cookie' info for this 279 MSDU_EXTENSION descriptor 280 281 <legal all> 282 283 buf3_ptr_39_32 284 285 Upper 8 bits of the fourth buffer pointer <legal all> 286 287 reserved_13a 288 289 <Legal 0> 290 291 buf3_len 292 293 Length of the fourth buffer <legal all> 294 295 buf4_ptr_31_0 296 297 Lower 32 bits of the fifth buffer pointer 298 299 300 301 NOTE: SW/FW manages the 'cookie' info related to this 302 buffer together with the 'cookie' info for this 303 MSDU_EXTENSION descriptor 304 305 <legal all> 306 307 buf4_ptr_39_32 308 309 Upper 8 bits of the fifth buffer pointer <legal all> 310 311 reserved_15a 312 313 <Legal 0> 314 315 buf4_len 316 317 Length of the fifth buffer <legal all> 318 319 buf5_ptr_31_0 320 321 Lower 32 bits of the sixth buffer pointer 322 323 324 325 NOTE: SW/FW manages the 'cookie' info related to this 326 buffer together with the 'cookie' info for this 327 MSDU_EXTENSION descriptor 328 329 <legal all> 330 331 buf5_ptr_39_32 332 333 Upper 8 bits of the sixth buffer pointer <legal all> 334 335 reserved_17a 336 337 <Legal 0> 338 339 buf5_len 340 341 Length of the sixth buffer <legal all> 342 */ 343 344 345 /* Description TX_MSDU_EXTENSION_0_TSO_ENABLE 346 347 Enable transmit segmentation offload <legal all> 348 */ 349 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 350 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 351 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 352 353 /* Description TX_MSDU_EXTENSION_0_RESERVED_0A 354 355 FW will set to 0, MAC will ignore. <legal 0> 356 */ 357 #define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 358 #define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 359 #define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e 360 361 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG 362 363 TCP flags 364 365 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 366 */ 367 #define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 368 #define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 369 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 370 371 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 372 373 TCP flag mask. Tcp_flag is inserted into the header 374 based on the mask, if tso is enabled 375 */ 376 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 377 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 378 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 379 380 /* Description TX_MSDU_EXTENSION_0_RESERVED_0B 381 382 FW will set to 0, MAC will ignore. <legal 0> 383 */ 384 #define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 385 #define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 386 #define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 387 388 /* Description TX_MSDU_EXTENSION_1_L2_LENGTH 389 390 L2 length for the msdu, if tso is enabled <legal all> 391 */ 392 #define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 393 #define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 394 #define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff 395 396 /* Description TX_MSDU_EXTENSION_1_IP_LENGTH 397 398 Ip length for the msdu, if tso is enabled <legal all> 399 */ 400 #define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 401 #define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 402 #define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 403 404 /* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER 405 406 Tcp_seq_number for the msdu, if tso is enabled <legal 407 all> 408 */ 409 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 410 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 411 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff 412 413 /* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION 414 415 Ip_identification for the msdu, if tso is enabled <legal 416 all> 417 */ 418 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c 419 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 420 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff 421 422 /* Description TX_MSDU_EXTENSION_3_UDP_LENGTH 423 424 TXDMA is copies this field into MSDU START TLV 425 */ 426 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c 427 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 428 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 429 430 /* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET 431 432 The calculated checksum from start offset to end offset 433 will be added to the checksum at the offset given by this 434 field<legal all> 435 */ 436 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 437 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 438 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff 439 440 /* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN 441 442 Partial Checksum Enable Bit. 443 444 <legal 0-1> 445 */ 446 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 447 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 448 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 449 450 /* Description TX_MSDU_EXTENSION_4_RESERVED_4A 451 452 <Legal 0> 453 */ 454 #define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 455 #define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 456 #define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 457 458 /* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET 459 460 L4 checksum calculations will start fromt this offset 461 462 <Legal all> 463 */ 464 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 465 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 466 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 467 468 /* Description TX_MSDU_EXTENSION_4_RESERVED_4B 469 470 <Legal 0> 471 */ 472 #define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 473 #define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 474 #define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 475 476 /* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET 477 478 L4 checksum calculations will end at this offset. 479 480 <Legal all> 481 */ 482 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 483 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 484 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff 485 486 /* Description TX_MSDU_EXTENSION_5_RESERVED_5A 487 488 <Legal 0> 489 */ 490 #define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 491 #define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 492 #define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 493 494 /* Description TX_MSDU_EXTENSION_5_WDS 495 496 If set the current packet is 4-address frame. Required 497 because an aggregate can include some frames with 3 address 498 format and other frames with 4 address format. Used by the 499 OLE during encapsulation. 500 501 Note: there is also global wds tx control in the 502 TX_PEER_ENTRY 503 504 <legal all> 505 */ 506 #define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 507 #define TX_MSDU_EXTENSION_5_WDS_LSB 16 508 #define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 509 510 /* Description TX_MSDU_EXTENSION_5_RESERVED_5B 511 512 <Legal 0> 513 */ 514 #define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 515 #define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 516 #define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 517 518 /* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 519 520 Lower 32 bits of the first buffer pointer 521 522 523 524 NOTE: SW/FW manages the 'cookie' info related to this 525 buffer together with the 'cookie' info for this 526 MSDU_EXTENSION descriptor 527 528 <legal all> 529 */ 530 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 531 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 532 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff 533 534 /* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 535 536 Upper 8 bits of the first buffer pointer <legal all> 537 */ 538 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c 539 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 540 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff 541 542 /* Description TX_MSDU_EXTENSION_7_RESERVED_7A 543 544 <Legal 0> 545 */ 546 #define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c 547 #define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 548 #define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 549 550 /* Description TX_MSDU_EXTENSION_7_BUF0_LEN 551 552 Length of the first buffer <legal all> 553 */ 554 #define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c 555 #define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 556 #define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 557 558 /* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 559 560 Lower 32 bits of the second buffer pointer 561 562 563 564 NOTE: SW/FW manages the 'cookie' info related to this 565 buffer together with the 'cookie' info for this 566 MSDU_EXTENSION descriptor 567 568 <legal all> 569 */ 570 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 571 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 572 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff 573 574 /* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 575 576 Upper 8 bits of the second buffer pointer <legal all> 577 */ 578 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 579 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 580 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff 581 582 /* Description TX_MSDU_EXTENSION_9_RESERVED_9A 583 584 <Legal 0> 585 */ 586 #define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 587 #define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 588 #define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 589 590 /* Description TX_MSDU_EXTENSION_9_BUF1_LEN 591 592 Length of the second buffer <legal all> 593 */ 594 #define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 595 #define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 596 #define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 597 598 /* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 599 600 Lower 32 bits of the third buffer pointer 601 602 NOTE: SW/FW manages the 'cookie' info related to this 603 buffer together with the 'cookie' info for this 604 MSDU_EXTENSION descriptor 605 606 <legal all> 607 */ 608 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 609 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 610 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff 611 612 /* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 613 614 Upper 8 bits of the third buffer pointer <legal all> 615 */ 616 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c 617 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 618 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff 619 620 /* Description TX_MSDU_EXTENSION_11_RESERVED_11A 621 622 <Legal 0> 623 */ 624 #define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c 625 #define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 626 #define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 627 628 /* Description TX_MSDU_EXTENSION_11_BUF2_LEN 629 630 Length of the third buffer <legal all> 631 */ 632 #define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c 633 #define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 634 #define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 635 636 /* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 637 638 Lower 32 bits of the fourth buffer pointer 639 640 641 642 NOTE: SW/FW manages the 'cookie' info related to this 643 buffer together with the 'cookie' info for this 644 MSDU_EXTENSION descriptor 645 646 <legal all> 647 */ 648 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 649 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 650 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff 651 652 /* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 653 654 Upper 8 bits of the fourth buffer pointer <legal all> 655 */ 656 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 657 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 658 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff 659 660 /* Description TX_MSDU_EXTENSION_13_RESERVED_13A 661 662 <Legal 0> 663 */ 664 #define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 665 #define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 666 #define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 667 668 /* Description TX_MSDU_EXTENSION_13_BUF3_LEN 669 670 Length of the fourth buffer <legal all> 671 */ 672 #define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 673 #define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 674 #define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 675 676 /* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 677 678 Lower 32 bits of the fifth buffer pointer 679 680 681 682 NOTE: SW/FW manages the 'cookie' info related to this 683 buffer together with the 'cookie' info for this 684 MSDU_EXTENSION descriptor 685 686 <legal all> 687 */ 688 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 689 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 690 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff 691 692 /* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 693 694 Upper 8 bits of the fifth buffer pointer <legal all> 695 */ 696 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c 697 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 698 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff 699 700 /* Description TX_MSDU_EXTENSION_15_RESERVED_15A 701 702 <Legal 0> 703 */ 704 #define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c 705 #define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 706 #define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 707 708 /* Description TX_MSDU_EXTENSION_15_BUF4_LEN 709 710 Length of the fifth buffer <legal all> 711 */ 712 #define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c 713 #define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 714 #define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 715 716 /* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 717 718 Lower 32 bits of the sixth buffer pointer 719 720 721 722 NOTE: SW/FW manages the 'cookie' info related to this 723 buffer together with the 'cookie' info for this 724 MSDU_EXTENSION descriptor 725 726 <legal all> 727 */ 728 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 729 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 730 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff 731 732 /* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 733 734 Upper 8 bits of the sixth buffer pointer <legal all> 735 */ 736 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 737 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 738 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff 739 740 /* Description TX_MSDU_EXTENSION_17_RESERVED_17A 741 742 <Legal 0> 743 */ 744 #define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 745 #define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 746 #define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 747 748 /* Description TX_MSDU_EXTENSION_17_BUF5_LEN 749 750 Length of the sixth buffer <legal all> 751 */ 752 #define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 753 #define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 754 #define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 755 756 757 #endif // _TX_MSDU_EXTENSION_H_ 758