1  /*
2   * Copyright (c) 2019 The Linux Foundation. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for
5   * any purpose with or without fee is hereby granted, provided that the
6   * above copyright notice and this permission notice appear in all
7   * copies.
8   *
9   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10   * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11   * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12   * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13   * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14   * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15   * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16   * PERFORMANCE OF THIS SOFTWARE.
17   */
18  
19  //
20  // DO NOT EDIT!  This file is automatically generated
21  //               These definitions are tied to a particular hardware layout
22  
23  
24  #ifndef _RX_MSDU_DETAILS_H_
25  #define _RX_MSDU_DETAILS_H_
26  #if !defined(__ASSEMBLER__)
27  #endif
28  
29  #include "buffer_addr_info.h"
30  #include "rx_msdu_desc_info.h"
31  
32  // ################ START SUMMARY #################
33  //
34  //	Dword	Fields
35  //	0-1	struct buffer_addr_info buffer_addr_info_details;
36  //	2-3	struct rx_msdu_desc_info rx_msdu_desc_info_details;
37  //
38  // ################ END SUMMARY #################
39  
40  #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
41  
42  struct rx_msdu_details {
43      struct            buffer_addr_info                       buffer_addr_info_details;
44      struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
45  };
46  
47  /*
48  
49  struct buffer_addr_info buffer_addr_info_details
50  
51  			Consumer: REO/SW
52  
53  			Producer: RXDMA
54  
55  
56  
57  			Details of the physical address of the buffer containing
58  			an MSDU (or entire MPDU)
59  
60  struct rx_msdu_desc_info rx_msdu_desc_info_details
61  
62  			Consumer: REO/SW
63  
64  			Producer: RXDMA
65  
66  
67  
68  			General information related to the MSDU that should be
69  			passed on from RXDMA all the way to to the REO destination
70  			ring.
71  */
72  
73  
74   /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
75  
76  
77  /* Description		RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
78  
79  			Address (lower 32 bits) of the MSDU buffer OR
80  			MSDU_EXTENSION descriptor OR Link Descriptor
81  
82  
83  
84  			In case of 'NULL' pointer, this field is set to 0
85  
86  			<legal all>
87  */
88  #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
89  #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
90  #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
91  
92  /* Description		RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
93  
94  			Address (upper 8 bits) of the MSDU buffer OR
95  			MSDU_EXTENSION descriptor OR Link Descriptor
96  
97  
98  
99  			In case of 'NULL' pointer, this field is set to 0
100  
101  			<legal all>
102  */
103  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
104  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
105  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
106  
107  /* Description		RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
108  
109  			Consumer: WBM
110  
111  			Producer: SW/FW
112  
113  
114  
115  			In case of 'NULL' pointer, this field is set to 0
116  
117  
118  
119  			Indicates to which buffer manager the buffer OR
120  			MSDU_EXTENSION descriptor OR link descriptor that is being
121  			pointed to shall be returned after the frame has been
122  			processed. It is used by WBM for routing purposes.
123  
124  
125  
126  			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
127  			to the WMB buffer idle list
128  
129  			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
130  			returned to the WMB idle link descriptor idle list
131  
132  			<enum 2 FW_BM> This buffer shall be returned to the FW
133  
134  			<enum 3 SW0_BM> This buffer shall be returned to the SW,
135  			ring 0
136  
137  			<enum 4 SW1_BM> This buffer shall be returned to the SW,
138  			ring 1
139  
140  			<enum 5 SW2_BM> This buffer shall be returned to the SW,
141  			ring 2
142  
143  			<enum 6 SW3_BM> This buffer shall be returned to the SW,
144  			ring 3
145  
146  			<enum 7 SW4_BM> This buffer shall be returned to the SW,
147  			ring 4
148  
149  
150  
151  			<legal all>
152  */
153  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
154  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
155  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
156  
157  /* Description		RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
158  
159  			Cookie field exclusively used by SW.
160  
161  
162  
163  			In case of 'NULL' pointer, this field is set to 0
164  
165  
166  
167  			HW ignores the contents, accept that it passes the
168  			programmed value on to other descriptors together with the
169  			physical address
170  
171  
172  
173  			Field can be used by SW to for example associate the
174  			buffers physical address with the virtual address
175  
176  			The bit definitions as used by SW are within SW HLD
177  			specification
178  
179  
180  
181  			NOTE:
182  
183  			The three most significant bits can have a special
184  			meaning in case this struct is embedded in a TX_MPDU_DETAILS
185  			STRUCT, and field transmit_bw_restriction is set
186  
187  
188  
189  			In case of NON punctured transmission:
190  
191  			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
192  
193  			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
194  
195  			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
196  
197  			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
198  
199  
200  
201  			In case of punctured transmission:
202  
203  			Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
204  
205  			Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
206  
207  			Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
208  
209  			Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
210  
211  			Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
212  
213  			Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
214  
215  			Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
216  
217  			Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
218  
219  
220  
221  			Note: a punctured transmission is indicated by the
222  			presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
223  			TLV
224  
225  
226  
227  			<legal all>
228  */
229  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
230  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
231  #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
232  
233   /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
234  
235  
236  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
237  
238  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
239  			over multiple buffers, this field will be valid in the Last
240  			buffer used by the MSDU
241  
242  
243  
244  			<enum 0 Not_first_msdu> This is not the first MSDU in
245  			the MPDU.
246  
247  			<enum 1 first_msdu> This MSDU is the first one in the
248  			MPDU.
249  
250  
251  
252  			<legal all>
253  */
254  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
255  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
256  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
257  
258  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
259  
260  			Consumer: WBM/REO/SW/FW
261  
262  			Producer: RXDMA
263  
264  
265  
266  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
267  			over multiple buffers, this field will be valid in the Last
268  			buffer used by the MSDU
269  
270  
271  
272  			<enum 0 Not_last_msdu> There are more MSDUs linked to
273  			this MSDU that belongs to this MPDU
274  
275  			<enum 1 Last_msdu> this MSDU is the last one in the
276  			MPDU. This setting is only allowed in combination with
277  			'Msdu_continuation' set to 0. This implies that when an msdu
278  			is spread out over multiple buffers and thus
279  			msdu_continuation is set, only for the very last buffer of
280  			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
281  
282  
283  
284  			When both first_msdu_in_mpdu_flag and
285  			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
286  			belongs to only contains a single MSDU.
287  
288  
289  
290  
291  
292  			<legal all>
293  */
294  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
295  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
296  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
297  
298  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
299  
300  			When set, this MSDU buffer was not able to hold the
301  			entire MSDU. The next buffer will therefor contain
302  			additional information related to this MSDU.
303  
304  
305  
306  			<legal all>
307  */
308  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
309  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
310  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
311  
312  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
313  
314  			Parsed from RX_MSDU_START TLV . In the case MSDU spans
315  			over multiple buffers, this field will be valid in the First
316  			buffer used by MSDU.
317  
318  
319  
320  			Full MSDU length in bytes after decapsulation.
321  
322  
323  
324  			This field is still valid for MPDU frames without
325  			A-MSDU.  It still represents MSDU length after decapsulation
326  
327  
328  
329  			Or in case of RAW MPDUs, it indicates the length of the
330  			entire MPDU (without FCS field)
331  
332  			<legal all>
333  */
334  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
335  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB  3
336  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
337  
338  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
339  
340  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
341  			over multiple buffers, this field will be valid in the Last
342  			buffer used by the MSDU
343  
344  
345  
346  			The ID of the REO exit ring where the MSDU frame shall
347  			push after (MPDU level) reordering has finished.
348  
349  
350  
351  			<enum 0 reo_destination_tcl> Reo will push the frame
352  			into the REO2TCL ring
353  
354  			<enum 1 reo_destination_sw1> Reo will push the frame
355  			into the REO2SW1 ring
356  
357  			<enum 2 reo_destination_sw2> Reo will push the frame
358  			into the REO2SW2 ring
359  
360  			<enum 3 reo_destination_sw3> Reo will push the frame
361  			into the REO2SW3 ring
362  
363  			<enum 4 reo_destination_sw4> Reo will push the frame
364  			into the REO2SW4 ring
365  
366  			<enum 5 reo_destination_release> Reo will push the frame
367  			into the REO_release ring
368  
369  			<enum 6 reo_destination_fw> Reo will push the frame into
370  			the REO2FW ring
371  
372  			<enum 7 reo_destination_sw5> Reo will push the frame
373  			into the REO2SW5 ring
374  
375  			<enum 8 reo_destination_sw6> Reo will push the frame
376  			into the REO2SW6 ring
377  
378  			 <enum 9 reo_destination_9> REO remaps this <enum 10
379  			reo_destination_10> REO remaps this
380  
381  			<enum 11 reo_destination_11> REO remaps this
382  
383  			<enum 12 reo_destination_12> REO remaps this <enum 13
384  			reo_destination_13> REO remaps this
385  
386  			<enum 14 reo_destination_14> REO remaps this
387  
388  			<enum 15 reo_destination_15> REO remaps this
389  
390  			<enum 16 reo_destination_16> REO remaps this
391  
392  			<enum 17 reo_destination_17> REO remaps this
393  
394  			<enum 18 reo_destination_18> REO remaps this
395  
396  			<enum 19 reo_destination_19> REO remaps this
397  
398  			<enum 20 reo_destination_20> REO remaps this
399  
400  			<enum 21 reo_destination_21> REO remaps this
401  
402  			<enum 22 reo_destination_22> REO remaps this
403  
404  			<enum 23 reo_destination_23> REO remaps this
405  
406  			<enum 24 reo_destination_24> REO remaps this
407  
408  			<enum 25 reo_destination_25> REO remaps this
409  
410  			<enum 26 reo_destination_26> REO remaps this
411  
412  			<enum 27 reo_destination_27> REO remaps this
413  
414  			<enum 28 reo_destination_28> REO remaps this
415  
416  			<enum 29 reo_destination_29> REO remaps this
417  
418  			<enum 30 reo_destination_30> REO remaps this
419  
420  			<enum 31 reo_destination_31> REO remaps this
421  
422  
423  
424  			<legal all>
425  */
426  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008
427  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
428  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
429  
430  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
431  
432  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
433  			over multiple buffers, this field will be valid in the Last
434  			buffer used by the MSDU
435  
436  
437  
438  			When set, REO shall drop this MSDU and not forward it to
439  			any other ring...
440  
441  			<legal all>
442  */
443  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
444  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB    22
445  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK   0x00400000
446  
447  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
448  
449  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
450  			over multiple buffers, this field will be valid in the Last
451  			buffer used by the MSDU
452  
453  
454  
455  			Indicates that OLE found a valid SA entry for this MSDU
456  
457  			<legal all>
458  */
459  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
460  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB  23
461  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
462  
463  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
464  
465  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
466  			over multiple buffers, this field will be valid in the Last
467  			buffer used by the MSDU
468  
469  
470  
471  			Indicates an unsuccessful MAC source address search due
472  			to the expiring of the search timer for this MSDU
473  
474  			<legal all>
475  */
476  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
477  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
478  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
479  
480  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
481  
482  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
483  			over multiple buffers, this field will be valid in the Last
484  			buffer used by the MSDU
485  
486  
487  
488  			Indicates that OLE found a valid DA entry for this MSDU
489  
490  			<legal all>
491  */
492  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
493  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB  25
494  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
495  
496  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
497  
498  			Field Only valid if da_is_valid is set
499  
500  
501  
502  			Indicates the DA address was a Multicast of Broadcast
503  			address for this MSDU
504  
505  			<legal all>
506  */
507  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
508  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB   26
509  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK  0x04000000
510  
511  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
512  
513  			Parsed from RX_MSDU_END TLV . In the case MSDU spans
514  			over multiple buffers, this field will be valid in the Last
515  			buffer used by the MSDU
516  
517  
518  
519  			Indicates an unsuccessful MAC destination address search
520  			due to the expiring of the search timer for this MSDU
521  
522  			<legal all>
523  */
524  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
525  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
526  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
527  
528  /* Description		RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A
529  
530  			<legal 0>
531  */
532  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
533  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB  28
534  #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000
535  
536  /* Description		RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A
537  
538  			<legal 0>
539  */
540  #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000c
541  #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB  0
542  #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff
543  
544  
545  #endif // _RX_MSDU_DETAILS_H_
546