1 /* 2 * Copyright (c) 2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_MPDU_START_H_ 25 #define _RX_MPDU_START_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "rx_mpdu_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-22 struct rx_mpdu_info rx_mpdu_info_details; 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_RX_MPDU_START 23 39 40 struct rx_mpdu_start { 41 struct rx_mpdu_info rx_mpdu_info_details; 42 }; 43 44 /* 45 46 struct rx_mpdu_info rx_mpdu_info_details 47 48 Structure containing all the MPDU header details that 49 might be needed for other modules further down the received 50 path 51 */ 52 53 54 /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */ 55 56 57 /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ 58 59 60 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION 61 62 The ID of the REO exit ring where the MSDU frame shall 63 push after (MPDU level) reordering has finished. 64 65 66 67 <enum 0 reo_destination_tcl> Reo will push the frame 68 into the REO2TCL ring 69 70 <enum 1 reo_destination_sw1> Reo will push the frame 71 into the REO2SW1 ring 72 73 <enum 2 reo_destination_sw2> Reo will push the frame 74 into the REO2SW2 ring 75 76 <enum 3 reo_destination_sw3> Reo will push the frame 77 into the REO2SW3 ring 78 79 <enum 4 reo_destination_sw4> Reo will push the frame 80 into the REO2SW4 ring 81 82 <enum 5 reo_destination_release> Reo will push the frame 83 into the REO_release ring 84 85 <enum 6 reo_destination_fw> Reo will push the frame into 86 the REO2FW ring 87 88 <enum 7 reo_destination_sw5> Reo will push the frame 89 into the REO2SW5 ring 90 91 <enum 8 reo_destination_sw6> Reo will push the frame 92 into the REO2SW6 ring 93 94 <enum 9 reo_destination_9> REO remaps this <enum 10 95 reo_destination_10> REO remaps this 96 97 <enum 11 reo_destination_11> REO remaps this 98 99 <enum 12 reo_destination_12> REO remaps this <enum 13 100 reo_destination_13> REO remaps this 101 102 <enum 14 reo_destination_14> REO remaps this 103 104 <enum 15 reo_destination_15> REO remaps this 105 106 <enum 16 reo_destination_16> REO remaps this 107 108 <enum 17 reo_destination_17> REO remaps this 109 110 <enum 18 reo_destination_18> REO remaps this 111 112 <enum 19 reo_destination_19> REO remaps this 113 114 <enum 20 reo_destination_20> REO remaps this 115 116 <enum 21 reo_destination_21> REO remaps this 117 118 <enum 22 reo_destination_22> REO remaps this 119 120 <enum 23 reo_destination_23> REO remaps this 121 122 <enum 24 reo_destination_24> REO remaps this 123 124 <enum 25 reo_destination_25> REO remaps this 125 126 <enum 26 reo_destination_26> REO remaps this 127 128 <enum 27 reo_destination_27> REO remaps this 129 130 <enum 28 reo_destination_28> REO remaps this 131 132 <enum 29 reo_destination_29> REO remaps this 133 134 <enum 30 reo_destination_30> REO remaps this 135 136 <enum 31 reo_destination_31> REO remaps this 137 138 139 140 <legal all> 141 */ 142 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 143 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 144 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 145 146 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB 147 148 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 149 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 150 hash[3:0]} using the chosen Toeplitz hash from Common Parser 151 if flow search fails. 152 153 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 154 's not 2'b00, Rx OLE uses a REO desination indication of 155 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash 156 from Common Parser if flow search fails. 157 158 This LMAC/peer-based routing is not supported in 159 Hastings80 and HastingsPrime. 160 161 <legal 0> 162 */ 163 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 164 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 165 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 166 167 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY 168 169 Indication to Rx OLE to enable REO destination routing 170 based on the chosen Toeplitz hash from Common Parser, in 171 case flow search fails 172 173 <legal all> 174 */ 175 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 176 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 177 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 178 179 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA 180 181 Filter pass Unicast data frame (matching 182 rxpcu_filter_pass and sw_frame_group_Unicast_data) routing 183 selection 184 185 186 187 1'b0: source and destination rings are selected from the 188 RxOLE register settings for the packet type 189 190 191 192 1'b1: source ring and destination ring is selected from 193 the rxdma0_source_ring_selection and 194 rxdma0_destination_ring_selection fields in this STRUCT 195 196 <legal all> 197 */ 198 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 199 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 200 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 201 202 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA 203 204 Filter pass Multicast data frame (matching 205 rxpcu_filter_pass and sw_frame_group_Multicast_data) routing 206 selection 207 208 209 210 1'b0: source and destination rings are selected from the 211 RxOLE register settings for the packet type 212 213 214 215 1'b1: source ring and destination ring is selected from 216 the rxdma0_source_ring_selection and 217 rxdma0_destination_ring_selection fields in this STRUCT 218 219 <legal all> 220 */ 221 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 222 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 223 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 224 225 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 226 227 Filter pass BAR frame (matching rxpcu_filter_pass and 228 sw_frame_group_ctrl_1000) routing selection 229 230 231 232 1'b0: source and destination rings are selected from the 233 RxOLE register settings for the packet type 234 235 236 237 1'b1: source ring and destination ring is selected from 238 the rxdma0_source_ring_selection and 239 rxdma0_destination_ring_selection fields in this STRUCT 240 241 <legal all> 242 */ 243 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 244 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 245 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 246 247 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION 248 249 Field only valid when for the received frame type the 250 corresponding pkt_selection_fp_... bit is set 251 252 253 254 <enum 0 wbm2rxdma_buf_source_ring> The data buffer for 255 256 <enum 1 fw2rxdma_buf_source_ring> The data buffer for 257 this frame shall be sourced by fw2rxdma buffer source ring. 258 259 <enum 2 sw2rxdma_buf_source_ring> The data buffer for 260 this frame shall be sourced by sw2rxdma buffer source ring. 261 262 <enum 3 no_buffer_ring> The frame shall not be written 263 to any data buffer. 264 265 266 267 <legal all> 268 */ 269 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 270 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 271 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 272 273 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION 274 275 Field only valid when for the received frame type the 276 corresponding pkt_selection_fp_... bit is set 277 278 279 280 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 281 to the Release ring. Effectively this means the frame needs 282 to be dropped. 283 284 <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to 285 the FW ring. 286 287 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to 288 the SW ring. 289 290 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 291 the REO entrance ring. 292 293 294 295 <legal all> 296 */ 297 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 298 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 299 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 300 301 /* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B 302 303 <legal 0> 304 */ 305 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 306 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 307 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 308 309 /* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0 310 311 In case of ndp or phy_err or AST_based_lookup_valid == 312 0, this field will be set to 0 313 314 315 316 Address (lower 32 bits) of the REO queue descriptor. 317 318 319 320 If no Peer entry lookup happened for this frame, the 321 value wil be set to 0, and the frame shall never be pushed 322 to REO entrance ring. 323 324 <legal all> 325 */ 326 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 327 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 328 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 329 330 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32 331 332 In case of ndp or phy_err or AST_based_lookup_valid == 333 0, this field will be set to 0 334 335 336 337 Address (upper 8 bits) of the REO queue descriptor. 338 339 340 341 If no Peer entry lookup happened for this frame, the 342 value wil be set to 0, and the frame shall never be pushed 343 to REO entrance ring. 344 345 <legal all> 346 */ 347 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 348 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 349 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 350 351 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER 352 353 In case of ndp or phy_err or AST_based_lookup_valid == 354 0, this field will be set to 0 355 356 357 358 Indicates the MPDU queue ID to which this MPDU link 359 descriptor belongs 360 361 Used for tracking and debugging 362 363 <legal all> 364 */ 365 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 366 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 367 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 368 369 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING 370 371 Indicates that a delimiter FCS error was found in 372 between the Previous MPDU and this MPDU. 373 374 375 376 Note that this is just a warning, and does not mean that 377 this MPDU is corrupted in any way. If it is, there will be 378 other errors indicated such as FCS or decrypt errors 379 380 381 382 In case of ndp or phy_err, this field will indicate at 383 least one of delimiters located after the last MPDU in the 384 previous PPDU has been corrupted. 385 */ 386 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 387 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 388 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 389 390 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR 391 392 Indicates that the first delimiter had a FCS failure. 393 Only valid when first_mpdu and first_msdu are set. 394 395 396 397 */ 398 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 399 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 400 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 401 402 /* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_11 403 404 <legal 0> 405 */ 406 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_11_OFFSET 0x00000008 407 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_11_LSB 26 408 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_11_MASK 0xfc000000 409 410 /* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0 411 412 413 414 415 416 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 417 is valid. 418 419 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 420 WEPSeed[1], pn1}. Only pn[47:0] is valid. 421 422 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 423 pn1, pn0}. Only pn[47:0] is valid. 424 425 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 426 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 427 pn0}. pn[127:0] are valid. 428 429 430 431 */ 432 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c 433 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 434 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff 435 436 /* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32 437 438 439 440 441 Bits [63:32] of the PN number. See description for 442 pn_31_0. 443 444 445 446 */ 447 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 448 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 449 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff 450 451 /* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64 452 453 454 455 456 Bits [95:64] of the PN number. See description for 457 pn_31_0. 458 459 460 461 */ 462 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 463 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 464 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff 465 466 /* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96 467 468 469 470 471 Bits [127:96] of the PN number. See description for 472 pn_31_0. 473 474 475 476 */ 477 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 478 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 479 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff 480 481 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN 482 483 Field only valid when AST_based_lookup_valid == 1. 484 485 486 487 488 489 In case of ndp or phy_err or AST_based_lookup_valid == 490 0, this field will be set to 0 491 492 493 494 If set to one use EPD instead of LPD 495 496 497 498 499 <legal all> 500 */ 501 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c 502 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 503 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 504 505 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED 506 507 In case of ndp or phy_err or AST_based_lookup_valid == 508 0, this field will be set to 0 509 510 511 512 When set, all frames (data only ?) shall be encrypted. 513 If not, RX CRYPTO shall set an error flag. 514 515 <legal all> 516 */ 517 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 518 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 519 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 520 521 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE 522 523 In case of ndp or phy_err or AST_based_lookup_valid == 524 0, this field will be set to 0 525 526 527 528 Indicates type of decrypt cipher used (as defined in the 529 peer entry) 530 531 532 533 <enum 0 wep_40> WEP 40-bit 534 535 <enum 1 wep_104> WEP 104-bit 536 537 <enum 2 tkip_no_mic> TKIP without MIC 538 539 <enum 3 wep_128> WEP 128-bit 540 541 <enum 4 tkip_with_mic> TKIP with MIC 542 543 <enum 5 wapi> WAPI 544 545 <enum 6 aes_ccmp_128> AES CCMP 128 546 547 <enum 7 no_cipher> No crypto 548 549 <enum 8 aes_ccmp_256> AES CCMP 256 550 551 <enum 9 aes_gcmp_128> AES CCMP 128 552 553 <enum 10 aes_gcmp_256> AES CCMP 256 554 555 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 556 557 558 559 <enum 12 wep_varied_width> WEP encryption. As for WEP 560 per keyid the key bit width can vary, the key bit width for 561 this MPDU will be indicated in field 562 wep_key_width_for_variable key 563 564 <legal 0-12> 565 */ 566 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c 567 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 568 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c 569 570 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 571 572 Field only valid when key_type is set to 573 wep_varied_width. 574 575 576 577 This field indicates the size of the wep key for this 578 MPDU. 579 580 581 582 <enum 0 wep_varied_width_40> WEP 40-bit 583 584 <enum 1 wep_varied_width_104> WEP 104-bit 585 586 <enum 2 wep_varied_width_128> WEP 128-bit 587 588 589 590 <legal 0-2> 591 */ 592 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 593 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 594 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 595 596 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA 597 598 In case of ndp or phy_err or AST_based_lookup_valid == 599 0, this field will be set to 0 600 601 602 603 When set, this is a Mesh (11s) STA. 604 605 606 607 The interpretation of the A-MSDU 'Length' field in the 608 MPDU (if any) is decided by the e-numerations below. 609 610 611 612 <enum 0 MESH_DISABLE> 613 614 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and 615 includes the length of Mesh Control. 616 617 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and 618 excludes the length of Mesh Control. 619 620 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian 621 and excludes the length of Mesh Control. This is 622 802.11s-compliant. 623 624 <legal all> 625 */ 626 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000001c 627 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8 628 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000300 629 630 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT 631 632 In case of ndp or phy_err or AST_based_lookup_valid == 633 0, this field will be set to 0 634 635 636 637 When set, the BSSID of the incoming frame matched one of 638 the 8 BSSID register values 639 640 641 642 <legal all> 643 */ 644 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c 645 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 646 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 647 648 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER 649 650 Field only valid when bssid_hit is set. 651 652 653 654 This number indicates which one out of the 8 BSSID 655 register values matched the incoming frame 656 657 <legal all> 658 */ 659 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c 660 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 661 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 662 663 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID 664 665 Field only valid when mpdu_qos_control_valid is set 666 667 668 669 The TID field in the QoS control field 670 671 <legal all> 672 */ 673 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c 674 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 675 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 676 677 /* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_3A 678 679 <legal 0> 680 */ 681 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000001c 682 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_3A_LSB 19 683 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_3A_MASK 0xfff80000 684 685 /* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA 686 687 In case of ndp or phy_err or AST_based_lookup_valid == 688 0, this field will be set to 0 689 690 691 692 Meta data that SW has programmed in the Peer table entry 693 of the transmitting STA. 694 695 <legal all> 696 */ 697 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 698 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 699 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 700 701 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY 702 703 Field indicates what the reason was that this MPDU frame 704 was allowed to come into the receive path by RXPCU 705 706 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 707 frame filter programming of rxpcu 708 709 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 710 regular frame filter and would have been dropped, were it 711 not for the frame fitting into the 'monitor_client' 712 category. 713 714 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 715 regular frame filter and also did not pass the 716 rxpcu_monitor_client filter. It would have been dropped 717 accept that it did pass the 'monitor_other' category. 718 719 720 721 Note: for ndp frame, if it was expected because the 722 preceding NDPA was filter_pass, the setting 723 rxpcu_filter_pass will be used. This setting will also be 724 used for every ndp frame in case Promiscuous mode is 725 enabled. 726 727 728 729 In case promiscuous is not enabled, and an NDP is not 730 preceded by a NPDA filter pass frame, the only other setting 731 that could appear here for the NDP is rxpcu_monitor_other. 732 733 (rxpcu has a configuration bit specifically for this 734 scenario) 735 736 737 738 Note: for 739 740 <legal 0-2> 741 */ 742 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 743 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 744 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 745 746 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID 747 748 SW processes frames based on certain classifications. 749 This field indicates to what sw classification this MPDU is 750 mapped. 751 752 The classification is given in priority order 753 754 755 756 <enum 0 sw_frame_group_NDP_frame> Note: The 757 corresponding Rxpcu_Mpdu_filter_in_category can be 758 rxpcu_filter_pass or rxpcu_monitor_other 759 760 761 762 <enum 1 sw_frame_group_Multicast_data> 763 764 <enum 2 sw_frame_group_Unicast_data> 765 766 <enum 3 sw_frame_group_Null_data > This includes mpdus 767 of type Data Null as well as QoS Data Null 768 769 770 771 <enum 4 sw_frame_group_mgmt_0000 > 772 773 <enum 5 sw_frame_group_mgmt_0001 > 774 775 <enum 6 sw_frame_group_mgmt_0010 > 776 777 <enum 7 sw_frame_group_mgmt_0011 > 778 779 <enum 8 sw_frame_group_mgmt_0100 > 780 781 <enum 9 sw_frame_group_mgmt_0101 > 782 783 <enum 10 sw_frame_group_mgmt_0110 > 784 785 <enum 11 sw_frame_group_mgmt_0111 > 786 787 <enum 12 sw_frame_group_mgmt_1000 > 788 789 <enum 13 sw_frame_group_mgmt_1001 > 790 791 <enum 14 sw_frame_group_mgmt_1010 > 792 793 <enum 15 sw_frame_group_mgmt_1011 > 794 795 <enum 16 sw_frame_group_mgmt_1100 > 796 797 <enum 17 sw_frame_group_mgmt_1101 > 798 799 <enum 18 sw_frame_group_mgmt_1110 > 800 801 <enum 19 sw_frame_group_mgmt_1111 > 802 803 804 805 <enum 20 sw_frame_group_ctrl_0000 > 806 807 <enum 21 sw_frame_group_ctrl_0001 > 808 809 <enum 22 sw_frame_group_ctrl_0010 > 810 811 <enum 23 sw_frame_group_ctrl_0011 > 812 813 <enum 24 sw_frame_group_ctrl_0100 > 814 815 <enum 25 sw_frame_group_ctrl_0101 > 816 817 <enum 26 sw_frame_group_ctrl_0110 > 818 819 <enum 27 sw_frame_group_ctrl_0111 > 820 821 <enum 28 sw_frame_group_ctrl_1000 > 822 823 <enum 29 sw_frame_group_ctrl_1001 > 824 825 <enum 30 sw_frame_group_ctrl_1010 > 826 827 <enum 31 sw_frame_group_ctrl_1011 > 828 829 <enum 32 sw_frame_group_ctrl_1100 > 830 831 <enum 33 sw_frame_group_ctrl_1101 > 832 833 <enum 34 sw_frame_group_ctrl_1110 > 834 835 <enum 35 sw_frame_group_ctrl_1111 > 836 837 838 839 <enum 36 sw_frame_group_unsupported> This covers type 3 840 and protocol version != 0 841 842 Note: The corresponding Rxpcu_Mpdu_filter_in_category 843 can only be rxpcu_monitor_other 844 845 846 847 848 Note: The corresponding Rxpcu_Mpdu_filter_in_category 849 can be rxpcu_filter_pass 850 851 852 853 <legal 0-37> 854 */ 855 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 856 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 857 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc 858 859 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME 860 861 When set, the received frame was an NDP frame, and thus 862 there will be no MPDU data. 863 864 <legal all> 865 */ 866 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 867 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 868 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 869 870 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR 871 872 When set, a PHY error was received before MAC received 873 any data, and thus there will be no MPDU data. 874 875 <legal all> 876 */ 877 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 878 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 879 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 880 881 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER 882 883 When set, a PHY error was received before MAC received 884 the complete MPDU header which was needed for proper 885 decoding 886 887 <legal all> 888 */ 889 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 890 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 891 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 892 893 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR 894 895 Set when RXPCU detected a version error in the Frame 896 control field 897 898 <legal all> 899 */ 900 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 901 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 902 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 903 904 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID 905 906 When set, AST based lookup for this frame has found a 907 valid result. 908 909 910 911 Note that for NDP frame this will never be set 912 913 <legal all> 914 */ 915 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 916 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 917 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 918 919 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_0A 920 921 <legal 0> 922 */ 923 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000024 924 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_0A_LSB 14 925 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_0A_MASK 0x0000c000 926 927 /* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID 928 929 A ppdu counter value that PHY increments for every PPDU 930 received. The counter value wraps around 931 932 <legal all> 933 */ 934 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 935 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 936 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 937 938 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX 939 940 This field indicates the index of the AST entry 941 corresponding to this MPDU. It is provided by the GSE module 942 instantiated in RXPCU. 943 944 A value of 0xFFFF indicates an invalid AST index, 945 meaning that No AST entry was found or NO AST search was 946 performed 947 948 949 950 In case of ndp or phy_err, this field will be set to 951 0xFFFF 952 953 <legal all> 954 */ 955 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 956 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 957 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff 958 959 /* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID 960 961 In case of ndp or phy_err or AST_based_lookup_valid == 962 0, this field will be set to 0 963 964 965 966 This field indicates a unique peer identifier. It is set 967 equal to field 'sw_peer_id' from the AST entry 968 969 970 971 <legal all> 972 */ 973 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 974 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 975 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 976 977 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID 978 979 When set, the field Mpdu_Frame_control_field has valid 980 information 981 982 983 984 985 <legal all> 986 */ 987 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 988 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 989 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 990 991 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID 992 993 When set, the field Mpdu_duration_field has valid 994 information 995 996 997 998 999 <legal all> 1000 */ 1001 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c 1002 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 1003 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 1004 1005 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID 1006 1007 When set, the fields mac_addr_ad1_..... have valid 1008 information 1009 1010 1011 1012 1013 <legal all> 1014 */ 1015 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 1016 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 1017 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 1018 1019 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID 1020 1021 When set, the fields mac_addr_ad2_..... have valid 1022 information 1023 1024 1025 1026 1027 1028 1029 1030 <legal all> 1031 */ 1032 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 1033 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 1034 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 1035 1036 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID 1037 1038 When set, the fields mac_addr_ad3_..... have valid 1039 information 1040 1041 1042 1043 1044 1045 1046 1047 <legal all> 1048 */ 1049 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 1050 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 1051 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 1052 1053 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID 1054 1055 When set, the fields mac_addr_ad4_..... have valid 1056 information 1057 1058 1059 1060 1061 1062 1063 1064 <legal all> 1065 */ 1066 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 1067 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 1068 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 1069 1070 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID 1071 1072 When set, the fields mpdu_sequence_control_field and 1073 mpdu_sequence_number have valid information as well as field 1074 1075 1076 1077 For MPDUs without a sequence control field, this field 1078 will not be set. 1079 1080 1081 1082 1083 <legal all> 1084 */ 1085 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 1086 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1087 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1088 1089 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID 1090 1091 When set, the field mpdu_qos_control_field has valid 1092 information 1093 1094 1095 1096 For MPDUs without a QoS control field, this field will 1097 not be set. 1098 1099 1100 1101 1102 <legal all> 1103 */ 1104 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 1105 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 1106 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1107 1108 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID 1109 1110 When set, the field mpdu_HT_control_field has valid 1111 information 1112 1113 1114 1115 For MPDUs without a HT control field, this field will 1116 not be set. 1117 1118 1119 1120 1121 <legal all> 1122 */ 1123 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 1124 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 1125 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1126 1127 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID 1128 1129 When set, the encryption related info fields, like IV 1130 and PN are valid 1131 1132 1133 1134 For MPDUs that are not encrypted, this will not be set. 1135 1136 1137 1138 1139 <legal all> 1140 */ 1141 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 1142 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1143 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1144 1145 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER 1146 1147 Field only valid when Mpdu_sequence_control_valid is set 1148 AND Fragment_flag is set 1149 1150 1151 1152 The fragment number from the 802.11 header 1153 1154 1155 1156 <legal all> 1157 */ 1158 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 1159 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 1160 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1161 1162 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG 1163 1164 The More Fragment bit setting from the MPDU header of 1165 the received frame 1166 1167 1168 1169 <legal all> 1170 */ 1171 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 1172 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 1173 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 1174 1175 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_2A 1176 1177 <legal 0> 1178 */ 1179 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000002c 1180 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 15 1181 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00008000 1182 1183 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS 1184 1185 Field only valid when Mpdu_frame_control_valid is set 1186 1187 1188 1189 Set if the from DS bit is set in the frame control. 1190 1191 <legal all> 1192 */ 1193 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c 1194 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 1195 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 1196 1197 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS 1198 1199 Field only valid when Mpdu_frame_control_valid is set 1200 1201 1202 1203 Set if the to DS bit is set in the frame control. 1204 1205 <legal all> 1206 */ 1207 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c 1208 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 1209 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 1210 1211 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED 1212 1213 Field only valid when Mpdu_frame_control_valid is set. 1214 1215 1216 1217 Protected bit from the frame control. 1218 1219 <legal all> 1220 */ 1221 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c 1222 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 1223 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 1224 1225 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY 1226 1227 Field only valid when Mpdu_frame_control_valid is set. 1228 1229 1230 1231 Retry bit from the frame control. Only valid when 1232 first_msdu is set. 1233 1234 <legal all> 1235 */ 1236 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c 1237 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 1238 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 1239 1240 /* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 1241 1242 Field only valid when Mpdu_sequence_control_valid is 1243 set. 1244 1245 1246 1247 The sequence number from the 802.11 header. 1248 1249 <legal all> 1250 */ 1251 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 1252 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 1253 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1254 1255 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET 1256 1257 1258 1259 1260 The key ID octet from the IV. 1261 1262 1263 1264 In case of ndp or phy_err or AST_based_lookup_valid == 1265 0, this field will be set to 0 1266 1267 <legal all> 1268 */ 1269 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 1270 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1271 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff 1272 1273 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY 1274 1275 In case of ndp or phy_err or AST_based_lookup_valid == 1276 0, this field will be set to 0 1277 1278 1279 1280 Set if new RX_PEER_ENTRY TLV follows. If clear, 1281 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 1282 uses old peer entry or not decrypt. 1283 1284 <legal all> 1285 */ 1286 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 1287 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1288 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 1289 1290 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED 1291 1292 In case of ndp or phy_err or AST_based_lookup_valid == 1293 0, this field will be set to 0 1294 1295 1296 1297 Set if decryption is needed. 1298 1299 1300 1301 Note: 1302 1303 When RXPCU sets bit 'ast_index_not_found' and/or 1304 ast_index_timeout', RXPCU will also ensure that this bit is 1305 NOT set 1306 1307 CRYPTO for that reason only needs to evaluate this bit 1308 and non of the other ones. 1309 1310 <legal all> 1311 */ 1312 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 1313 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1314 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 1315 1316 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE 1317 1318 In case of ndp or phy_err or AST_based_lookup_valid == 1319 0, this field will be set to 0 1320 1321 1322 1323 Used by the OLE during decapsulation. 1324 1325 1326 1327 Indicates the decapsulation that HW will perform: 1328 1329 1330 1331 <enum 0 RAW> No encapsulation 1332 1333 <enum 1 Native_WiFi> 1334 1335 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 1336 SNAP/LLC) 1337 1338 <enum 3 802_3> Indicate Ethernet 1339 1340 1341 1342 <legal all> 1343 */ 1344 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 1345 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1346 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 1347 1348 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING 1349 1350 In case of ndp or phy_err or AST_based_lookup_valid == 1351 0, this field will be set to 0 1352 1353 1354 1355 Insert 4 byte of all zeros as VLAN tag if the rx payload 1356 does not have VLAN. Used during decapsulation. 1357 1358 <legal all> 1359 */ 1360 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1361 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1362 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1363 1364 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING 1365 1366 In case of ndp or phy_err or AST_based_lookup_valid == 1367 0, this field will be set to 0 1368 1369 1370 1371 Insert 4 byte of all zeros as double VLAN tag if the rx 1372 payload does not have VLAN. Used during 1373 1374 <legal all> 1375 */ 1376 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1377 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1378 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1379 1380 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP 1381 1382 In case of ndp or phy_err or AST_based_lookup_valid == 1383 0, this field will be set to 0 1384 1385 1386 1387 Strip the VLAN during decapsulation. Used by the OLE. 1388 1389 <legal all> 1390 */ 1391 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1392 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1393 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1394 1395 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP 1396 1397 In case of ndp or phy_err or AST_based_lookup_valid == 1398 0, this field will be set to 0 1399 1400 1401 1402 Strip the double VLAN during decapsulation. Used by 1403 the OLE. 1404 1405 <legal all> 1406 */ 1407 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1408 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1409 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1410 1411 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT 1412 1413 The number of delimiters before this MPDU. 1414 1415 1416 1417 Note that this number is cleared at PPDU start. 1418 1419 1420 1421 If this MPDU is the first received MPDU in the PPDU and 1422 this MPDU gets filtered-in, this field will indicate the 1423 number of delimiters located after the last MPDU in the 1424 previous PPDU. 1425 1426 1427 1428 If this MPDU is located after the first received MPDU in 1429 an PPDU, this field will indicate the number of delimiters 1430 located between the previous MPDU and this MPDU. 1431 1432 1433 1434 In case of ndp or phy_err, this field will indicate the 1435 number of delimiters located after the last MPDU in the 1436 previous PPDU. 1437 1438 <legal all> 1439 */ 1440 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 1441 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1442 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 1443 1444 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG 1445 1446 When set, received frame was part of an A-MPDU. 1447 1448 1449 1450 1451 <legal all> 1452 */ 1453 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 1454 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1455 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 1456 1457 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME 1458 1459 In case of ndp or phy_err or AST_based_lookup_valid == 1460 0, this field will be set to 0 1461 1462 1463 1464 When set, received frame is a BAR frame 1465 1466 <legal all> 1467 */ 1468 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 1469 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1470 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 1471 1472 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU 1473 1474 Consumer: SW 1475 1476 Producer: RXOLE 1477 1478 1479 1480 RXPCU sets this field to 0 and RXOLE overwrites it. 1481 1482 1483 1484 Set to 1 by RXOLE when it has not performed any 802.11 1485 to Ethernet/Natvie WiFi header conversion on this MPDU. 1486 1487 <legal all> 1488 */ 1489 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 1490 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 1491 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 1492 1493 /* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12 1494 1495 <legal 0> 1496 */ 1497 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 1498 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 1499 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 1500 1501 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH 1502 1503 In case of ndp or phy_err this field will be set to 0 1504 1505 1506 1507 MPDU length before decapsulation. 1508 1509 <legal all> 1510 */ 1511 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 1512 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 1513 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff 1514 1515 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU 1516 1517 See definition in RX attention descriptor 1518 1519 1520 1521 In case of ndp or phy_err, this field will be set. Note 1522 however that there will not actually be any data contents in 1523 the MPDU. 1524 1525 <legal all> 1526 */ 1527 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 1528 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 1529 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 1530 1531 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST 1532 1533 In case of ndp or phy_err or Phy_err_during_mpdu_header 1534 this field will be set to 0 1535 1536 1537 1538 See definition in RX attention descriptor 1539 1540 <legal all> 1541 */ 1542 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 1543 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 1544 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 1545 1546 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND 1547 1548 In case of ndp or phy_err or Phy_err_during_mpdu_header 1549 this field will be set to 0 1550 1551 1552 1553 See definition in RX attention descriptor 1554 1555 <legal all> 1556 */ 1557 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1558 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 1559 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 1560 1561 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT 1562 1563 In case of ndp or phy_err or Phy_err_during_mpdu_header 1564 this field will be set to 0 1565 1566 1567 1568 See definition in RX attention descriptor 1569 1570 <legal all> 1571 */ 1572 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1573 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 1574 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 1575 1576 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT 1577 1578 In case of ndp or phy_err or Phy_err_during_mpdu_header 1579 this field will be set to 0 1580 1581 1582 1583 See definition in RX attention descriptor 1584 1585 <legal all> 1586 */ 1587 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 1588 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 1589 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 1590 1591 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS 1592 1593 In case of ndp or phy_err or Phy_err_during_mpdu_header 1594 this field will be set to 1 1595 1596 1597 1598 See definition in RX attention descriptor 1599 1600 <legal all> 1601 */ 1602 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 1603 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 1604 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 1605 1606 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA 1607 1608 In case of ndp or phy_err or Phy_err_during_mpdu_header 1609 this field will be set to 0 1610 1611 1612 1613 See definition in RX attention descriptor 1614 1615 <legal all> 1616 */ 1617 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 1618 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 1619 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 1620 1621 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE 1622 1623 In case of ndp or phy_err or Phy_err_during_mpdu_header 1624 this field will be set to 0 1625 1626 1627 1628 See definition in RX attention descriptor 1629 1630 <legal all> 1631 */ 1632 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 1633 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 1634 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 1635 1636 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE 1637 1638 In case of ndp or phy_err or Phy_err_during_mpdu_header 1639 this field will be set to 0 1640 1641 1642 1643 See definition in RX attention descriptor 1644 1645 <legal all> 1646 */ 1647 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 1648 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 1649 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 1650 1651 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA 1652 1653 In case of ndp or phy_err or Phy_err_during_mpdu_header 1654 this field will be set to 0 1655 1656 1657 1658 See definition in RX attention descriptor 1659 1660 <legal all> 1661 */ 1662 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 1663 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 1664 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 1665 1666 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP 1667 1668 In case of ndp or phy_err or Phy_err_during_mpdu_header 1669 this field will be set to 0 1670 1671 1672 1673 See definition in RX attention descriptor 1674 1675 <legal all> 1676 */ 1677 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 1678 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 1679 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 1680 1681 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG 1682 1683 In case of ndp or phy_err or Phy_err_during_mpdu_header 1684 this field will be set to 0 1685 1686 1687 1688 See definition in RX attention descriptor 1689 1690 <legal all> 1691 */ 1692 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 1693 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 1694 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 1695 1696 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER 1697 1698 In case of ndp or phy_err or Phy_err_during_mpdu_header 1699 this field will be set to 0 1700 1701 1702 1703 See definition in RX attention descriptor 1704 1705 1706 1707 <legal all> 1708 */ 1709 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 1710 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 1711 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 1712 1713 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER 1714 1715 In case of ndp or phy_err or Phy_err_during_mpdu_header 1716 this field will be set to 0 1717 1718 1719 1720 See definition in RX attention descriptor 1721 1722 <legal all> 1723 */ 1724 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 1725 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 1726 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 1727 1728 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED 1729 1730 In case of ndp or phy_err or Phy_err_during_mpdu_header 1731 this field will be set to 0 1732 1733 1734 1735 See definition in RX attention descriptor 1736 1737 <legal all> 1738 */ 1739 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 1740 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 1741 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 1742 1743 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED 1744 1745 In case of ndp or phy_err or Phy_err_during_mpdu_header 1746 this field will be set to 0 1747 1748 1749 1750 See definition in RX attention descriptor 1751 1752 <legal all> 1753 */ 1754 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 1755 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 1756 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 1757 1758 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT 1759 1760 Field only valid when Mpdu_qos_control_valid is set 1761 1762 1763 1764 The 'amsdu_present' bit within the QoS control field of 1765 the MPDU 1766 1767 <legal all> 1768 */ 1769 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 1770 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 1771 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 1772 1773 /* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13 1774 1775 <legal 0> 1776 */ 1777 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 1778 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 1779 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 1780 1781 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD 1782 1783 Field only valid when Mpdu_frame_control_valid is set 1784 1785 1786 1787 The frame control field of this received MPDU. 1788 1789 1790 1791 Field only valid when Ndp_frame and phy_err are NOT set 1792 1793 1794 1795 Bytes 0 + 1 of the received MPDU 1796 1797 <legal all> 1798 */ 1799 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1800 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1801 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1802 1803 /* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD 1804 1805 Field only valid when Mpdu_duration_valid is set 1806 1807 1808 1809 The duration field of this received MPDU. 1810 1811 <legal all> 1812 */ 1813 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 1814 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1815 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 1816 1817 /* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0 1818 1819 Field only valid when mac_addr_ad1_valid is set 1820 1821 1822 1823 The Least Significant 4 bytes of the Received Frames MAC 1824 Address AD1 1825 1826 <legal all> 1827 */ 1828 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1829 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 1830 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1831 1832 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32 1833 1834 Field only valid when mac_addr_ad1_valid is set 1835 1836 1837 1838 The 2 most significant bytes of the Received Frames MAC 1839 Address AD1 1840 1841 <legal all> 1842 */ 1843 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1844 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1845 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1846 1847 /* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0 1848 1849 Field only valid when mac_addr_ad2_valid is set 1850 1851 1852 1853 The Least Significant 2 bytes of the Received Frames MAC 1854 Address AD2 1855 1856 <legal all> 1857 */ 1858 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1859 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1860 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1861 1862 /* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16 1863 1864 Field only valid when mac_addr_ad2_valid is set 1865 1866 1867 1868 The 4 most significant bytes of the Received Frames MAC 1869 Address AD2 1870 1871 <legal all> 1872 */ 1873 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1874 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 1875 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1876 1877 /* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0 1878 1879 Field only valid when mac_addr_ad3_valid is set 1880 1881 1882 1883 The Least Significant 4 bytes of the Received Frames MAC 1884 Address AD3 1885 1886 <legal all> 1887 */ 1888 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1889 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1890 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1891 1892 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32 1893 1894 Field only valid when mac_addr_ad3_valid is set 1895 1896 1897 1898 The 2 most significant bytes of the Received Frames MAC 1899 Address AD3 1900 1901 <legal all> 1902 */ 1903 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1904 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 1905 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1906 1907 /* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD 1908 1909 1910 1911 1912 The sequence control field of the MPDU 1913 1914 <legal all> 1915 */ 1916 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1917 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1918 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1919 1920 /* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0 1921 1922 Field only valid when mac_addr_ad4_valid is set 1923 1924 1925 1926 The Least Significant 4 bytes of the Received Frames MAC 1927 Address AD4 1928 1929 <legal all> 1930 */ 1931 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1932 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1933 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1934 1935 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32 1936 1937 Field only valid when mac_addr_ad4_valid is set 1938 1939 1940 1941 The 2 most significant bytes of the Received Frames MAC 1942 Address AD4 1943 1944 <legal all> 1945 */ 1946 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1947 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 1948 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1949 1950 /* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD 1951 1952 Field only valid when mpdu_qos_control_valid is set 1953 1954 1955 1956 The sequence control field of the MPDU 1957 1958 <legal all> 1959 */ 1960 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1961 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 1962 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1963 1964 /* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD 1965 1966 Field only valid when mpdu_qos_control_valid is set 1967 1968 1969 1970 The HT control field of the MPDU 1971 1972 <legal all> 1973 */ 1974 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1975 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 1976 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1977 1978 1979 #endif // _RX_MPDU_START_H_ 1980