1 /*
2  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 //
20 // DO NOT EDIT!  This file is automatically generated
21 //               These definitions are tied to a particular hardware layout
22 
23 
24 #ifndef _RX_FLOW_SEARCH_ENTRY_H_
25 #define _RX_FLOW_SEARCH_ENTRY_H_
26 #if !defined(__ASSEMBLER__)
27 #endif
28 
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0	src_ip_127_96[31:0]
34 //	1	src_ip_95_64[31:0]
35 //	2	src_ip_63_32[31:0]
36 //	3	src_ip_31_0[31:0]
37 //	4	dest_ip_127_96[31:0]
38 //	5	dest_ip_95_64[31:0]
39 //	6	dest_ip_63_32[31:0]
40 //	7	dest_ip_31_0[31:0]
41 //	8	src_port[15:0], dest_port[31:16]
42 //	9	l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30]
43 //	10	metadata[31:0]
44 //	11	aggregation_count[6:0], lro_eligible[7], msdu_count[31:8]
45 //	12	msdu_byte_count[31:0]
46 //	13	timestamp[31:0]
47 //	14	cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
48 //	15	tcp_sequence_number[31:0]
49 //
50 // ################ END SUMMARY #################
51 
52 #define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
53 
54 struct rx_flow_search_entry {
55              uint32_t src_ip_127_96                   : 32; //[31:0]
56              uint32_t src_ip_95_64                    : 32; //[31:0]
57              uint32_t src_ip_63_32                    : 32; //[31:0]
58              uint32_t src_ip_31_0                     : 32; //[31:0]
59              uint32_t dest_ip_127_96                  : 32; //[31:0]
60              uint32_t dest_ip_95_64                   : 32; //[31:0]
61              uint32_t dest_ip_63_32                   : 32; //[31:0]
62              uint32_t dest_ip_31_0                    : 32; //[31:0]
63              uint32_t src_port                        : 16, //[15:0]
64                       dest_port                       : 16; //[31:16]
65              uint32_t l4_protocol                     :  8, //[7:0]
66                       valid                           :  1, //[8]
67                       reserved_9                      : 15, //[23:9]
68                       reo_destination_indication      :  5, //[28:24]
69                       msdu_drop                       :  1, //[29]
70                       reo_destination_handler         :  2; //[31:30]
71              uint32_t metadata                        : 32; //[31:0]
72              uint32_t aggregation_count               :  7, //[6:0]
73                       lro_eligible                    :  1, //[7]
74                       msdu_count                      : 24; //[31:8]
75              uint32_t msdu_byte_count                 : 32; //[31:0]
76              uint32_t timestamp                       : 32; //[31:0]
77              uint32_t cumulative_l4_checksum          : 16, //[15:0]
78                       cumulative_ip_length            : 16; //[31:16]
79              uint32_t tcp_sequence_number             : 32; //[31:0]
80 };
81 
82 /*
83 
84 src_ip_127_96
85 
86 			Uppermost 32 bits of source IPv6 address or prefix as
87 			per Common Parser register field IP_DA_SA_PREFIX (with the
88 			first byte in the MSB and the last byte in the LSB, i.e.
89 			requiring a byte-swap for little-endian SW w.r.t. the byte
90 			order in an IPv6 packet)
91 
92 			<legal all>
93 
94 src_ip_95_64
95 
96 			Next 32 bits of source IPv6 address or prefix (requiring
97 			a byte-swap for little-endian SW) <legal all>
98 
99 src_ip_63_32
100 
101 			Next 32 bits of source IPv6 address or lowest 32 bits of
102 			prefix (requiring a byte-swap for little-endian SW)
103 
104 			<legal all>
105 
106 src_ip_31_0
107 
108 			Lowest 32 bits of source IPv6 address, or source IPv4
109 			address (requiring a byte-swap for little-endian SW w.r.t.
110 			the byte order in an Ipv6 or IPv4 packet)
111 
112 			<legal all>
113 
114 dest_ip_127_96
115 
116 			Uppermost 32 bits of destination IPv6 address or prefix
117 			as per Common Parser register field IP_DA_SA_PREFIX (with
118 			the first byte in the MSB and the last byte in the LSB, i.e.
119 			requiring a byte-swap for little-endian SW w.r.t. the byte
120 			order as in an IPv6 packet)
121 
122 			<legal all>
123 
124 dest_ip_95_64
125 
126 			Next 32 bits of destination IPv6 address or prefix
127 			(requiring a byte-swap for little-endian SW)
128 
129 			<legal all>
130 
131 dest_ip_63_32
132 
133 			Next 32 bits of destination IPv6 address or lowest 32
134 			bits of prefix (requiring a byte-swap for little-endian SW)
135 
136 			<legal all>
137 
138 dest_ip_31_0
139 
140 			Lowest 32 bits of destination IPv6 address, or
141 			destination IPv4 address (requiring a byte-swap for
142 			little-endian SW w.r.t. the byte order in an Ipv6 or IPv4
143 			packet)
144 
145 			<legal all>
146 
147 src_port
148 
149 			LSB of SPI in case of ESP/AH
150 
151 			else source port in case of TCP/UDP without IPsec,
152 
153 			else zeros in case of ICMP (with the first/third byte in
154 			the MSB and the second/fourth byte in the LSB, i.e.
155 			requiring a byte-swap for little-endian SW w.r.t. the byte
156 			order as in an Ipv6 or IPv4 packet)  <legal all>
157 
158 dest_port
159 
160 			MSB of SPI in case of ESP/AH
161 
162 			else destination port in case of TCP/UDP without IPsec,
163 
164 			else zeros in case of ICMP (with the first byte in the
165 			MSB and the second byte in the LSB, i.e. requiring a
166 			byte-swap for little-endian SW w.r.t. the byte order as in
167 			an Ipv6 or IPv4 packet)
168 
169 			<legal all>
170 
171 l4_protocol
172 
173 			IPsec or L4 protocol
174 
175 
176 
177 			<enum 1 ICMPV4>
178 
179 			<enum 6 TCP>
180 
181 			<enum 17 UDP>
182 
183 			<enum 50 ESP>
184 
185 			<enum 51 AH>
186 
187 			<enum 58 ICMPV6>
188 
189 			<legal 1, 6, 17, 50, 51, 58>
190 
191 valid
192 
193 			Indicates validity of entry
194 
195 			<legal all>
196 
197 reserved_9
198 
199 			<legal 0>
200 
201 reo_destination_indication
202 
203 			The ID of the REO exit ring where the MSDU frame shall
204 			push after (MPDU level) reordering has finished.
205 
206 
207 
208 			<enum 0 reo_destination_tcl> Reo will push the frame
209 			into the REO2TCL ring
210 
211 			<enum 1 reo_destination_sw1> Reo will push the frame
212 			into the REO2SW1 ring
213 
214 			<enum 2 reo_destination_sw2> Reo will push the frame
215 			into the REO2SW2 ring
216 
217 			<enum 3 reo_destination_sw3> Reo will push the frame
218 			into the REO2SW3 ring
219 
220 			<enum 4 reo_destination_sw4> Reo will push the frame
221 			into the REO2SW4 ring
222 
223 			<enum 5 reo_destination_release> Reo will push the frame
224 			into the REO_release ring
225 
226 			<enum 6 reo_destination_fw> Reo will push the frame into
227 			the REO2FW ring
228 
229 			<enum 7 reo_destination_sw5> Reo will push the frame
230 			into the REO2SW5 ring
231 
232 			<enum 8 reo_destination_sw6> Reo will push the frame
233 			into the REO2SW6 ring
234 
235 			<enum 9 reo_destination_9> REO remaps this <enum 10
236 			reo_destination_10> REO remaps this
237 
238 			<enum 11 reo_destination_11> REO remaps this
239 
240 			<enum 12 reo_destination_12> REO remaps this <enum 13
241 			reo_destination_13> REO remaps this
242 
243 			<enum 14 reo_destination_14> REO remaps this
244 
245 			<enum 15 reo_destination_15> REO remaps this
246 
247 			<enum 16 reo_destination_16> REO remaps this
248 
249 			<enum 17 reo_destination_17> REO remaps this
250 
251 			<enum 18 reo_destination_18> REO remaps this
252 
253 			<enum 19 reo_destination_19> REO remaps this
254 
255 			<enum 20 reo_destination_20> REO remaps this
256 
257 			<enum 21 reo_destination_21> REO remaps this
258 
259 			<enum 22 reo_destination_22> REO remaps this
260 
261 			<enum 23 reo_destination_23> REO remaps this
262 
263 			<enum 24 reo_destination_24> REO remaps this
264 
265 			<enum 25 reo_destination_25> REO remaps this
266 
267 			<enum 26 reo_destination_26> REO remaps this
268 
269 			<enum 27 reo_destination_27> REO remaps this
270 
271 			<enum 28 reo_destination_28> REO remaps this
272 
273 			<enum 29 reo_destination_29> REO remaps this
274 
275 			<enum 30 reo_destination_30> REO remaps this
276 
277 			<enum 31 reo_destination_31> REO remaps this
278 
279 
280 
281 			<legal all>
282 
283 msdu_drop
284 
285 			Overriding indication to REO to forward to REO release
286 			ring
287 
288 			<legal all>
289 
290 reo_destination_handler
291 
292 			Indicates how to decide the REO destination indication
293 
294 			<enum 0 RXFT_USE_FT> Follow this entry
295 
296 			<enum 1 RXFT_USE_ASPT> Use address search+peer table
297 			entry
298 
299 			<enum 2 RXFT_USE_FT2> Follow this entry
300 
301 			<enum 3 RXFT_USE_CCE> Use CCE super-rule
302 
303 			<legal all>
304 
305 metadata
306 
307 			Value to be passed to SW if this flow search entry
308 			matches
309 
310 			<legal all>
311 
312 aggregation_count
313 
314 			FISA: Number'of MSDU's aggregated so far
315 
316 
317 
318 			Set to zero in chips not supporting FISA, e.g. Pine
319 
320 			<legal all>
321 
322 lro_eligible
323 
324 			FISA: To indicate whether the previous MSDU for this
325 			flow is eligible for LRO/FISA
326 
327 
328 
329 			Set to zero in chips not supporting FISA, e.g. Pine
330 
331 			<legal all>
332 
333 msdu_count
334 
335 			Number of Rx MSDUs matching this flow
336 
337 			<legal all>
338 
339 msdu_byte_count
340 
341 			Number of bytes in Rx MSDUs matching this flow
342 
343 			<legal all>
344 
345 timestamp
346 
347 			Time of last reception (as measured at Rx OLE) matching
348 			this flow
349 
350 			<legal all>
351 
352 cumulative_l4_checksum
353 
354 			FISA: checksum 'or MSDU's that is part of this flow
355 			aggregated so far
356 
357 
358 
359 			Set to zero in chips not supporting FISA, e.g. Pine
360 
361 			<legal all>
362 
363 cumulative_ip_length
364 
365 			FISA: Total MSDU length that is part of this flow
366 			aggregated so far
367 
368 
369 
370 			Set to zero in chips not supporting FISA, e.g. Pine
371 
372 			<legal all>
373 
374 tcp_sequence_number
375 
376 			FISA: TCP Sequence number of the last packet in this
377 			flow to detect sequence number jump
378 
379 
380 
381 			Set to zero in chips not supporting FISA, e.g. Pine
382 
383 			<legal all>
384 */
385 
386 
387 /* Description		RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96
388 
389 			Uppermost 32 bits of source IPv6 address or prefix as
390 			per Common Parser register field IP_DA_SA_PREFIX (with the
391 			first byte in the MSB and the last byte in the LSB, i.e.
392 			requiring a byte-swap for little-endian SW w.r.t. the byte
393 			order in an IPv6 packet)
394 
395 			<legal all>
396 */
397 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET                  0x00000000
398 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB                     0
399 #define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK                    0xffffffff
400 
401 /* Description		RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64
402 
403 			Next 32 bits of source IPv6 address or prefix (requiring
404 			a byte-swap for little-endian SW) <legal all>
405 */
406 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET                   0x00000004
407 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB                      0
408 #define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK                     0xffffffff
409 
410 /* Description		RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32
411 
412 			Next 32 bits of source IPv6 address or lowest 32 bits of
413 			prefix (requiring a byte-swap for little-endian SW)
414 
415 			<legal all>
416 */
417 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET                   0x00000008
418 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB                      0
419 #define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK                     0xffffffff
420 
421 /* Description		RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0
422 
423 			Lowest 32 bits of source IPv6 address, or source IPv4
424 			address (requiring a byte-swap for little-endian SW w.r.t.
425 			the byte order in an Ipv6 or IPv4 packet)
426 
427 			<legal all>
428 */
429 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET                    0x0000000c
430 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB                       0
431 #define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK                      0xffffffff
432 
433 /* Description		RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96
434 
435 			Uppermost 32 bits of destination IPv6 address or prefix
436 			as per Common Parser register field IP_DA_SA_PREFIX (with
437 			the first byte in the MSB and the last byte in the LSB, i.e.
438 			requiring a byte-swap for little-endian SW w.r.t. the byte
439 			order as in an IPv6 packet)
440 
441 			<legal all>
442 */
443 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET                 0x00000010
444 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB                    0
445 #define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK                   0xffffffff
446 
447 /* Description		RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64
448 
449 			Next 32 bits of destination IPv6 address or prefix
450 			(requiring a byte-swap for little-endian SW)
451 
452 			<legal all>
453 */
454 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET                  0x00000014
455 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB                     0
456 #define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK                    0xffffffff
457 
458 /* Description		RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32
459 
460 			Next 32 bits of destination IPv6 address or lowest 32
461 			bits of prefix (requiring a byte-swap for little-endian SW)
462 
463 			<legal all>
464 */
465 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET                  0x00000018
466 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB                     0
467 #define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK                    0xffffffff
468 
469 /* Description		RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0
470 
471 			Lowest 32 bits of destination IPv6 address, or
472 			destination IPv4 address (requiring a byte-swap for
473 			little-endian SW w.r.t. the byte order in an Ipv6 or IPv4
474 			packet)
475 
476 			<legal all>
477 */
478 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET                   0x0000001c
479 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB                      0
480 #define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK                     0xffffffff
481 
482 /* Description		RX_FLOW_SEARCH_ENTRY_8_SRC_PORT
483 
484 			LSB of SPI in case of ESP/AH
485 
486 			else source port in case of TCP/UDP without IPsec,
487 
488 			else zeros in case of ICMP (with the first/third byte in
489 			the MSB and the second/fourth byte in the LSB, i.e.
490 			requiring a byte-swap for little-endian SW w.r.t. the byte
491 			order as in an Ipv6 or IPv4 packet)  <legal all>
492 */
493 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET                       0x00000020
494 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB                          0
495 #define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK                         0x0000ffff
496 
497 /* Description		RX_FLOW_SEARCH_ENTRY_8_DEST_PORT
498 
499 			MSB of SPI in case of ESP/AH
500 
501 			else destination port in case of TCP/UDP without IPsec,
502 
503 			else zeros in case of ICMP (with the first byte in the
504 			MSB and the second byte in the LSB, i.e. requiring a
505 			byte-swap for little-endian SW w.r.t. the byte order as in
506 			an Ipv6 or IPv4 packet)
507 
508 			<legal all>
509 */
510 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET                      0x00000020
511 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB                         16
512 #define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK                        0xffff0000
513 
514 /* Description		RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL
515 
516 			IPsec or L4 protocol
517 
518 
519 
520 			<enum 1 ICMPV4>
521 
522 			<enum 6 TCP>
523 
524 			<enum 17 UDP>
525 
526 			<enum 50 ESP>
527 
528 			<enum 51 AH>
529 
530 			<enum 58 ICMPV6>
531 
532 			<legal 1, 6, 17, 50, 51, 58>
533 */
534 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET                    0x00000024
535 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB                       0
536 #define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK                      0x000000ff
537 
538 /* Description		RX_FLOW_SEARCH_ENTRY_9_VALID
539 
540 			Indicates validity of entry
541 
542 			<legal all>
543 */
544 #define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET                          0x00000024
545 #define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB                             8
546 #define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK                            0x00000100
547 
548 /* Description		RX_FLOW_SEARCH_ENTRY_9_RESERVED_9
549 
550 			<legal 0>
551 */
552 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET                     0x00000024
553 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB                        9
554 #define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK                       0x00fffe00
555 
556 /* Description		RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION
557 
558 			The ID of the REO exit ring where the MSDU frame shall
559 			push after (MPDU level) reordering has finished.
560 
561 
562 
563 			<enum 0 reo_destination_tcl> Reo will push the frame
564 			into the REO2TCL ring
565 
566 			<enum 1 reo_destination_sw1> Reo will push the frame
567 			into the REO2SW1 ring
568 
569 			<enum 2 reo_destination_sw2> Reo will push the frame
570 			into the REO2SW2 ring
571 
572 			<enum 3 reo_destination_sw3> Reo will push the frame
573 			into the REO2SW3 ring
574 
575 			<enum 4 reo_destination_sw4> Reo will push the frame
576 			into the REO2SW4 ring
577 
578 			<enum 5 reo_destination_release> Reo will push the frame
579 			into the REO_release ring
580 
581 			<enum 6 reo_destination_fw> Reo will push the frame into
582 			the REO2FW ring
583 
584 			<enum 7 reo_destination_sw5> Reo will push the frame
585 			into the REO2SW5 ring
586 
587 			<enum 8 reo_destination_sw6> Reo will push the frame
588 			into the REO2SW6 ring
589 
590 			<enum 9 reo_destination_9> REO remaps this <enum 10
591 			reo_destination_10> REO remaps this
592 
593 			<enum 11 reo_destination_11> REO remaps this
594 
595 			<enum 12 reo_destination_12> REO remaps this <enum 13
596 			reo_destination_13> REO remaps this
597 
598 			<enum 14 reo_destination_14> REO remaps this
599 
600 			<enum 15 reo_destination_15> REO remaps this
601 
602 			<enum 16 reo_destination_16> REO remaps this
603 
604 			<enum 17 reo_destination_17> REO remaps this
605 
606 			<enum 18 reo_destination_18> REO remaps this
607 
608 			<enum 19 reo_destination_19> REO remaps this
609 
610 			<enum 20 reo_destination_20> REO remaps this
611 
612 			<enum 21 reo_destination_21> REO remaps this
613 
614 			<enum 22 reo_destination_22> REO remaps this
615 
616 			<enum 23 reo_destination_23> REO remaps this
617 
618 			<enum 24 reo_destination_24> REO remaps this
619 
620 			<enum 25 reo_destination_25> REO remaps this
621 
622 			<enum 26 reo_destination_26> REO remaps this
623 
624 			<enum 27 reo_destination_27> REO remaps this
625 
626 			<enum 28 reo_destination_28> REO remaps this
627 
628 			<enum 29 reo_destination_29> REO remaps this
629 
630 			<enum 30 reo_destination_30> REO remaps this
631 
632 			<enum 31 reo_destination_31> REO remaps this
633 
634 
635 
636 			<legal all>
637 */
638 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET     0x00000024
639 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB        24
640 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK       0x1f000000
641 
642 /* Description		RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP
643 
644 			Overriding indication to REO to forward to REO release
645 			ring
646 
647 			<legal all>
648 */
649 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET                      0x00000024
650 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB                         29
651 #define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK                        0x20000000
652 
653 /* Description		RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER
654 
655 			Indicates how to decide the REO destination indication
656 
657 			<enum 0 RXFT_USE_FT> Follow this entry
658 
659 			<enum 1 RXFT_USE_ASPT> Use address search+peer table
660 			entry
661 
662 			<enum 2 RXFT_USE_FT2> Follow this entry
663 
664 			<enum 3 RXFT_USE_CCE> Use CCE super-rule
665 
666 			<legal all>
667 */
668 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET        0x00000024
669 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB           30
670 #define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK          0xc0000000
671 
672 /* Description		RX_FLOW_SEARCH_ENTRY_10_METADATA
673 
674 			Value to be passed to SW if this flow search entry
675 			matches
676 
677 			<legal all>
678 */
679 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET                      0x00000028
680 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB                         0
681 #define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK                        0xffffffff
682 
683 /* Description		RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT
684 
685 			FISA: Number'of MSDU's aggregated so far
686 
687 
688 
689 			Set to zero in chips not supporting FISA, e.g. Pine
690 
691 			<legal all>
692 */
693 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET             0x0000002c
694 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB                0
695 #define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK               0x0000007f
696 
697 /* Description		RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE
698 
699 			FISA: To indicate whether the previous MSDU for this
700 			flow is eligible for LRO/FISA
701 
702 
703 
704 			Set to zero in chips not supporting FISA, e.g. Pine
705 
706 			<legal all>
707 */
708 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET                  0x0000002c
709 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB                     7
710 #define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK                    0x00000080
711 
712 /* Description		RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT
713 
714 			Number of Rx MSDUs matching this flow
715 
716 			<legal all>
717 */
718 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET                    0x0000002c
719 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB                       8
720 #define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK                      0xffffff00
721 
722 /* Description		RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT
723 
724 			Number of bytes in Rx MSDUs matching this flow
725 
726 			<legal all>
727 */
728 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET               0x00000030
729 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB                  0
730 #define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK                 0xffffffff
731 
732 /* Description		RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP
733 
734 			Time of last reception (as measured at Rx OLE) matching
735 			this flow
736 
737 			<legal all>
738 */
739 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET                     0x00000034
740 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB                        0
741 #define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK                       0xffffffff
742 
743 /* Description		RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM
744 
745 			FISA: checksum 'or MSDU's that is part of this flow
746 			aggregated so far
747 
748 
749 
750 			Set to zero in chips not supporting FISA, e.g. Pine
751 
752 			<legal all>
753 */
754 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET        0x00000038
755 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB           0
756 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK          0x0000ffff
757 
758 /* Description		RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH
759 
760 			FISA: Total MSDU length that is part of this flow
761 			aggregated so far
762 
763 
764 
765 			Set to zero in chips not supporting FISA, e.g. Pine
766 
767 			<legal all>
768 */
769 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET          0x00000038
770 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB             16
771 #define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK            0xffff0000
772 
773 /* Description		RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER
774 
775 			FISA: TCP Sequence number of the last packet in this
776 			flow to detect sequence number jump
777 
778 
779 
780 			Set to zero in chips not supporting FISA, e.g. Pine
781 
782 			<legal all>
783 */
784 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET           0x0000003c
785 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB              0
786 #define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK             0xffffffff
787 
788 
789 #endif // _RX_FLOW_SEARCH_ENTRY_H_
790