1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _TCL_GSE_CMD_H_ 20 #define _TCL_GSE_CMD_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 control_buffer_addr_31_0[31:0] 29 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20] 30 // 2 cmd_meta_data_31_0[31:0] 31 // 3 cmd_meta_data_63_32[31:0] 32 // 4 reserved_4a[31:0] 33 // 5 reserved_5a[31:0] 34 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 35 // 36 // ################ END SUMMARY ################# 37 38 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 39 40 struct tcl_gse_cmd { 41 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 42 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 43 gse_ctrl : 4, //[11:8] 44 gse_sel : 1, //[12] 45 status_destination_ring_id : 1, //[13] 46 swap : 1, //[14] 47 index_search_en : 1, //[15] 48 cache_set_num : 4, //[19:16] 49 reserved_1a : 12; //[31:20] 50 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 51 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 52 uint32_t reserved_4a : 32; //[31:0] 53 uint32_t reserved_5a : 32; //[31:0] 54 uint32_t reserved_6a : 20, //[19:0] 55 ring_id : 8, //[27:20] 56 looping_count : 4; //[31:28] 57 }; 58 59 /* 60 61 control_buffer_addr_31_0 62 63 Address (lower 32 bits) of a control buffer containing 64 additional info needed for this command execution. 65 66 <legal all> 67 68 control_buffer_addr_39_32 69 70 Address (upper 8 bits) of a control buffer containing 71 additional info needed for this command execution. 72 73 <legal all> 74 75 gse_ctrl 76 77 GSE control operations. This includes cache operations 78 and table entry statistics read/clear operation. 79 80 <enum 0 rd_stat> Report or Read statistics 81 82 <enum 1 srch_dis> Search disable. Report only Hash 83 84 <enum 2 Wr_bk_single> Write Back single entry 85 86 <enum 3 wr_bk_all> Write Back entire cache entry 87 88 <enum 4 inval_single> Invalidate single cache entry 89 90 <enum 5 inval_all> Invalidate entire cache 91 92 <enum 6 wr_bk_inval_single> Write back and Invalidate 93 single entry in cache 94 95 <enum 7 wr_bk_inval_all> write back and invalidate 96 entire cache 97 98 <enum 8 clr_stat_single> Clear statistics for single 99 entry 100 101 <legal 0-8> 102 103 Rest of the values reserved. 104 105 For all single entry control operations (write back, 106 Invalidate or both)Statistics will be reported 107 108 gse_sel 109 110 Bit to select the ASE or FSE to do the operation mention 111 by GSE_ctrl bit 112 113 0: FSE select 114 115 1: ASE select 116 117 status_destination_ring_id 118 119 The TCL status ring to which the GSE status needs to be 120 send. 121 122 123 124 <enum 0 tcl_status_0_ring> 125 126 <enum 1 tcl_status_1_ring> 127 128 129 130 <legal all> 131 132 swap 133 134 Bit to enable byte swapping of contents of buffer 135 136 <enum 0 Byte_swap_disable > 137 138 <enum 1 byte_swap_enable > 139 140 <legal all> 141 142 index_search_en 143 144 When this bit is set to 1 control_buffer_addr[19:0] will 145 be considered as index of the AST or Flow table and GSE 146 commands will be executed accordingly on the entry pointed 147 by the index. 148 149 This feature is disabled by setting this bit to 0. 150 151 <enum 0 index_based_cmd_disable> 152 153 <enum 1 index_based_cmd_enable> 154 155 156 157 <legal all> 158 159 cache_set_num 160 161 Cache set number that should be used to cache the index 162 based search results, for address and flow search. This 163 value should be equal to value of cache_set_num for the 164 index that is issued in TCL_DATA_CMD during search index 165 based ASE or FSE. This field is valid for index based GSE 166 commands 167 168 <legal all> 169 170 reserved_1a 171 172 <legal 0> 173 174 cmd_meta_data_31_0 175 176 Meta data to be returned in the status descriptor 177 178 <legal all> 179 180 cmd_meta_data_63_32 181 182 Meta data to be returned in the status descriptor 183 184 <legal all> 185 186 reserved_4a 187 188 <legal 0> 189 190 reserved_5a 191 192 <legal 0> 193 194 reserved_6a 195 196 <legal 0> 197 198 ring_id 199 200 Helps with debugging when dumping ring contents. 201 202 <legal all> 203 204 looping_count 205 206 A count value that indicates the number of times the 207 producer of entries into the Ring has looped around the 208 ring. 209 210 At initialization time, this value is set to 0. On the 211 first loop, this value is set to 1. After the max value is 212 reached allowed by the number of bits for this field, the 213 count value continues with 0 again. 214 215 216 217 In case SW is the consumer of the ring entries, it can 218 use this field to figure out up to where the producer of 219 entries has created new entries. This eliminates the need to 220 check where the head pointer' of the ring is located once 221 the SW starts processing an interrupt indicating that new 222 entries have been put into this ring... 223 224 225 226 Also note that SW if it wants only needs to look at the 227 LSB bit of this count value. 228 229 <legal all> 230 */ 231 232 233 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 234 235 Address (lower 32 bits) of a control buffer containing 236 additional info needed for this command execution. 237 238 <legal all> 239 */ 240 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 241 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 242 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 243 244 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 245 246 Address (upper 8 bits) of a control buffer containing 247 additional info needed for this command execution. 248 249 <legal all> 250 */ 251 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 252 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 253 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 254 255 /* Description TCL_GSE_CMD_1_GSE_CTRL 256 257 GSE control operations. This includes cache operations 258 and table entry statistics read/clear operation. 259 260 <enum 0 rd_stat> Report or Read statistics 261 262 <enum 1 srch_dis> Search disable. Report only Hash 263 264 <enum 2 Wr_bk_single> Write Back single entry 265 266 <enum 3 wr_bk_all> Write Back entire cache entry 267 268 <enum 4 inval_single> Invalidate single cache entry 269 270 <enum 5 inval_all> Invalidate entire cache 271 272 <enum 6 wr_bk_inval_single> Write back and Invalidate 273 single entry in cache 274 275 <enum 7 wr_bk_inval_all> write back and invalidate 276 entire cache 277 278 <enum 8 clr_stat_single> Clear statistics for single 279 entry 280 281 <legal 0-8> 282 283 Rest of the values reserved. 284 285 For all single entry control operations (write back, 286 Invalidate or both)Statistics will be reported 287 */ 288 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 289 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 290 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 291 292 /* Description TCL_GSE_CMD_1_GSE_SEL 293 294 Bit to select the ASE or FSE to do the operation mention 295 by GSE_ctrl bit 296 297 0: FSE select 298 299 1: ASE select 300 */ 301 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 302 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 303 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 304 305 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 306 307 The TCL status ring to which the GSE status needs to be 308 send. 309 310 311 312 <enum 0 tcl_status_0_ring> 313 314 <enum 1 tcl_status_1_ring> 315 316 317 318 <legal all> 319 */ 320 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 321 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 322 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 323 324 /* Description TCL_GSE_CMD_1_SWAP 325 326 Bit to enable byte swapping of contents of buffer 327 328 <enum 0 Byte_swap_disable > 329 330 <enum 1 byte_swap_enable > 331 332 <legal all> 333 */ 334 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 335 #define TCL_GSE_CMD_1_SWAP_LSB 14 336 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 337 338 /* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN 339 340 When this bit is set to 1 control_buffer_addr[19:0] will 341 be considered as index of the AST or Flow table and GSE 342 commands will be executed accordingly on the entry pointed 343 by the index. 344 345 This feature is disabled by setting this bit to 0. 346 347 <enum 0 index_based_cmd_disable> 348 349 <enum 1 index_based_cmd_enable> 350 351 352 353 <legal all> 354 */ 355 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 356 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 357 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 358 359 /* Description TCL_GSE_CMD_1_CACHE_SET_NUM 360 361 Cache set number that should be used to cache the index 362 based search results, for address and flow search. This 363 value should be equal to value of cache_set_num for the 364 index that is issued in TCL_DATA_CMD during search index 365 based ASE or FSE. This field is valid for index based GSE 366 commands 367 368 <legal all> 369 */ 370 #define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 371 #define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 372 #define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 373 374 /* Description TCL_GSE_CMD_1_RESERVED_1A 375 376 <legal 0> 377 */ 378 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 379 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 380 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 381 382 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 383 384 Meta data to be returned in the status descriptor 385 386 <legal all> 387 */ 388 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 389 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 390 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 391 392 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 393 394 Meta data to be returned in the status descriptor 395 396 <legal all> 397 */ 398 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 399 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 400 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 401 402 /* Description TCL_GSE_CMD_4_RESERVED_4A 403 404 <legal 0> 405 */ 406 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 407 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 408 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 409 410 /* Description TCL_GSE_CMD_5_RESERVED_5A 411 412 <legal 0> 413 */ 414 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 415 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 416 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 417 418 /* Description TCL_GSE_CMD_6_RESERVED_6A 419 420 <legal 0> 421 */ 422 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 423 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 424 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 425 426 /* Description TCL_GSE_CMD_6_RING_ID 427 428 Helps with debugging when dumping ring contents. 429 430 <legal all> 431 */ 432 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 433 #define TCL_GSE_CMD_6_RING_ID_LSB 20 434 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 435 436 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 437 438 A count value that indicates the number of times the 439 producer of entries into the Ring has looped around the 440 ring. 441 442 At initialization time, this value is set to 0. On the 443 first loop, this value is set to 1. After the max value is 444 reached allowed by the number of bits for this field, the 445 count value continues with 0 again. 446 447 448 449 In case SW is the consumer of the ring entries, it can 450 use this field to figure out up to where the producer of 451 entries has created new entries. This eliminates the need to 452 check where the head pointer' of the ring is located once 453 the SW starts processing an interrupt indicating that new 454 entries have been put into this ring... 455 456 457 458 Also note that SW if it wants only needs to look at the 459 LSB bit of this count value. 460 461 <legal all> 462 */ 463 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 464 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 465 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 466 467 468 #endif // _TCL_GSE_CMD_H_ 469