1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _RX_MPDU_INFO_H_ 20 #define _RX_MPDU_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "rxpt_classify_info.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16] 30 // 1 ast_index[15:0], sw_peer_id[31:16] 31 // 2 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_2a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] 32 // 3 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[8], bssid_hit[9], bssid_number[13:10], tid[17:14], reserved_3a[31:18] 33 // 4 pn_31_0[31:0] 34 // 5 pn_63_32[31:0] 35 // 6 pn_95_64[31:0] 36 // 7 pn_127_96[31:0] 37 // 8 peer_meta_data[31:0] 38 // 9 struct rxpt_classify_info rxpt_classify_info_details; 39 // 10 rx_reo_queue_desc_addr_31_0[31:0] 40 // 11 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26] 41 // 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30] 42 // 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31] 43 // 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] 44 // 15 mac_addr_ad1_31_0[31:0] 45 // 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] 46 // 17 mac_addr_ad2_47_16[31:0] 47 // 18 mac_addr_ad3_31_0[31:0] 48 // 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] 49 // 20 mac_addr_ad4_31_0[31:0] 50 // 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] 51 // 22 mpdu_ht_control_field[31:0] 52 // 53 // ################ END SUMMARY ################# 54 55 #define NUM_OF_DWORDS_RX_MPDU_INFO 23 56 57 struct rx_mpdu_info { 58 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 59 sw_frame_group_id : 7, //[8:2] 60 ndp_frame : 1, //[9] 61 phy_err : 1, //[10] 62 phy_err_during_mpdu_header : 1, //[11] 63 protocol_version_err : 1, //[12] 64 ast_based_lookup_valid : 1, //[13] 65 reserved_0a : 2, //[15:14] 66 phy_ppdu_id : 16; //[31:16] 67 uint32_t ast_index : 16, //[15:0] 68 sw_peer_id : 16; //[31:16] 69 uint32_t mpdu_frame_control_valid : 1, //[0] 70 mpdu_duration_valid : 1, //[1] 71 mac_addr_ad1_valid : 1, //[2] 72 mac_addr_ad2_valid : 1, //[3] 73 mac_addr_ad3_valid : 1, //[4] 74 mac_addr_ad4_valid : 1, //[5] 75 mpdu_sequence_control_valid : 1, //[6] 76 mpdu_qos_control_valid : 1, //[7] 77 mpdu_ht_control_valid : 1, //[8] 78 frame_encryption_info_valid : 1, //[9] 79 mpdu_fragment_number : 4, //[13:10] 80 more_fragment_flag : 1, //[14] 81 reserved_2a : 1, //[15] 82 fr_ds : 1, //[16] 83 to_ds : 1, //[17] 84 encrypted : 1, //[18] 85 mpdu_retry : 1, //[19] 86 mpdu_sequence_number : 12; //[31:20] 87 uint32_t epd_en : 1, //[0] 88 all_frames_shall_be_encrypted : 1, //[1] 89 encrypt_type : 4, //[5:2] 90 wep_key_width_for_variable_key : 2, //[7:6] 91 mesh_sta : 1, //[8] 92 bssid_hit : 1, //[9] 93 bssid_number : 4, //[13:10] 94 tid : 4, //[17:14] 95 reserved_3a : 14; //[31:18] 96 uint32_t pn_31_0 : 32; //[31:0] 97 uint32_t pn_63_32 : 32; //[31:0] 98 uint32_t pn_95_64 : 32; //[31:0] 99 uint32_t pn_127_96 : 32; //[31:0] 100 uint32_t peer_meta_data : 32; //[31:0] 101 struct rxpt_classify_info rxpt_classify_info_details; 102 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 103 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 104 receive_queue_number : 16, //[23:8] 105 pre_delim_err_warning : 1, //[24] 106 first_delim_err : 1, //[25] 107 reserved_11 : 6; //[31:26] 108 uint32_t key_id_octet : 8, //[7:0] 109 new_peer_entry : 1, //[8] 110 decrypt_needed : 1, //[9] 111 decap_type : 2, //[11:10] 112 rx_insert_vlan_c_tag_padding : 1, //[12] 113 rx_insert_vlan_s_tag_padding : 1, //[13] 114 strip_vlan_c_tag_decap : 1, //[14] 115 strip_vlan_s_tag_decap : 1, //[15] 116 pre_delim_count : 12, //[27:16] 117 ampdu_flag : 1, //[28] 118 bar_frame : 1, //[29] 119 reserved_12 : 2; //[31:30] 120 uint32_t mpdu_length : 14, //[13:0] 121 first_mpdu : 1, //[14] 122 mcast_bcast : 1, //[15] 123 ast_index_not_found : 1, //[16] 124 ast_index_timeout : 1, //[17] 125 power_mgmt : 1, //[18] 126 non_qos : 1, //[19] 127 null_data : 1, //[20] 128 mgmt_type : 1, //[21] 129 ctrl_type : 1, //[22] 130 more_data : 1, //[23] 131 eosp : 1, //[24] 132 fragment_flag : 1, //[25] 133 order : 1, //[26] 134 u_apsd_trigger : 1, //[27] 135 encrypt_required : 1, //[28] 136 directed : 1, //[29] 137 amsdu_present : 1, //[30] 138 reserved_13 : 1; //[31] 139 uint32_t mpdu_frame_control_field : 16, //[15:0] 140 mpdu_duration_field : 16; //[31:16] 141 uint32_t mac_addr_ad1_31_0 : 32; //[31:0] 142 uint32_t mac_addr_ad1_47_32 : 16, //[15:0] 143 mac_addr_ad2_15_0 : 16; //[31:16] 144 uint32_t mac_addr_ad2_47_16 : 32; //[31:0] 145 uint32_t mac_addr_ad3_31_0 : 32; //[31:0] 146 uint32_t mac_addr_ad3_47_32 : 16, //[15:0] 147 mpdu_sequence_control_field : 16; //[31:16] 148 uint32_t mac_addr_ad4_31_0 : 32; //[31:0] 149 uint32_t mac_addr_ad4_47_32 : 16, //[15:0] 150 mpdu_qos_control_field : 16; //[31:16] 151 uint32_t mpdu_ht_control_field : 32; //[31:0] 152 }; 153 154 /* 155 156 rxpcu_mpdu_filter_in_category 157 158 Field indicates what the reason was that this MPDU frame 159 was allowed to come into the receive path by RXPCU 160 161 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 162 frame filter programming of rxpcu 163 164 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 165 regular frame filter and would have been dropped, were it 166 not for the frame fitting into the 'monitor_client' 167 category. 168 169 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 170 regular frame filter and also did not pass the 171 rxpcu_monitor_client filter. It would have been dropped 172 accept that it did pass the 'monitor_other' category. 173 174 175 176 Note: for ndp frame, if it was expected because the 177 preceding NDPA was filter_pass, the setting 178 rxpcu_filter_pass will be used. This setting will also be 179 used for every ndp frame in case Promiscuous mode is 180 enabled. 181 182 183 184 In case promiscuous is not enabled, and an NDP is not 185 preceded by a NPDA filter pass frame, the only other setting 186 that could appear here for the NDP is rxpcu_monitor_other. 187 188 (rxpcu has a configuration bit specifically for this 189 scenario) 190 191 192 193 Note: for 194 195 <legal 0-2> 196 197 sw_frame_group_id 198 199 SW processes frames based on certain classifications. 200 This field indicates to what sw classification this MPDU is 201 mapped. 202 203 The classification is given in priority order 204 205 206 207 <enum 0 sw_frame_group_NDP_frame> Note: The 208 corresponding Rxpcu_Mpdu_filter_in_category can be 209 rxpcu_filter_pass or rxpcu_monitor_other 210 211 212 213 <enum 1 sw_frame_group_Multicast_data> 214 215 <enum 2 sw_frame_group_Unicast_data> 216 217 <enum 3 sw_frame_group_Null_data > This includes mpdus 218 of type Data Null as well as QoS Data Null 219 220 221 222 <enum 4 sw_frame_group_mgmt_0000 > 223 224 <enum 5 sw_frame_group_mgmt_0001 > 225 226 <enum 6 sw_frame_group_mgmt_0010 > 227 228 <enum 7 sw_frame_group_mgmt_0011 > 229 230 <enum 8 sw_frame_group_mgmt_0100 > 231 232 <enum 9 sw_frame_group_mgmt_0101 > 233 234 <enum 10 sw_frame_group_mgmt_0110 > 235 236 <enum 11 sw_frame_group_mgmt_0111 > 237 238 <enum 12 sw_frame_group_mgmt_1000 > 239 240 <enum 13 sw_frame_group_mgmt_1001 > 241 242 <enum 14 sw_frame_group_mgmt_1010 > 243 244 <enum 15 sw_frame_group_mgmt_1011 > 245 246 <enum 16 sw_frame_group_mgmt_1100 > 247 248 <enum 17 sw_frame_group_mgmt_1101 > 249 250 <enum 18 sw_frame_group_mgmt_1110 > 251 252 <enum 19 sw_frame_group_mgmt_1111 > 253 254 255 256 <enum 20 sw_frame_group_ctrl_0000 > 257 258 <enum 21 sw_frame_group_ctrl_0001 > 259 260 <enum 22 sw_frame_group_ctrl_0010 > 261 262 <enum 23 sw_frame_group_ctrl_0011 > 263 264 <enum 24 sw_frame_group_ctrl_0100 > 265 266 <enum 25 sw_frame_group_ctrl_0101 > 267 268 <enum 26 sw_frame_group_ctrl_0110 > 269 270 <enum 27 sw_frame_group_ctrl_0111 > 271 272 <enum 28 sw_frame_group_ctrl_1000 > 273 274 <enum 29 sw_frame_group_ctrl_1001 > 275 276 <enum 30 sw_frame_group_ctrl_1010 > 277 278 <enum 31 sw_frame_group_ctrl_1011 > 279 280 <enum 32 sw_frame_group_ctrl_1100 > 281 282 <enum 33 sw_frame_group_ctrl_1101 > 283 284 <enum 34 sw_frame_group_ctrl_1110 > 285 286 <enum 35 sw_frame_group_ctrl_1111 > 287 288 289 290 <enum 36 sw_frame_group_unsupported> This covers type 3 291 and protocol version != 0 292 293 Note: The corresponding Rxpcu_Mpdu_filter_in_category 294 can only be rxpcu_monitor_other 295 296 297 298 299 Note: The corresponding Rxpcu_Mpdu_filter_in_category 300 can be rxpcu_filter_pass 301 302 303 304 <legal 0-37> 305 306 ndp_frame 307 308 When set, the received frame was an NDP frame, and thus 309 there will be no MPDU data. 310 311 <legal all> 312 313 phy_err 314 315 When set, a PHY error was received before MAC received 316 any data, and thus there will be no MPDU data. 317 318 <legal all> 319 320 phy_err_during_mpdu_header 321 322 When set, a PHY error was received before MAC received 323 the complete MPDU header which was needed for proper 324 decoding 325 326 <legal all> 327 328 protocol_version_err 329 330 Set when RXPCU detected a version error in the Frame 331 control field 332 333 <legal all> 334 335 ast_based_lookup_valid 336 337 When set, AST based lookup for this frame has found a 338 valid result. 339 340 341 342 Note that for NDP frame this will never be set 343 344 <legal all> 345 346 reserved_0a 347 348 <legal 0> 349 350 phy_ppdu_id 351 352 A ppdu counter value that PHY increments for every PPDU 353 received. The counter value wraps around 354 355 <legal all> 356 357 ast_index 358 359 This field indicates the index of the AST entry 360 corresponding to this MPDU. It is provided by the GSE module 361 instantiated in RXPCU. 362 363 A value of 0xFFFF indicates an invalid AST index, 364 meaning that No AST entry was found or NO AST search was 365 performed 366 367 368 369 In case of ndp or phy_err, this field will be set to 370 0xFFFF 371 372 <legal all> 373 374 sw_peer_id 375 376 In case of ndp or phy_err or AST_based_lookup_valid == 377 0, this field will be set to 0 378 379 380 381 This field indicates a unique peer identifier. It is set 382 equal to field 'sw_peer_id' from the AST entry 383 384 385 386 <legal all> 387 388 mpdu_frame_control_valid 389 390 When set, the field Mpdu_Frame_control_field has valid 391 information 392 393 394 395 396 <legal all> 397 398 mpdu_duration_valid 399 400 When set, the field Mpdu_duration_field has valid 401 information 402 403 404 405 406 <legal all> 407 408 mac_addr_ad1_valid 409 410 When set, the fields mac_addr_ad1_..... have valid 411 information 412 413 414 415 416 <legal all> 417 418 mac_addr_ad2_valid 419 420 When set, the fields mac_addr_ad2_..... have valid 421 information 422 423 424 425 426 427 428 429 <legal all> 430 431 mac_addr_ad3_valid 432 433 When set, the fields mac_addr_ad3_..... have valid 434 information 435 436 437 438 439 440 441 442 <legal all> 443 444 mac_addr_ad4_valid 445 446 When set, the fields mac_addr_ad4_..... have valid 447 information 448 449 450 451 452 453 454 455 <legal all> 456 457 mpdu_sequence_control_valid 458 459 When set, the fields mpdu_sequence_control_field and 460 mpdu_sequence_number have valid information as well as field 461 462 463 464 For MPDUs without a sequence control field, this field 465 will not be set. 466 467 468 469 470 <legal all> 471 472 mpdu_qos_control_valid 473 474 When set, the field mpdu_qos_control_field has valid 475 information 476 477 478 479 For MPDUs without a QoS control field, this field will 480 not be set. 481 482 483 484 485 <legal all> 486 487 mpdu_ht_control_valid 488 489 When set, the field mpdu_HT_control_field has valid 490 information 491 492 493 494 For MPDUs without a HT control field, this field will 495 not be set. 496 497 498 499 500 <legal all> 501 502 frame_encryption_info_valid 503 504 When set, the encryption related info fields, like IV 505 and PN are valid 506 507 508 509 For MPDUs that are not encrypted, this will not be set. 510 511 512 513 514 <legal all> 515 516 mpdu_fragment_number 517 518 Field only valid when Mpdu_sequence_control_valid is set 519 AND Fragment_flag is set 520 521 522 523 The fragment number from the 802.11 header 524 525 526 527 <legal all> 528 529 more_fragment_flag 530 531 The More Fragment bit setting from the MPDU header of 532 the received frame 533 534 535 536 <legal all> 537 538 reserved_2a 539 540 <legal 0> 541 542 fr_ds 543 544 Field only valid when Mpdu_frame_control_valid is set 545 546 547 548 Set if the from DS bit is set in the frame control. 549 550 <legal all> 551 552 to_ds 553 554 Field only valid when Mpdu_frame_control_valid is set 555 556 557 558 Set if the to DS bit is set in the frame control. 559 560 <legal all> 561 562 encrypted 563 564 Field only valid when Mpdu_frame_control_valid is set. 565 566 567 568 Protected bit from the frame control. 569 570 <legal all> 571 572 mpdu_retry 573 574 Field only valid when Mpdu_frame_control_valid is set. 575 576 577 578 Retry bit from the frame control. Only valid when 579 first_msdu is set. 580 581 <legal all> 582 583 mpdu_sequence_number 584 585 Field only valid when Mpdu_sequence_control_valid is 586 set. 587 588 589 590 The sequence number from the 802.11 header. 591 592 <legal all> 593 594 epd_en 595 596 Field only valid when AST_based_lookup_valid == 1. 597 598 599 600 601 602 In case of ndp or phy_err or AST_based_lookup_valid == 603 0, this field will be set to 0 604 605 606 607 If set to one use EPD instead of LPD 608 609 610 611 612 <legal all> 613 614 all_frames_shall_be_encrypted 615 616 In case of ndp or phy_err or AST_based_lookup_valid == 617 0, this field will be set to 0 618 619 620 621 When set, all frames (data only ?) shall be encrypted. 622 If not, RX CRYPTO shall set an error flag. 623 624 <legal all> 625 626 encrypt_type 627 628 In case of ndp or phy_err or AST_based_lookup_valid == 629 0, this field will be set to 0 630 631 632 633 Indicates type of decrypt cipher used (as defined in the 634 peer entry) 635 636 637 638 <enum 0 wep_40> WEP 40-bit 639 640 <enum 1 wep_104> WEP 104-bit 641 642 <enum 2 tkip_no_mic> TKIP without MIC 643 644 <enum 3 wep_128> WEP 128-bit 645 646 <enum 4 tkip_with_mic> TKIP with MIC 647 648 <enum 5 wapi> WAPI 649 650 <enum 6 aes_ccmp_128> AES CCMP 128 651 652 <enum 7 no_cipher> No crypto 653 654 <enum 8 aes_ccmp_256> AES CCMP 256 655 656 <enum 9 aes_gcmp_128> AES CCMP 128 657 658 <enum 10 aes_gcmp_256> AES CCMP 256 659 660 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 661 662 663 664 <enum 12 wep_varied_width> WEP encryption. As for WEP 665 per keyid the key bit width can vary, the key bit width for 666 this MPDU will be indicated in field 667 wep_key_width_for_variable key 668 669 <legal 0-12> 670 671 wep_key_width_for_variable_key 672 673 Field only valid when key_type is set to 674 wep_varied_width. 675 676 677 678 This field indicates the size of the wep key for this 679 MPDU. 680 681 682 683 <enum 0 wep_varied_width_40> WEP 40-bit 684 685 <enum 1 wep_varied_width_104> WEP 104-bit 686 687 <enum 2 wep_varied_width_128> WEP 128-bit 688 689 690 691 <legal 0-2> 692 693 mesh_sta 694 695 In case of ndp or phy_err or AST_based_lookup_valid == 696 0, this field will be set to 0 697 698 699 700 When set, this is a Mesh (11s) STA 701 702 <legal all> 703 704 bssid_hit 705 706 In case of ndp or phy_err or AST_based_lookup_valid == 707 0, this field will be set to 0 708 709 710 711 When set, the BSSID of the incoming frame matched one of 712 the 8 BSSID register values 713 714 715 716 <legal all> 717 718 bssid_number 719 720 Field only valid when bssid_hit is set. 721 722 723 724 This number indicates which one out of the 8 BSSID 725 register values matched the incoming frame 726 727 <legal all> 728 729 tid 730 731 Field only valid when mpdu_qos_control_valid is set 732 733 734 735 The TID field in the QoS control field 736 737 <legal all> 738 739 reserved_3a 740 741 <legal 0> 742 743 pn_31_0 744 745 746 747 748 749 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 750 is valid. 751 752 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 753 WEPSeed[1], pn1}. Only pn[47:0] is valid. 754 755 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 756 pn1, pn0}. Only pn[47:0] is valid. 757 758 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 759 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 760 pn0}. pn[127:0] are valid. 761 762 763 764 765 pn_63_32 766 767 768 769 770 Bits [63:32] of the PN number. See description for 771 pn_31_0. 772 773 774 775 776 pn_95_64 777 778 779 780 781 Bits [95:64] of the PN number. See description for 782 pn_31_0. 783 784 785 786 787 pn_127_96 788 789 790 791 792 Bits [127:96] of the PN number. See description for 793 pn_31_0. 794 795 796 797 798 peer_meta_data 799 800 In case of ndp or phy_err or AST_based_lookup_valid == 801 0, this field will be set to 0 802 803 804 805 Meta data that SW has programmed in the Peer table entry 806 of the transmitting STA. 807 808 <legal all> 809 810 struct rxpt_classify_info rxpt_classify_info_details 811 812 In case of ndp or phy_err or AST_based_lookup_valid == 813 0, this field will be set to 0 814 815 816 817 RXOLE related classification info 818 819 <legal all 820 821 rx_reo_queue_desc_addr_31_0 822 823 In case of ndp or phy_err or AST_based_lookup_valid == 824 0, this field will be set to 0 825 826 827 828 Address (lower 32 bits) of the REO queue descriptor. 829 830 831 832 If no Peer entry lookup happened for this frame, the 833 value wil be set to 0, and the frame shall never be pushed 834 to REO entrance ring. 835 836 <legal all> 837 838 rx_reo_queue_desc_addr_39_32 839 840 In case of ndp or phy_err or AST_based_lookup_valid == 841 0, this field will be set to 0 842 843 844 845 Address (upper 8 bits) of the REO queue descriptor. 846 847 848 849 If no Peer entry lookup happened for this frame, the 850 value wil be set to 0, and the frame shall never be pushed 851 to REO entrance ring. 852 853 <legal all> 854 855 receive_queue_number 856 857 In case of ndp or phy_err or AST_based_lookup_valid == 858 0, this field will be set to 0 859 860 861 862 Indicates the MPDU queue ID to which this MPDU link 863 descriptor belongs 864 865 Used for tracking and debugging 866 867 <legal all> 868 869 pre_delim_err_warning 870 871 Indicates that a delimiter FCS error was found in 872 between the Previous MPDU and this MPDU. 873 874 875 876 Note that this is just a warning, and does not mean that 877 this MPDU is corrupted in any way. If it is, there will be 878 other errors indicated such as FCS or decrypt errors 879 880 881 882 In case of ndp or phy_err, this field will indicate at 883 least one of delimiters located after the last MPDU in the 884 previous PPDU has been corrupted. 885 886 first_delim_err 887 888 Indicates that the first delimiter had a FCS failure. 889 Only valid when first_mpdu and first_msdu are set. 890 891 892 893 894 reserved_11 895 896 <legal 0> 897 898 key_id_octet 899 900 901 902 903 The key ID octet from the IV. 904 905 906 907 In case of ndp or phy_err or AST_based_lookup_valid == 908 0, this field will be set to 0 909 910 <legal all> 911 912 new_peer_entry 913 914 In case of ndp or phy_err or AST_based_lookup_valid == 915 0, this field will be set to 0 916 917 918 919 Set if new RX_PEER_ENTRY TLV follows. If clear, 920 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 921 uses old peer entry or not decrypt. 922 923 <legal all> 924 925 decrypt_needed 926 927 In case of ndp or phy_err or AST_based_lookup_valid == 928 0, this field will be set to 0 929 930 931 932 Set if decryption is needed. 933 934 935 936 Note: 937 938 When RXPCU sets bit 'ast_index_not_found' and/or 939 ast_index_timeout', RXPCU will also ensure that this bit is 940 NOT set 941 942 CRYPTO for that reason only needs to evaluate this bit 943 and non of the other ones. 944 945 <legal all> 946 947 decap_type 948 949 In case of ndp or phy_err or AST_based_lookup_valid == 950 0, this field will be set to 0 951 952 953 954 Used by the OLE during decapsulation. 955 956 957 958 Indicates the decapsulation that HW will perform: 959 960 961 962 <enum 0 RAW> No encapsulation 963 964 <enum 1 Native_WiFi> 965 966 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 967 SNAP/LLC) 968 969 <enum 3 802_3> Indicate Ethernet 970 971 972 973 <legal all> 974 975 rx_insert_vlan_c_tag_padding 976 977 In case of ndp or phy_err or AST_based_lookup_valid == 978 0, this field will be set to 0 979 980 981 982 Insert 4 byte of all zeros as VLAN tag if the rx payload 983 does not have VLAN. Used during decapsulation. 984 985 <legal all> 986 987 rx_insert_vlan_s_tag_padding 988 989 In case of ndp or phy_err or AST_based_lookup_valid == 990 0, this field will be set to 0 991 992 993 994 Insert 4 byte of all zeros as double VLAN tag if the rx 995 payload does not have VLAN. Used during 996 997 <legal all> 998 999 strip_vlan_c_tag_decap 1000 1001 In case of ndp or phy_err or AST_based_lookup_valid == 1002 0, this field will be set to 0 1003 1004 1005 1006 Strip the VLAN during decapsulation. Used by the OLE. 1007 1008 <legal all> 1009 1010 strip_vlan_s_tag_decap 1011 1012 In case of ndp or phy_err or AST_based_lookup_valid == 1013 0, this field will be set to 0 1014 1015 1016 1017 Strip the double VLAN during decapsulation. Used by 1018 the OLE. 1019 1020 <legal all> 1021 1022 pre_delim_count 1023 1024 The number of delimiters before this MPDU. 1025 1026 1027 1028 Note that this number is cleared at PPDU start. 1029 1030 1031 1032 If this MPDU is the first received MPDU in the PPDU and 1033 this MPDU gets filtered-in, this field will indicate the 1034 number of delimiters located after the last MPDU in the 1035 previous PPDU. 1036 1037 1038 1039 If this MPDU is located after the first received MPDU in 1040 an PPDU, this field will indicate the number of delimiters 1041 located between the previous MPDU and this MPDU. 1042 1043 1044 1045 In case of ndp or phy_err, this field will indicate the 1046 number of delimiters located after the last MPDU in the 1047 previous PPDU. 1048 1049 <legal all> 1050 1051 ampdu_flag 1052 1053 When set, received frame was part of an A-MPDU. 1054 1055 1056 1057 1058 <legal all> 1059 1060 bar_frame 1061 1062 In case of ndp or phy_err or AST_based_lookup_valid == 1063 0, this field will be set to 0 1064 1065 1066 1067 When set, received frame is a BAR frame 1068 1069 <legal all> 1070 1071 reserved_12 1072 1073 <legal 0>. 1074 1075 mpdu_length 1076 1077 In case of ndp or phy_err this field will be set to 0 1078 1079 1080 1081 MPDU length before decapsulation. 1082 1083 <legal all> 1084 1085 first_mpdu 1086 1087 See definition in RX attention descriptor 1088 1089 1090 1091 In case of ndp or phy_err, this field will be set. Note 1092 however that there will not actually be any data contents in 1093 the MPDU. 1094 1095 <legal all> 1096 1097 mcast_bcast 1098 1099 In case of ndp or phy_err or Phy_err_during_mpdu_header 1100 this field will be set to 0 1101 1102 1103 1104 See definition in RX attention descriptor 1105 1106 <legal all> 1107 1108 ast_index_not_found 1109 1110 In case of ndp or phy_err or Phy_err_during_mpdu_header 1111 this field will be set to 0 1112 1113 1114 1115 See definition in RX attention descriptor 1116 1117 <legal all> 1118 1119 ast_index_timeout 1120 1121 In case of ndp or phy_err or Phy_err_during_mpdu_header 1122 this field will be set to 0 1123 1124 1125 1126 See definition in RX attention descriptor 1127 1128 <legal all> 1129 1130 power_mgmt 1131 1132 In case of ndp or phy_err or Phy_err_during_mpdu_header 1133 this field will be set to 0 1134 1135 1136 1137 See definition in RX attention descriptor 1138 1139 <legal all> 1140 1141 non_qos 1142 1143 In case of ndp or phy_err or Phy_err_during_mpdu_header 1144 this field will be set to 1 1145 1146 1147 1148 See definition in RX attention descriptor 1149 1150 <legal all> 1151 1152 null_data 1153 1154 In case of ndp or phy_err or Phy_err_during_mpdu_header 1155 this field will be set to 0 1156 1157 1158 1159 See definition in RX attention descriptor 1160 1161 <legal all> 1162 1163 mgmt_type 1164 1165 In case of ndp or phy_err or Phy_err_during_mpdu_header 1166 this field will be set to 0 1167 1168 1169 1170 See definition in RX attention descriptor 1171 1172 <legal all> 1173 1174 ctrl_type 1175 1176 In case of ndp or phy_err or Phy_err_during_mpdu_header 1177 this field will be set to 0 1178 1179 1180 1181 See definition in RX attention descriptor 1182 1183 <legal all> 1184 1185 more_data 1186 1187 In case of ndp or phy_err or Phy_err_during_mpdu_header 1188 this field will be set to 0 1189 1190 1191 1192 See definition in RX attention descriptor 1193 1194 <legal all> 1195 1196 eosp 1197 1198 In case of ndp or phy_err or Phy_err_during_mpdu_header 1199 this field will be set to 0 1200 1201 1202 1203 See definition in RX attention descriptor 1204 1205 <legal all> 1206 1207 fragment_flag 1208 1209 In case of ndp or phy_err or Phy_err_during_mpdu_header 1210 this field will be set to 0 1211 1212 1213 1214 See definition in RX attention descriptor 1215 1216 <legal all> 1217 1218 order 1219 1220 In case of ndp or phy_err or Phy_err_during_mpdu_header 1221 this field will be set to 0 1222 1223 1224 1225 See definition in RX attention descriptor 1226 1227 1228 1229 <legal all> 1230 1231 u_apsd_trigger 1232 1233 In case of ndp or phy_err or Phy_err_during_mpdu_header 1234 this field will be set to 0 1235 1236 1237 1238 See definition in RX attention descriptor 1239 1240 <legal all> 1241 1242 encrypt_required 1243 1244 In case of ndp or phy_err or Phy_err_during_mpdu_header 1245 this field will be set to 0 1246 1247 1248 1249 See definition in RX attention descriptor 1250 1251 <legal all> 1252 1253 directed 1254 1255 In case of ndp or phy_err or Phy_err_during_mpdu_header 1256 this field will be set to 0 1257 1258 1259 1260 See definition in RX attention descriptor 1261 1262 <legal all> 1263 1264 amsdu_present 1265 1266 Field only valid when Mpdu_qos_control_valid is set 1267 1268 1269 1270 The 'amsdu_present' bit within the QoS control field of 1271 the MPDU 1272 1273 <legal all> 1274 1275 reserved_13 1276 1277 <legal 0> 1278 1279 mpdu_frame_control_field 1280 1281 Field only valid when Mpdu_frame_control_valid is set 1282 1283 1284 1285 The frame control field of this received MPDU. 1286 1287 1288 1289 Field only valid when Ndp_frame and phy_err are NOT set 1290 1291 1292 1293 Bytes 0 + 1 of the received MPDU 1294 1295 <legal all> 1296 1297 mpdu_duration_field 1298 1299 Field only valid when Mpdu_duration_valid is set 1300 1301 1302 1303 The duration field of this received MPDU. 1304 1305 <legal all> 1306 1307 mac_addr_ad1_31_0 1308 1309 Field only valid when mac_addr_ad1_valid is set 1310 1311 1312 1313 The Least Significant 4 bytes of the Received Frames MAC 1314 Address AD1 1315 1316 <legal all> 1317 1318 mac_addr_ad1_47_32 1319 1320 Field only valid when mac_addr_ad1_valid is set 1321 1322 1323 1324 The 2 most significant bytes of the Received Frames MAC 1325 Address AD1 1326 1327 <legal all> 1328 1329 mac_addr_ad2_15_0 1330 1331 Field only valid when mac_addr_ad2_valid is set 1332 1333 1334 1335 The Least Significant 2 bytes of the Received Frames MAC 1336 Address AD2 1337 1338 <legal all> 1339 1340 mac_addr_ad2_47_16 1341 1342 Field only valid when mac_addr_ad2_valid is set 1343 1344 1345 1346 The 4 most significant bytes of the Received Frames MAC 1347 Address AD2 1348 1349 <legal all> 1350 1351 mac_addr_ad3_31_0 1352 1353 Field only valid when mac_addr_ad3_valid is set 1354 1355 1356 1357 The Least Significant 4 bytes of the Received Frames MAC 1358 Address AD3 1359 1360 <legal all> 1361 1362 mac_addr_ad3_47_32 1363 1364 Field only valid when mac_addr_ad3_valid is set 1365 1366 1367 1368 The 2 most significant bytes of the Received Frames MAC 1369 Address AD3 1370 1371 <legal all> 1372 1373 mpdu_sequence_control_field 1374 1375 1376 1377 1378 The sequence control field of the MPDU 1379 1380 <legal all> 1381 1382 mac_addr_ad4_31_0 1383 1384 Field only valid when mac_addr_ad4_valid is set 1385 1386 1387 1388 The Least Significant 4 bytes of the Received Frames MAC 1389 Address AD4 1390 1391 <legal all> 1392 1393 mac_addr_ad4_47_32 1394 1395 Field only valid when mac_addr_ad4_valid is set 1396 1397 1398 1399 The 2 most significant bytes of the Received Frames MAC 1400 Address AD4 1401 1402 <legal all> 1403 1404 mpdu_qos_control_field 1405 1406 Field only valid when mpdu_qos_control_valid is set 1407 1408 1409 1410 The sequence control field of the MPDU 1411 1412 <legal all> 1413 1414 mpdu_ht_control_field 1415 1416 Field only valid when mpdu_qos_control_valid is set 1417 1418 1419 1420 The HT control field of the MPDU 1421 1422 <legal all> 1423 */ 1424 1425 1426 /* Description RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY 1427 1428 Field indicates what the reason was that this MPDU frame 1429 was allowed to come into the receive path by RXPCU 1430 1431 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 1432 frame filter programming of rxpcu 1433 1434 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 1435 regular frame filter and would have been dropped, were it 1436 not for the frame fitting into the 'monitor_client' 1437 category. 1438 1439 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 1440 regular frame filter and also did not pass the 1441 rxpcu_monitor_client filter. It would have been dropped 1442 accept that it did pass the 'monitor_other' category. 1443 1444 1445 1446 Note: for ndp frame, if it was expected because the 1447 preceding NDPA was filter_pass, the setting 1448 rxpcu_filter_pass will be used. This setting will also be 1449 used for every ndp frame in case Promiscuous mode is 1450 enabled. 1451 1452 1453 1454 In case promiscuous is not enabled, and an NDP is not 1455 preceded by a NPDA filter pass frame, the only other setting 1456 that could appear here for the NDP is rxpcu_monitor_other. 1457 1458 (rxpcu has a configuration bit specifically for this 1459 scenario) 1460 1461 1462 1463 Note: for 1464 1465 <legal 0-2> 1466 */ 1467 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 1468 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1469 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 1470 1471 /* Description RX_MPDU_INFO_0_SW_FRAME_GROUP_ID 1472 1473 SW processes frames based on certain classifications. 1474 This field indicates to what sw classification this MPDU is 1475 mapped. 1476 1477 The classification is given in priority order 1478 1479 1480 1481 <enum 0 sw_frame_group_NDP_frame> Note: The 1482 corresponding Rxpcu_Mpdu_filter_in_category can be 1483 rxpcu_filter_pass or rxpcu_monitor_other 1484 1485 1486 1487 <enum 1 sw_frame_group_Multicast_data> 1488 1489 <enum 2 sw_frame_group_Unicast_data> 1490 1491 <enum 3 sw_frame_group_Null_data > This includes mpdus 1492 of type Data Null as well as QoS Data Null 1493 1494 1495 1496 <enum 4 sw_frame_group_mgmt_0000 > 1497 1498 <enum 5 sw_frame_group_mgmt_0001 > 1499 1500 <enum 6 sw_frame_group_mgmt_0010 > 1501 1502 <enum 7 sw_frame_group_mgmt_0011 > 1503 1504 <enum 8 sw_frame_group_mgmt_0100 > 1505 1506 <enum 9 sw_frame_group_mgmt_0101 > 1507 1508 <enum 10 sw_frame_group_mgmt_0110 > 1509 1510 <enum 11 sw_frame_group_mgmt_0111 > 1511 1512 <enum 12 sw_frame_group_mgmt_1000 > 1513 1514 <enum 13 sw_frame_group_mgmt_1001 > 1515 1516 <enum 14 sw_frame_group_mgmt_1010 > 1517 1518 <enum 15 sw_frame_group_mgmt_1011 > 1519 1520 <enum 16 sw_frame_group_mgmt_1100 > 1521 1522 <enum 17 sw_frame_group_mgmt_1101 > 1523 1524 <enum 18 sw_frame_group_mgmt_1110 > 1525 1526 <enum 19 sw_frame_group_mgmt_1111 > 1527 1528 1529 1530 <enum 20 sw_frame_group_ctrl_0000 > 1531 1532 <enum 21 sw_frame_group_ctrl_0001 > 1533 1534 <enum 22 sw_frame_group_ctrl_0010 > 1535 1536 <enum 23 sw_frame_group_ctrl_0011 > 1537 1538 <enum 24 sw_frame_group_ctrl_0100 > 1539 1540 <enum 25 sw_frame_group_ctrl_0101 > 1541 1542 <enum 26 sw_frame_group_ctrl_0110 > 1543 1544 <enum 27 sw_frame_group_ctrl_0111 > 1545 1546 <enum 28 sw_frame_group_ctrl_1000 > 1547 1548 <enum 29 sw_frame_group_ctrl_1001 > 1549 1550 <enum 30 sw_frame_group_ctrl_1010 > 1551 1552 <enum 31 sw_frame_group_ctrl_1011 > 1553 1554 <enum 32 sw_frame_group_ctrl_1100 > 1555 1556 <enum 33 sw_frame_group_ctrl_1101 > 1557 1558 <enum 34 sw_frame_group_ctrl_1110 > 1559 1560 <enum 35 sw_frame_group_ctrl_1111 > 1561 1562 1563 1564 <enum 36 sw_frame_group_unsupported> This covers type 3 1565 and protocol version != 0 1566 1567 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1568 can only be rxpcu_monitor_other 1569 1570 1571 1572 1573 Note: The corresponding Rxpcu_Mpdu_filter_in_category 1574 can be rxpcu_filter_pass 1575 1576 1577 1578 <legal 0-37> 1579 */ 1580 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 1581 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB 2 1582 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 1583 1584 /* Description RX_MPDU_INFO_0_NDP_FRAME 1585 1586 When set, the received frame was an NDP frame, and thus 1587 there will be no MPDU data. 1588 1589 <legal all> 1590 */ 1591 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET 0x00000000 1592 #define RX_MPDU_INFO_0_NDP_FRAME_LSB 9 1593 #define RX_MPDU_INFO_0_NDP_FRAME_MASK 0x00000200 1594 1595 /* Description RX_MPDU_INFO_0_PHY_ERR 1596 1597 When set, a PHY error was received before MAC received 1598 any data, and thus there will be no MPDU data. 1599 1600 <legal all> 1601 */ 1602 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET 0x00000000 1603 #define RX_MPDU_INFO_0_PHY_ERR_LSB 10 1604 #define RX_MPDU_INFO_0_PHY_ERR_MASK 0x00000400 1605 1606 /* Description RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER 1607 1608 When set, a PHY error was received before MAC received 1609 the complete MPDU header which was needed for proper 1610 decoding 1611 1612 <legal all> 1613 */ 1614 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000000 1615 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1616 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1617 1618 /* Description RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR 1619 1620 Set when RXPCU detected a version error in the Frame 1621 control field 1622 1623 <legal all> 1624 */ 1625 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET 0x00000000 1626 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB 12 1627 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK 0x00001000 1628 1629 /* Description RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID 1630 1631 When set, AST based lookup for this frame has found a 1632 valid result. 1633 1634 1635 1636 Note that for NDP frame this will never be set 1637 1638 <legal all> 1639 */ 1640 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET 0x00000000 1641 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB 13 1642 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1643 1644 /* Description RX_MPDU_INFO_0_RESERVED_0A 1645 1646 <legal 0> 1647 */ 1648 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET 0x00000000 1649 #define RX_MPDU_INFO_0_RESERVED_0A_LSB 14 1650 #define RX_MPDU_INFO_0_RESERVED_0A_MASK 0x0000c000 1651 1652 /* Description RX_MPDU_INFO_0_PHY_PPDU_ID 1653 1654 A ppdu counter value that PHY increments for every PPDU 1655 received. The counter value wraps around 1656 1657 <legal all> 1658 */ 1659 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 1660 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB 16 1661 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK 0xffff0000 1662 1663 /* Description RX_MPDU_INFO_1_AST_INDEX 1664 1665 This field indicates the index of the AST entry 1666 corresponding to this MPDU. It is provided by the GSE module 1667 instantiated in RXPCU. 1668 1669 A value of 0xFFFF indicates an invalid AST index, 1670 meaning that No AST entry was found or NO AST search was 1671 performed 1672 1673 1674 1675 In case of ndp or phy_err, this field will be set to 1676 0xFFFF 1677 1678 <legal all> 1679 */ 1680 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET 0x00000004 1681 #define RX_MPDU_INFO_1_AST_INDEX_LSB 0 1682 #define RX_MPDU_INFO_1_AST_INDEX_MASK 0x0000ffff 1683 1684 /* Description RX_MPDU_INFO_1_SW_PEER_ID 1685 1686 In case of ndp or phy_err or AST_based_lookup_valid == 1687 0, this field will be set to 0 1688 1689 1690 1691 This field indicates a unique peer identifier. It is set 1692 equal to field 'sw_peer_id' from the AST entry 1693 1694 1695 1696 <legal all> 1697 */ 1698 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET 0x00000004 1699 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB 16 1700 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK 0xffff0000 1701 1702 /* Description RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID 1703 1704 When set, the field Mpdu_Frame_control_field has valid 1705 information 1706 1707 1708 1709 1710 <legal all> 1711 */ 1712 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000008 1713 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB 0 1714 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1715 1716 /* Description RX_MPDU_INFO_2_MPDU_DURATION_VALID 1717 1718 When set, the field Mpdu_duration_field has valid 1719 information 1720 1721 1722 1723 1724 <legal all> 1725 */ 1726 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET 0x00000008 1727 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB 1 1728 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK 0x00000002 1729 1730 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID 1731 1732 When set, the fields mac_addr_ad1_..... have valid 1733 information 1734 1735 1736 1737 1738 <legal all> 1739 */ 1740 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET 0x00000008 1741 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB 2 1742 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK 0x00000004 1743 1744 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID 1745 1746 When set, the fields mac_addr_ad2_..... have valid 1747 information 1748 1749 1750 1751 1752 1753 1754 1755 <legal all> 1756 */ 1757 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET 0x00000008 1758 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB 3 1759 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK 0x00000008 1760 1761 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID 1762 1763 When set, the fields mac_addr_ad3_..... have valid 1764 information 1765 1766 1767 1768 1769 1770 1771 1772 <legal all> 1773 */ 1774 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET 0x00000008 1775 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB 4 1776 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK 0x00000010 1777 1778 /* Description RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID 1779 1780 When set, the fields mac_addr_ad4_..... have valid 1781 information 1782 1783 1784 1785 1786 1787 1788 1789 <legal all> 1790 */ 1791 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET 0x00000008 1792 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB 5 1793 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK 0x00000020 1794 1795 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID 1796 1797 When set, the fields mpdu_sequence_control_field and 1798 mpdu_sequence_number have valid information as well as field 1799 1800 1801 1802 For MPDUs without a sequence control field, this field 1803 will not be set. 1804 1805 1806 1807 1808 <legal all> 1809 */ 1810 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000008 1811 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1812 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1813 1814 /* Description RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID 1815 1816 When set, the field mpdu_qos_control_field has valid 1817 information 1818 1819 1820 1821 For MPDUs without a QoS control field, this field will 1822 not be set. 1823 1824 1825 1826 1827 <legal all> 1828 */ 1829 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 1830 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB 7 1831 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1832 1833 /* Description RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID 1834 1835 When set, the field mpdu_HT_control_field has valid 1836 information 1837 1838 1839 1840 For MPDUs without a HT control field, this field will 1841 not be set. 1842 1843 1844 1845 1846 <legal all> 1847 */ 1848 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET 0x00000008 1849 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB 8 1850 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1851 1852 /* Description RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID 1853 1854 When set, the encryption related info fields, like IV 1855 and PN are valid 1856 1857 1858 1859 For MPDUs that are not encrypted, this will not be set. 1860 1861 1862 1863 1864 <legal all> 1865 */ 1866 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000008 1867 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1868 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1869 1870 /* Description RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER 1871 1872 Field only valid when Mpdu_sequence_control_valid is set 1873 AND Fragment_flag is set 1874 1875 1876 1877 The fragment number from the 802.11 header 1878 1879 1880 1881 <legal all> 1882 */ 1883 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000008 1884 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_LSB 10 1885 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1886 1887 /* Description RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG 1888 1889 The More Fragment bit setting from the MPDU header of 1890 the received frame 1891 1892 1893 1894 <legal all> 1895 */ 1896 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 1897 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_LSB 14 1898 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_MASK 0x00004000 1899 1900 /* Description RX_MPDU_INFO_2_RESERVED_2A 1901 1902 <legal 0> 1903 */ 1904 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 1905 #define RX_MPDU_INFO_2_RESERVED_2A_LSB 15 1906 #define RX_MPDU_INFO_2_RESERVED_2A_MASK 0x00008000 1907 1908 /* Description RX_MPDU_INFO_2_FR_DS 1909 1910 Field only valid when Mpdu_frame_control_valid is set 1911 1912 1913 1914 Set if the from DS bit is set in the frame control. 1915 1916 <legal all> 1917 */ 1918 #define RX_MPDU_INFO_2_FR_DS_OFFSET 0x00000008 1919 #define RX_MPDU_INFO_2_FR_DS_LSB 16 1920 #define RX_MPDU_INFO_2_FR_DS_MASK 0x00010000 1921 1922 /* Description RX_MPDU_INFO_2_TO_DS 1923 1924 Field only valid when Mpdu_frame_control_valid is set 1925 1926 1927 1928 Set if the to DS bit is set in the frame control. 1929 1930 <legal all> 1931 */ 1932 #define RX_MPDU_INFO_2_TO_DS_OFFSET 0x00000008 1933 #define RX_MPDU_INFO_2_TO_DS_LSB 17 1934 #define RX_MPDU_INFO_2_TO_DS_MASK 0x00020000 1935 1936 /* Description RX_MPDU_INFO_2_ENCRYPTED 1937 1938 Field only valid when Mpdu_frame_control_valid is set. 1939 1940 1941 1942 Protected bit from the frame control. 1943 1944 <legal all> 1945 */ 1946 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET 0x00000008 1947 #define RX_MPDU_INFO_2_ENCRYPTED_LSB 18 1948 #define RX_MPDU_INFO_2_ENCRYPTED_MASK 0x00040000 1949 1950 /* Description RX_MPDU_INFO_2_MPDU_RETRY 1951 1952 Field only valid when Mpdu_frame_control_valid is set. 1953 1954 1955 1956 Retry bit from the frame control. Only valid when 1957 first_msdu is set. 1958 1959 <legal all> 1960 */ 1961 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET 0x00000008 1962 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB 19 1963 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK 0x00080000 1964 1965 /* Description RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER 1966 1967 Field only valid when Mpdu_sequence_control_valid is 1968 set. 1969 1970 1971 1972 The sequence number from the 802.11 header. 1973 1974 <legal all> 1975 */ 1976 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 1977 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB 20 1978 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1979 1980 /* Description RX_MPDU_INFO_3_EPD_EN 1981 1982 Field only valid when AST_based_lookup_valid == 1. 1983 1984 1985 1986 1987 1988 In case of ndp or phy_err or AST_based_lookup_valid == 1989 0, this field will be set to 0 1990 1991 1992 1993 If set to one use EPD instead of LPD 1994 1995 1996 1997 1998 <legal all> 1999 */ 2000 #define RX_MPDU_INFO_3_EPD_EN_OFFSET 0x0000000c 2001 #define RX_MPDU_INFO_3_EPD_EN_LSB 0 2002 #define RX_MPDU_INFO_3_EPD_EN_MASK 0x00000001 2003 2004 /* Description RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED 2005 2006 In case of ndp or phy_err or AST_based_lookup_valid == 2007 0, this field will be set to 0 2008 2009 2010 2011 When set, all frames (data only ?) shall be encrypted. 2012 If not, RX CRYPTO shall set an error flag. 2013 2014 <legal all> 2015 */ 2016 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000c 2017 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 2018 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 2019 2020 /* Description RX_MPDU_INFO_3_ENCRYPT_TYPE 2021 2022 In case of ndp or phy_err or AST_based_lookup_valid == 2023 0, this field will be set to 0 2024 2025 2026 2027 Indicates type of decrypt cipher used (as defined in the 2028 peer entry) 2029 2030 2031 2032 <enum 0 wep_40> WEP 40-bit 2033 2034 <enum 1 wep_104> WEP 104-bit 2035 2036 <enum 2 tkip_no_mic> TKIP without MIC 2037 2038 <enum 3 wep_128> WEP 128-bit 2039 2040 <enum 4 tkip_with_mic> TKIP with MIC 2041 2042 <enum 5 wapi> WAPI 2043 2044 <enum 6 aes_ccmp_128> AES CCMP 128 2045 2046 <enum 7 no_cipher> No crypto 2047 2048 <enum 8 aes_ccmp_256> AES CCMP 256 2049 2050 <enum 9 aes_gcmp_128> AES CCMP 128 2051 2052 <enum 10 aes_gcmp_256> AES CCMP 256 2053 2054 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 2055 2056 2057 2058 <enum 12 wep_varied_width> WEP encryption. As for WEP 2059 per keyid the key bit width can vary, the key bit width for 2060 this MPDU will be indicated in field 2061 wep_key_width_for_variable key 2062 2063 <legal 0-12> 2064 */ 2065 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET 0x0000000c 2066 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB 2 2067 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK 0x0000003c 2068 2069 /* Description RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY 2070 2071 Field only valid when key_type is set to 2072 wep_varied_width. 2073 2074 2075 2076 This field indicates the size of the wep key for this 2077 MPDU. 2078 2079 2080 2081 <enum 0 wep_varied_width_40> WEP 40-bit 2082 2083 <enum 1 wep_varied_width_104> WEP 104-bit 2084 2085 <enum 2 wep_varied_width_128> WEP 128-bit 2086 2087 2088 2089 <legal 0-2> 2090 */ 2091 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000c 2092 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 2093 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 2094 2095 /* Description RX_MPDU_INFO_3_MESH_STA 2096 2097 In case of ndp or phy_err or AST_based_lookup_valid == 2098 0, this field will be set to 0 2099 2100 2101 2102 When set, this is a Mesh (11s) STA 2103 2104 <legal all> 2105 */ 2106 #define RX_MPDU_INFO_3_MESH_STA_OFFSET 0x0000000c 2107 #define RX_MPDU_INFO_3_MESH_STA_LSB 8 2108 #define RX_MPDU_INFO_3_MESH_STA_MASK 0x00000100 2109 2110 /* Description RX_MPDU_INFO_3_BSSID_HIT 2111 2112 In case of ndp or phy_err or AST_based_lookup_valid == 2113 0, this field will be set to 0 2114 2115 2116 2117 When set, the BSSID of the incoming frame matched one of 2118 the 8 BSSID register values 2119 2120 2121 2122 <legal all> 2123 */ 2124 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET 0x0000000c 2125 #define RX_MPDU_INFO_3_BSSID_HIT_LSB 9 2126 #define RX_MPDU_INFO_3_BSSID_HIT_MASK 0x00000200 2127 2128 /* Description RX_MPDU_INFO_3_BSSID_NUMBER 2129 2130 Field only valid when bssid_hit is set. 2131 2132 2133 2134 This number indicates which one out of the 8 BSSID 2135 register values matched the incoming frame 2136 2137 <legal all> 2138 */ 2139 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET 0x0000000c 2140 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB 10 2141 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK 0x00003c00 2142 2143 /* Description RX_MPDU_INFO_3_TID 2144 2145 Field only valid when mpdu_qos_control_valid is set 2146 2147 2148 2149 The TID field in the QoS control field 2150 2151 <legal all> 2152 */ 2153 #define RX_MPDU_INFO_3_TID_OFFSET 0x0000000c 2154 #define RX_MPDU_INFO_3_TID_LSB 14 2155 #define RX_MPDU_INFO_3_TID_MASK 0x0003c000 2156 2157 /* Description RX_MPDU_INFO_3_RESERVED_3A 2158 2159 <legal 0> 2160 */ 2161 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET 0x0000000c 2162 #define RX_MPDU_INFO_3_RESERVED_3A_LSB 18 2163 #define RX_MPDU_INFO_3_RESERVED_3A_MASK 0xfffc0000 2164 2165 /* Description RX_MPDU_INFO_4_PN_31_0 2166 2167 2168 2169 2170 2171 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 2172 is valid. 2173 2174 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 2175 WEPSeed[1], pn1}. Only pn[47:0] is valid. 2176 2177 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, 2178 pn1, pn0}. Only pn[47:0] is valid. 2179 2180 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, 2181 pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, 2182 pn0}. pn[127:0] are valid. 2183 2184 2185 2186 */ 2187 #define RX_MPDU_INFO_4_PN_31_0_OFFSET 0x00000010 2188 #define RX_MPDU_INFO_4_PN_31_0_LSB 0 2189 #define RX_MPDU_INFO_4_PN_31_0_MASK 0xffffffff 2190 2191 /* Description RX_MPDU_INFO_5_PN_63_32 2192 2193 2194 2195 2196 Bits [63:32] of the PN number. See description for 2197 pn_31_0. 2198 2199 2200 2201 */ 2202 #define RX_MPDU_INFO_5_PN_63_32_OFFSET 0x00000014 2203 #define RX_MPDU_INFO_5_PN_63_32_LSB 0 2204 #define RX_MPDU_INFO_5_PN_63_32_MASK 0xffffffff 2205 2206 /* Description RX_MPDU_INFO_6_PN_95_64 2207 2208 2209 2210 2211 Bits [95:64] of the PN number. See description for 2212 pn_31_0. 2213 2214 2215 2216 */ 2217 #define RX_MPDU_INFO_6_PN_95_64_OFFSET 0x00000018 2218 #define RX_MPDU_INFO_6_PN_95_64_LSB 0 2219 #define RX_MPDU_INFO_6_PN_95_64_MASK 0xffffffff 2220 2221 /* Description RX_MPDU_INFO_7_PN_127_96 2222 2223 2224 2225 2226 Bits [127:96] of the PN number. See description for 2227 pn_31_0. 2228 2229 2230 2231 */ 2232 #define RX_MPDU_INFO_7_PN_127_96_OFFSET 0x0000001c 2233 #define RX_MPDU_INFO_7_PN_127_96_LSB 0 2234 #define RX_MPDU_INFO_7_PN_127_96_MASK 0xffffffff 2235 2236 /* Description RX_MPDU_INFO_8_PEER_META_DATA 2237 2238 In case of ndp or phy_err or AST_based_lookup_valid == 2239 0, this field will be set to 0 2240 2241 2242 2243 Meta data that SW has programmed in the Peer table entry 2244 of the transmitting STA. 2245 2246 <legal all> 2247 */ 2248 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 2249 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 2250 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff 2251 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024 2252 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0 2253 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff 2254 2255 /* Description RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0 2256 2257 In case of ndp or phy_err or AST_based_lookup_valid == 2258 0, this field will be set to 0 2259 2260 2261 2262 Address (lower 32 bits) of the REO queue descriptor. 2263 2264 2265 2266 If no Peer entry lookup happened for this frame, the 2267 value wil be set to 0, and the frame shall never be pushed 2268 to REO entrance ring. 2269 2270 <legal all> 2271 */ 2272 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000028 2273 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 2274 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 2275 2276 /* Description RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32 2277 2278 In case of ndp or phy_err or AST_based_lookup_valid == 2279 0, this field will be set to 0 2280 2281 2282 2283 Address (upper 8 bits) of the REO queue descriptor. 2284 2285 2286 2287 If no Peer entry lookup happened for this frame, the 2288 value wil be set to 0, and the frame shall never be pushed 2289 to REO entrance ring. 2290 2291 <legal all> 2292 */ 2293 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000002c 2294 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 2295 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 2296 2297 /* Description RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER 2298 2299 In case of ndp or phy_err or AST_based_lookup_valid == 2300 0, this field will be set to 0 2301 2302 2303 2304 Indicates the MPDU queue ID to which this MPDU link 2305 descriptor belongs 2306 2307 Used for tracking and debugging 2308 2309 <legal all> 2310 */ 2311 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000002c 2312 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB 8 2313 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 2314 2315 /* Description RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING 2316 2317 Indicates that a delimiter FCS error was found in 2318 between the Previous MPDU and this MPDU. 2319 2320 2321 2322 Note that this is just a warning, and does not mean that 2323 this MPDU is corrupted in any way. If it is, there will be 2324 other errors indicated such as FCS or decrypt errors 2325 2326 2327 2328 In case of ndp or phy_err, this field will indicate at 2329 least one of delimiters located after the last MPDU in the 2330 previous PPDU has been corrupted. 2331 */ 2332 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET 0x0000002c 2333 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB 24 2334 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK 0x01000000 2335 2336 /* Description RX_MPDU_INFO_11_FIRST_DELIM_ERR 2337 2338 Indicates that the first delimiter had a FCS failure. 2339 Only valid when first_mpdu and first_msdu are set. 2340 2341 2342 2343 */ 2344 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET 0x0000002c 2345 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB 25 2346 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK 0x02000000 2347 2348 /* Description RX_MPDU_INFO_11_RESERVED_11 2349 2350 <legal 0> 2351 */ 2352 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET 0x0000002c 2353 #define RX_MPDU_INFO_11_RESERVED_11_LSB 26 2354 #define RX_MPDU_INFO_11_RESERVED_11_MASK 0xfc000000 2355 2356 /* Description RX_MPDU_INFO_12_KEY_ID_OCTET 2357 2358 2359 2360 2361 The key ID octet from the IV. 2362 2363 2364 2365 In case of ndp or phy_err or AST_based_lookup_valid == 2366 0, this field will be set to 0 2367 2368 <legal all> 2369 */ 2370 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 2371 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 2372 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff 2373 2374 /* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY 2375 2376 In case of ndp or phy_err or AST_based_lookup_valid == 2377 0, this field will be set to 0 2378 2379 2380 2381 Set if new RX_PEER_ENTRY TLV follows. If clear, 2382 RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either 2383 uses old peer entry or not decrypt. 2384 2385 <legal all> 2386 */ 2387 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 2388 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 2389 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 2390 2391 /* Description RX_MPDU_INFO_12_DECRYPT_NEEDED 2392 2393 In case of ndp or phy_err or AST_based_lookup_valid == 2394 0, this field will be set to 0 2395 2396 2397 2398 Set if decryption is needed. 2399 2400 2401 2402 Note: 2403 2404 When RXPCU sets bit 'ast_index_not_found' and/or 2405 ast_index_timeout', RXPCU will also ensure that this bit is 2406 NOT set 2407 2408 CRYPTO for that reason only needs to evaluate this bit 2409 and non of the other ones. 2410 2411 <legal all> 2412 */ 2413 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 2414 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 2415 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 2416 2417 /* Description RX_MPDU_INFO_12_DECAP_TYPE 2418 2419 In case of ndp or phy_err or AST_based_lookup_valid == 2420 0, this field will be set to 0 2421 2422 2423 2424 Used by the OLE during decapsulation. 2425 2426 2427 2428 Indicates the decapsulation that HW will perform: 2429 2430 2431 2432 <enum 0 RAW> No encapsulation 2433 2434 <enum 1 Native_WiFi> 2435 2436 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses 2437 SNAP/LLC) 2438 2439 <enum 3 802_3> Indicate Ethernet 2440 2441 2442 2443 <legal all> 2444 */ 2445 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 2446 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 2447 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 2448 2449 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING 2450 2451 In case of ndp or phy_err or AST_based_lookup_valid == 2452 0, this field will be set to 0 2453 2454 2455 2456 Insert 4 byte of all zeros as VLAN tag if the rx payload 2457 does not have VLAN. Used during decapsulation. 2458 2459 <legal all> 2460 */ 2461 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 2462 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 2463 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 2464 2465 /* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING 2466 2467 In case of ndp or phy_err or AST_based_lookup_valid == 2468 0, this field will be set to 0 2469 2470 2471 2472 Insert 4 byte of all zeros as double VLAN tag if the rx 2473 payload does not have VLAN. Used during 2474 2475 <legal all> 2476 */ 2477 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 2478 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 2479 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 2480 2481 /* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP 2482 2483 In case of ndp or phy_err or AST_based_lookup_valid == 2484 0, this field will be set to 0 2485 2486 2487 2488 Strip the VLAN during decapsulation. Used by the OLE. 2489 2490 <legal all> 2491 */ 2492 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 2493 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 2494 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 2495 2496 /* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP 2497 2498 In case of ndp or phy_err or AST_based_lookup_valid == 2499 0, this field will be set to 0 2500 2501 2502 2503 Strip the double VLAN during decapsulation. Used by 2504 the OLE. 2505 2506 <legal all> 2507 */ 2508 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 2509 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 2510 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 2511 2512 /* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT 2513 2514 The number of delimiters before this MPDU. 2515 2516 2517 2518 Note that this number is cleared at PPDU start. 2519 2520 2521 2522 If this MPDU is the first received MPDU in the PPDU and 2523 this MPDU gets filtered-in, this field will indicate the 2524 number of delimiters located after the last MPDU in the 2525 previous PPDU. 2526 2527 2528 2529 If this MPDU is located after the first received MPDU in 2530 an PPDU, this field will indicate the number of delimiters 2531 located between the previous MPDU and this MPDU. 2532 2533 2534 2535 In case of ndp or phy_err, this field will indicate the 2536 number of delimiters located after the last MPDU in the 2537 previous PPDU. 2538 2539 <legal all> 2540 */ 2541 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 2542 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 2543 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 2544 2545 /* Description RX_MPDU_INFO_12_AMPDU_FLAG 2546 2547 When set, received frame was part of an A-MPDU. 2548 2549 2550 2551 2552 <legal all> 2553 */ 2554 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 2555 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 2556 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 2557 2558 /* Description RX_MPDU_INFO_12_BAR_FRAME 2559 2560 In case of ndp or phy_err or AST_based_lookup_valid == 2561 0, this field will be set to 0 2562 2563 2564 2565 When set, received frame is a BAR frame 2566 2567 <legal all> 2568 */ 2569 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 2570 #define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 2571 #define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 2572 2573 /* Description RX_MPDU_INFO_12_RESERVED_12 2574 2575 <legal 0>. 2576 */ 2577 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 2578 #define RX_MPDU_INFO_12_RESERVED_12_LSB 30 2579 #define RX_MPDU_INFO_12_RESERVED_12_MASK 0xc0000000 2580 2581 /* Description RX_MPDU_INFO_13_MPDU_LENGTH 2582 2583 In case of ndp or phy_err this field will be set to 0 2584 2585 2586 2587 MPDU length before decapsulation. 2588 2589 <legal all> 2590 */ 2591 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 2592 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 2593 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff 2594 2595 /* Description RX_MPDU_INFO_13_FIRST_MPDU 2596 2597 See definition in RX attention descriptor 2598 2599 2600 2601 In case of ndp or phy_err, this field will be set. Note 2602 however that there will not actually be any data contents in 2603 the MPDU. 2604 2605 <legal all> 2606 */ 2607 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 2608 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 2609 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 2610 2611 /* Description RX_MPDU_INFO_13_MCAST_BCAST 2612 2613 In case of ndp or phy_err or Phy_err_during_mpdu_header 2614 this field will be set to 0 2615 2616 2617 2618 See definition in RX attention descriptor 2619 2620 <legal all> 2621 */ 2622 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 2623 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 2624 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 2625 2626 /* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND 2627 2628 In case of ndp or phy_err or Phy_err_during_mpdu_header 2629 this field will be set to 0 2630 2631 2632 2633 See definition in RX attention descriptor 2634 2635 <legal all> 2636 */ 2637 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 2638 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 2639 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 2640 2641 /* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT 2642 2643 In case of ndp or phy_err or Phy_err_during_mpdu_header 2644 this field will be set to 0 2645 2646 2647 2648 See definition in RX attention descriptor 2649 2650 <legal all> 2651 */ 2652 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 2653 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 2654 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 2655 2656 /* Description RX_MPDU_INFO_13_POWER_MGMT 2657 2658 In case of ndp or phy_err or Phy_err_during_mpdu_header 2659 this field will be set to 0 2660 2661 2662 2663 See definition in RX attention descriptor 2664 2665 <legal all> 2666 */ 2667 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 2668 #define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 2669 #define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 2670 2671 /* Description RX_MPDU_INFO_13_NON_QOS 2672 2673 In case of ndp or phy_err or Phy_err_during_mpdu_header 2674 this field will be set to 1 2675 2676 2677 2678 See definition in RX attention descriptor 2679 2680 <legal all> 2681 */ 2682 #define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 2683 #define RX_MPDU_INFO_13_NON_QOS_LSB 19 2684 #define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 2685 2686 /* Description RX_MPDU_INFO_13_NULL_DATA 2687 2688 In case of ndp or phy_err or Phy_err_during_mpdu_header 2689 this field will be set to 0 2690 2691 2692 2693 See definition in RX attention descriptor 2694 2695 <legal all> 2696 */ 2697 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 2698 #define RX_MPDU_INFO_13_NULL_DATA_LSB 20 2699 #define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 2700 2701 /* Description RX_MPDU_INFO_13_MGMT_TYPE 2702 2703 In case of ndp or phy_err or Phy_err_during_mpdu_header 2704 this field will be set to 0 2705 2706 2707 2708 See definition in RX attention descriptor 2709 2710 <legal all> 2711 */ 2712 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 2713 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 2714 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 2715 2716 /* Description RX_MPDU_INFO_13_CTRL_TYPE 2717 2718 In case of ndp or phy_err or Phy_err_during_mpdu_header 2719 this field will be set to 0 2720 2721 2722 2723 See definition in RX attention descriptor 2724 2725 <legal all> 2726 */ 2727 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 2728 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 2729 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 2730 2731 /* Description RX_MPDU_INFO_13_MORE_DATA 2732 2733 In case of ndp or phy_err or Phy_err_during_mpdu_header 2734 this field will be set to 0 2735 2736 2737 2738 See definition in RX attention descriptor 2739 2740 <legal all> 2741 */ 2742 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 2743 #define RX_MPDU_INFO_13_MORE_DATA_LSB 23 2744 #define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 2745 2746 /* Description RX_MPDU_INFO_13_EOSP 2747 2748 In case of ndp or phy_err or Phy_err_during_mpdu_header 2749 this field will be set to 0 2750 2751 2752 2753 See definition in RX attention descriptor 2754 2755 <legal all> 2756 */ 2757 #define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 2758 #define RX_MPDU_INFO_13_EOSP_LSB 24 2759 #define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 2760 2761 /* Description RX_MPDU_INFO_13_FRAGMENT_FLAG 2762 2763 In case of ndp or phy_err or Phy_err_during_mpdu_header 2764 this field will be set to 0 2765 2766 2767 2768 See definition in RX attention descriptor 2769 2770 <legal all> 2771 */ 2772 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 2773 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 2774 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 2775 2776 /* Description RX_MPDU_INFO_13_ORDER 2777 2778 In case of ndp or phy_err or Phy_err_during_mpdu_header 2779 this field will be set to 0 2780 2781 2782 2783 See definition in RX attention descriptor 2784 2785 2786 2787 <legal all> 2788 */ 2789 #define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 2790 #define RX_MPDU_INFO_13_ORDER_LSB 26 2791 #define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 2792 2793 /* Description RX_MPDU_INFO_13_U_APSD_TRIGGER 2794 2795 In case of ndp or phy_err or Phy_err_during_mpdu_header 2796 this field will be set to 0 2797 2798 2799 2800 See definition in RX attention descriptor 2801 2802 <legal all> 2803 */ 2804 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 2805 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 2806 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 2807 2808 /* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED 2809 2810 In case of ndp or phy_err or Phy_err_during_mpdu_header 2811 this field will be set to 0 2812 2813 2814 2815 See definition in RX attention descriptor 2816 2817 <legal all> 2818 */ 2819 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 2820 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 2821 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 2822 2823 /* Description RX_MPDU_INFO_13_DIRECTED 2824 2825 In case of ndp or phy_err or Phy_err_during_mpdu_header 2826 this field will be set to 0 2827 2828 2829 2830 See definition in RX attention descriptor 2831 2832 <legal all> 2833 */ 2834 #define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 2835 #define RX_MPDU_INFO_13_DIRECTED_LSB 29 2836 #define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 2837 2838 /* Description RX_MPDU_INFO_13_AMSDU_PRESENT 2839 2840 Field only valid when Mpdu_qos_control_valid is set 2841 2842 2843 2844 The 'amsdu_present' bit within the QoS control field of 2845 the MPDU 2846 2847 <legal all> 2848 */ 2849 #define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 2850 #define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 2851 #define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 2852 2853 /* Description RX_MPDU_INFO_13_RESERVED_13 2854 2855 <legal 0> 2856 */ 2857 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 2858 #define RX_MPDU_INFO_13_RESERVED_13_LSB 31 2859 #define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 2860 2861 /* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD 2862 2863 Field only valid when Mpdu_frame_control_valid is set 2864 2865 2866 2867 The frame control field of this received MPDU. 2868 2869 2870 2871 Field only valid when Ndp_frame and phy_err are NOT set 2872 2873 2874 2875 Bytes 0 + 1 of the received MPDU 2876 2877 <legal all> 2878 */ 2879 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2880 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 2881 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2882 2883 /* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD 2884 2885 Field only valid when Mpdu_duration_valid is set 2886 2887 2888 2889 The duration field of this received MPDU. 2890 2891 <legal all> 2892 */ 2893 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 2894 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 2895 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 2896 2897 /* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 2898 2899 Field only valid when mac_addr_ad1_valid is set 2900 2901 2902 2903 The Least Significant 4 bytes of the Received Frames MAC 2904 Address AD1 2905 2906 <legal all> 2907 */ 2908 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2909 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 2910 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2911 2912 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 2913 2914 Field only valid when mac_addr_ad1_valid is set 2915 2916 2917 2918 The 2 most significant bytes of the Received Frames MAC 2919 Address AD1 2920 2921 <legal all> 2922 */ 2923 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2924 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 2925 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2926 2927 /* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 2928 2929 Field only valid when mac_addr_ad2_valid is set 2930 2931 2932 2933 The Least Significant 2 bytes of the Received Frames MAC 2934 Address AD2 2935 2936 <legal all> 2937 */ 2938 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2939 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 2940 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2941 2942 /* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 2943 2944 Field only valid when mac_addr_ad2_valid is set 2945 2946 2947 2948 The 4 most significant bytes of the Received Frames MAC 2949 Address AD2 2950 2951 <legal all> 2952 */ 2953 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2954 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 2955 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2956 2957 /* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 2958 2959 Field only valid when mac_addr_ad3_valid is set 2960 2961 2962 2963 The Least Significant 4 bytes of the Received Frames MAC 2964 Address AD3 2965 2966 <legal all> 2967 */ 2968 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2969 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 2970 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2971 2972 /* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 2973 2974 Field only valid when mac_addr_ad3_valid is set 2975 2976 2977 2978 The 2 most significant bytes of the Received Frames MAC 2979 Address AD3 2980 2981 <legal all> 2982 */ 2983 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2984 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 2985 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2986 2987 /* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD 2988 2989 2990 2991 2992 The sequence control field of the MPDU 2993 2994 <legal all> 2995 */ 2996 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2997 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2998 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2999 3000 /* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 3001 3002 Field only valid when mac_addr_ad4_valid is set 3003 3004 3005 3006 The Least Significant 4 bytes of the Received Frames MAC 3007 Address AD4 3008 3009 <legal all> 3010 */ 3011 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 3012 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 3013 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff 3014 3015 /* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 3016 3017 Field only valid when mac_addr_ad4_valid is set 3018 3019 3020 3021 The 2 most significant bytes of the Received Frames MAC 3022 Address AD4 3023 3024 <legal all> 3025 */ 3026 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 3027 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 3028 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 3029 3030 /* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD 3031 3032 Field only valid when mpdu_qos_control_valid is set 3033 3034 3035 3036 The sequence control field of the MPDU 3037 3038 <legal all> 3039 */ 3040 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 3041 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 3042 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 3043 3044 /* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD 3045 3046 Field only valid when mpdu_qos_control_valid is set 3047 3048 3049 3050 The HT control field of the MPDU 3051 3052 <legal all> 3053 */ 3054 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 3055 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 3056 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 3057 3058 3059 #endif // _RX_MPDU_INFO_H_ 3060