1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // 20 // DO NOT EDIT! This file is automatically generated 21 // These definitions are tied to a particular hardware layout 22 23 24 #ifndef _RX_REO_QUEUE_H_ 25 #define _RX_REO_QUEUE_H_ 26 #if !defined(__ASSEMBLER__) 27 #endif 28 29 #include "uniform_descriptor_header.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_descriptor_header descriptor_header; 35 // 1 receive_queue_number[15:0], reserved_1b[31:16] 36 // 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] 37 // 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] 38 // 4 pn_31_0[31:0] 39 // 5 pn_63_32[31:0] 40 // 6 pn_95_64[31:0] 41 // 7 pn_127_96[31:0] 42 // 8 last_rx_enqueue_timestamp[31:0] 43 // 9 last_rx_dequeue_timestamp[31:0] 44 // 10 ptr_to_next_aging_queue_31_0[31:0] 45 // 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] 46 // 12 ptr_to_previous_aging_queue_31_0[31:0] 47 // 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] 48 // 14 rx_bitmap_31_0[31:0] 49 // 15 rx_bitmap_63_32[31:0] 50 // 16 rx_bitmap_95_64[31:0] 51 // 17 rx_bitmap_127_96[31:0] 52 // 18 rx_bitmap_159_128[31:0] 53 // 19 rx_bitmap_191_160[31:0] 54 // 20 rx_bitmap_223_192[31:0] 55 // 21 rx_bitmap_255_224[31:0] 56 // 22 current_mpdu_count[6:0], current_msdu_count[31:7] 57 // 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] 58 // 24 frames_in_order_count[23:0], bar_received_count[31:24] 59 // 25 mpdu_frames_processed_count[31:0] 60 // 26 msdu_frames_processed_count[31:0] 61 // 27 total_processed_byte_count[31:0] 62 // 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] 63 // 29 reserved_29[31:0] 64 // 30 reserved_30[31:0] 65 // 31 reserved_31[31:0] 66 // 67 // ################ END SUMMARY ################# 68 69 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 70 71 struct rx_reo_queue { 72 struct uniform_descriptor_header descriptor_header; 73 uint32_t receive_queue_number : 16, //[15:0] 74 reserved_1b : 16; //[31:16] 75 uint32_t vld : 1, //[0] 76 associated_link_descriptor_counter: 2, //[2:1] 77 disable_duplicate_detection : 1, //[3] 78 soft_reorder_enable : 1, //[4] 79 ac : 2, //[6:5] 80 bar : 1, //[7] 81 rty : 1, //[8] 82 chk_2k_mode : 1, //[9] 83 oor_mode : 1, //[10] 84 ba_window_size : 8, //[18:11] 85 pn_check_needed : 1, //[19] 86 pn_shall_be_even : 1, //[20] 87 pn_shall_be_uneven : 1, //[21] 88 pn_handling_enable : 1, //[22] 89 pn_size : 2, //[24:23] 90 ignore_ampdu_flag : 1, //[25] 91 reserved_2b : 6; //[31:26] 92 uint32_t svld : 1, //[0] 93 ssn : 12, //[12:1] 94 current_index : 8, //[20:13] 95 seq_2k_error_detected_flag : 1, //[21] 96 pn_error_detected_flag : 1, //[22] 97 reserved_3a : 8, //[30:23] 98 pn_valid : 1; //[31] 99 uint32_t pn_31_0 : 32; //[31:0] 100 uint32_t pn_63_32 : 32; //[31:0] 101 uint32_t pn_95_64 : 32; //[31:0] 102 uint32_t pn_127_96 : 32; //[31:0] 103 uint32_t last_rx_enqueue_timestamp : 32; //[31:0] 104 uint32_t last_rx_dequeue_timestamp : 32; //[31:0] 105 uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] 106 uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] 107 reserved_11a : 24; //[31:8] 108 uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] 109 uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] 110 reserved_13a : 24; //[31:8] 111 uint32_t rx_bitmap_31_0 : 32; //[31:0] 112 uint32_t rx_bitmap_63_32 : 32; //[31:0] 113 uint32_t rx_bitmap_95_64 : 32; //[31:0] 114 uint32_t rx_bitmap_127_96 : 32; //[31:0] 115 uint32_t rx_bitmap_159_128 : 32; //[31:0] 116 uint32_t rx_bitmap_191_160 : 32; //[31:0] 117 uint32_t rx_bitmap_223_192 : 32; //[31:0] 118 uint32_t rx_bitmap_255_224 : 32; //[31:0] 119 uint32_t current_mpdu_count : 7, //[6:0] 120 current_msdu_count : 25; //[31:7] 121 uint32_t reserved_23 : 4, //[3:0] 122 timeout_count : 6, //[9:4] 123 forward_due_to_bar_count : 6, //[15:10] 124 duplicate_count : 16; //[31:16] 125 uint32_t frames_in_order_count : 24, //[23:0] 126 bar_received_count : 8; //[31:24] 127 uint32_t mpdu_frames_processed_count : 32; //[31:0] 128 uint32_t msdu_frames_processed_count : 32; //[31:0] 129 uint32_t total_processed_byte_count : 32; //[31:0] 130 uint32_t late_receive_mpdu_count : 12, //[11:0] 131 window_jump_2k : 4, //[15:12] 132 hole_count : 16; //[31:16] 133 uint32_t reserved_29 : 32; //[31:0] 134 uint32_t reserved_30 : 32; //[31:0] 135 uint32_t reserved_31 : 32; //[31:0] 136 }; 137 138 /* 139 140 struct uniform_descriptor_header descriptor_header 141 142 Details about which module owns this struct. 143 144 Note that sub field Buffer_type shall be set to 145 Receive_REO_queue_descriptor 146 147 receive_queue_number 148 149 Indicates the MPDU queue ID to which this MPDU link 150 descriptor belongs 151 152 Used for tracking and debugging 153 154 <legal all> 155 156 reserved_1b 157 158 <legal 0> 159 160 vld 161 162 Valid bit indicating a session is established and the 163 queue descriptor is valid(Filled by SW) 164 165 <legal all> 166 167 associated_link_descriptor_counter 168 169 Indicates which of the 3 link descriptor counters shall 170 be incremented or decremented when link descriptors are 171 added or removed from this flow queue. 172 173 MSDU link descriptors related with MPDUs stored in the 174 re-order buffer shall also be included in this count. 175 176 177 178 <legal 0-2> 179 180 disable_duplicate_detection 181 182 When set, do not perform any duplicate detection. 183 184 185 186 <legal all> 187 188 soft_reorder_enable 189 190 When set, REO has been instructed to not perform the 191 actual re-ordering of frames for this queue, but just to 192 insert the reorder opcodes. 193 194 195 196 Note that this implies that REO is also not going to 197 perform any MSDU level operations, and the entire MPDU (and 198 thus pointer to the MSDU link descriptor) will be pushed to 199 a destination ring that SW has programmed in a SW 200 programmable configuration register in REO 201 202 203 204 <legal all> 205 206 ac 207 208 Indicates which access category the queue descriptor 209 belongs to(filled by SW) 210 211 <legal all> 212 213 bar 214 215 Indicates if BAR has been received (mostly used for 216 debug purpose and this is filled by REO) 217 218 <legal all> 219 220 rty 221 222 Retry bit is checked if this bit is set. 223 224 <legal all> 225 226 chk_2k_mode 227 228 Indicates what type of operation is expected from Reo 229 when the received frame SN falls within the 2K window 230 231 232 233 See REO MLD document for programming details. 234 235 <legal all> 236 237 oor_mode 238 239 Out of Order mode: 240 241 Indicates what type of operation is expected when the 242 received frame falls within the OOR window. 243 244 245 246 See REO MLD document for programming details. 247 248 <legal all> 249 250 ba_window_size 251 252 Indicates the negotiated (window size + 1). 253 254 it can go up to Max of 256bits. 255 256 257 258 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 259 (means non-BA session, with window size of 0). The 3 values 260 here are the main values validated, but other values should 261 work as well. 262 263 264 265 A BA window size of 0 (=> one frame entry bitmat), means 266 that there is NO RX_REO_QUEUE_EXT descriptor following this 267 RX_REO_QUEUE STRUCT in memory 268 269 270 271 A BA window size of 1 - 105, means that there is 1 272 RX_REO_QUEUE_EXT descriptor directly following this 273 RX_REO_QUEUE STRUCT in memory. 274 275 276 277 A BA window size of 106 - 210, means that there are 2 278 RX_REO_QUEUE_EXT descriptors directly following this 279 RX_REO_QUEUE STRUCT in memory 280 281 282 283 A BA window size of 211 - 256, means that there are 3 284 RX_REO_QUEUE_EXT descriptors directly following this 285 RX_REO_QUEUE STRUCT in memory 286 287 288 289 <legal 0 - 255> 290 291 pn_check_needed 292 293 When set, REO shall perform the PN increment check 294 295 <legal all> 296 297 pn_shall_be_even 298 299 Field only valid when 'pn_check_needed' is set. 300 301 302 303 When set, REO shall confirm that the received PN number 304 is not only incremented, but also always an even number 305 306 <legal all> 307 308 pn_shall_be_uneven 309 310 Field only valid when 'pn_check_needed' is set. 311 312 313 314 When set, REO shall confirm that the received PN number 315 is not only incremented, but also always an uneven number 316 317 <legal all> 318 319 pn_handling_enable 320 321 Field only valid when 'pn_check_needed' is set. 322 323 324 325 When set, and REO detected a PN error, HW shall set the 326 'pn_error_detected_flag'. 327 328 <legal all> 329 330 pn_size 331 332 Size of the PN field check. 333 334 Needed for wrap around handling... 335 336 337 338 <enum 0 pn_size_24> 339 340 <enum 1 pn_size_48> 341 342 <enum 2 pn_size_128> 343 344 345 346 <legal 0-2> 347 348 ignore_ampdu_flag 349 350 When set, REO shall ignore the ampdu_flag on the 351 entrance descriptor for this queue. 352 353 <legal all> 354 355 reserved_2b 356 357 <legal 0> 358 359 svld 360 361 Sequence number in next field is valid one. It can be 362 filled by SW if the want to fill in the any negotiated SSN, 363 otherwise REO will fill the sequence number of first 364 received packet and set this bit to 1. 365 366 <legal all> 367 368 ssn 369 370 Starting Sequence number of the session, this changes 371 whenever window moves. (can be filled by SW then maintained 372 by REO) 373 374 <legal all> 375 376 current_index 377 378 Points to last forwarded packet 379 380 <legal all> 381 382 seq_2k_error_detected_flag 383 384 Set by REO, can only be cleared by SW 385 386 387 388 When set, REO has detected a 2k error jump in the 389 sequence number and from that moment forward, all new frames 390 are forwarded directly to FW, without duplicate detect, 391 reordering, etc. 392 393 <legal all> 394 395 pn_error_detected_flag 396 397 Set by REO, can only be cleared by SW 398 399 400 401 When set, REO has detected a PN error and from that 402 moment forward, all new frames are forwarded directly to FW, 403 without duplicate detect, reordering, etc. 404 405 <legal all> 406 407 reserved_3a 408 409 <legal 0> 410 411 pn_valid 412 413 PN number in next fields are valid. It can be filled by 414 SW if it wants to fill in the any negotiated SSN, otherwise 415 REO will fill the pn based on the first received packet and 416 set this bit to 1. 417 418 <legal all> 419 420 pn_31_0 421 422 423 <legal all> 424 425 pn_63_32 426 427 Bits [63:32] of the PN number. 428 429 <legal all> 430 431 pn_95_64 432 433 Bits [95:64] of the PN number. 434 435 <legal all> 436 437 pn_127_96 438 439 Bits [127:96] of the PN number. 440 441 <legal all> 442 443 last_rx_enqueue_timestamp 444 445 This timestamp is updated when an MPDU is received and 446 accesses this Queue Descriptor. It does not include the 447 access due to Command TLVs or Aging (which will be updated 448 in Last_rx_dequeue_timestamp). 449 450 <legal all> 451 452 last_rx_dequeue_timestamp 453 454 This timestamp is used for Aging. When an MPDU or 455 multiple MPDUs are forwarded, either due to window movement, 456 bar, aging or command flush, this timestamp is updated. Also 457 when the bitmap is all zero and the first time an MPDU is 458 queued (opcode=QCUR), this timestamp is updated for aging. 459 460 <legal all> 461 462 ptr_to_next_aging_queue_31_0 463 464 Address (address bits 31-0)of next RX_REO_QUEUE 465 descriptor in the 'receive timestamp' ordered list. 466 467 From it the Position of this queue descriptor in the per 468 AC aging waitlist can be derived. 469 470 Value 0x0 indicates the 'NULL' pointer which implies 471 that this is the last entry in the list. 472 473 <legal all> 474 475 ptr_to_next_aging_queue_39_32 476 477 Address (address bits 39-32)of next RX_REO_QUEUE 478 descriptor in the 'receive timestamp' ordered list. 479 480 From it the Position of this queue descriptor in the per 481 AC aging waitlist can be derived. 482 483 Value 0x0 indicates the 'NULL' pointer which implies 484 that this is the last entry in the list. 485 486 <legal all> 487 488 reserved_11a 489 490 <legal 0> 491 492 ptr_to_previous_aging_queue_31_0 493 494 Address (address bits 31-0)of next RX_REO_QUEUE 495 descriptor in the 'receive timestamp' ordered list. 496 497 From it the Position of this queue descriptor in the per 498 AC aging waitlist can be derived. 499 500 Value 0x0 indicates the 'NULL' pointer which implies 501 that this is the first entry in the list. 502 503 <legal all> 504 505 ptr_to_previous_aging_queue_39_32 506 507 Address (address bits 39-32)of next RX_REO_QUEUE 508 descriptor in the 'receive timestamp' ordered list. 509 510 From it the Position of this queue descriptor in the per 511 AC aging waitlist can be derived. 512 513 Value 0x0 indicates the 'NULL' pointer which implies 514 that this is the first entry in the list. 515 516 <legal all> 517 518 reserved_13a 519 520 <legal 0> 521 522 rx_bitmap_31_0 523 524 When a bit is set, the corresponding frame is currently 525 held in the re-order queue. 526 527 The bitmap is Fully managed by HW. 528 529 SW shall init this to 0, and then never ever change it 530 531 <legal all> 532 533 rx_bitmap_63_32 534 535 See Rx_bitmap_31_0 description 536 537 <legal all> 538 539 rx_bitmap_95_64 540 541 See Rx_bitmap_31_0 description 542 543 <legal all> 544 545 rx_bitmap_127_96 546 547 See Rx_bitmap_31_0 description 548 549 <legal all> 550 551 rx_bitmap_159_128 552 553 See Rx_bitmap_31_0 description 554 555 <legal all> 556 557 rx_bitmap_191_160 558 559 See Rx_bitmap_31_0 description 560 561 <legal all> 562 563 rx_bitmap_223_192 564 565 See Rx_bitmap_31_0 description 566 567 <legal all> 568 569 rx_bitmap_255_224 570 571 See Rx_bitmap_31_0 description 572 573 <legal all> 574 575 current_mpdu_count 576 577 The number of MPDUs in the queue. 578 579 580 581 <legal all> 582 583 current_msdu_count 584 585 The number of MSDUs in the queue. 586 587 <legal all> 588 589 reserved_23 590 591 <legal 0> 592 593 timeout_count 594 595 The number of times that REO started forwarding frames 596 even though there is a hole in the bitmap. Forwarding reason 597 is Timeout 598 599 600 601 The counter saturates and freezes at 0x3F 602 603 604 605 <legal all> 606 607 forward_due_to_bar_count 608 609 The number of times that REO started forwarding frames 610 even though there is a hole in the bitmap. Forwarding reason 611 is reception of BAR frame. 612 613 614 615 The counter saturates and freezes at 0x3F 616 617 618 619 <legal all> 620 621 duplicate_count 622 623 The number of duplicate frames that have been detected 624 625 <legal all> 626 627 frames_in_order_count 628 629 The number of frames that have been received in order 630 (without a hole that prevented them from being forwarded 631 immediately) 632 633 634 635 This corresponds to the Reorder opcodes: 636 637 'FWDCUR' and 'FWD BUF' 638 639 640 641 <legal all> 642 643 bar_received_count 644 645 The number of times a BAR frame is received. 646 647 648 649 This corresponds to the Reorder opcodes with 'DROP' 650 651 652 653 The counter saturates and freezes at 0xFF 654 655 <legal all> 656 657 mpdu_frames_processed_count 658 659 The total number of MPDU frames that have been processed 660 by REO. 'Processing' here means that REO has received them 661 out of the entrance ring, and retrieved the corresponding 662 RX_REO_QUEUE Descriptor. 663 664 665 666 Note that this count includes duplicates, frames that 667 later had errors, etc. 668 669 670 671 Note that field 'Duplicate_count' indicates how many of 672 these MPDUs were duplicates. 673 674 675 676 <legal all> 677 678 msdu_frames_processed_count 679 680 The total number of MSDU frames that have been processed 681 by REO. 'Processing' here means that REO has received them 682 out of the entrance ring, and retrieved the corresponding 683 RX_REO_QUEUE Descriptor. 684 685 686 687 Note that this count includes duplicates, frames that 688 later had errors, etc. 689 690 691 692 <legal all> 693 694 total_processed_byte_count 695 696 An approximation of the number of bytes processed for 697 this queue. 698 699 'Processing' here means that REO has received them out 700 of the entrance ring, and retrieved the corresponding 701 RX_REO_QUEUE Descriptor. 702 703 704 705 Note that this count includes duplicates, frames that 706 later had errors, etc. 707 708 709 710 In 64 byte units 711 712 <legal all> 713 714 late_receive_mpdu_count 715 716 The number of MPDUs received after the window had 717 already moved on. The 'late' sequence window is defined as 718 (Window SSN - 256) - (Window SSN - 1) 719 720 721 722 This corresponds with Out of order detection in 723 duplicate detect FSM 724 725 726 727 The counter saturates and freezes at 0xFFF 728 729 730 731 <legal all> 732 733 window_jump_2k 734 735 The number of times the window moved more then 2K 736 737 738 739 The counter saturates and freezes at 0xF 740 741 742 743 (Note: field name can not start with number: previous 744 2k_window_jump) 745 746 747 748 <legal all> 749 750 hole_count 751 752 The number of times a hole was created in the receive 753 bitmap. 754 755 756 757 This corresponds to the Reorder opcodes with 'QCUR' 758 759 760 761 <legal all> 762 763 reserved_29 764 765 <legal 0> 766 767 reserved_30 768 769 <legal 0> 770 771 reserved_31 772 773 <legal 0> 774 */ 775 776 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000 777 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0 778 #define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff 779 780 /* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER 781 782 Indicates the MPDU queue ID to which this MPDU link 783 descriptor belongs 784 785 Used for tracking and debugging 786 787 <legal all> 788 */ 789 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 790 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 791 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 792 793 /* Description RX_REO_QUEUE_1_RESERVED_1B 794 795 <legal 0> 796 */ 797 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 798 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 799 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 800 801 /* Description RX_REO_QUEUE_2_VLD 802 803 Valid bit indicating a session is established and the 804 queue descriptor is valid(Filled by SW) 805 806 <legal all> 807 */ 808 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 809 #define RX_REO_QUEUE_2_VLD_LSB 0 810 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 811 812 /* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 813 814 Indicates which of the 3 link descriptor counters shall 815 be incremented or decremented when link descriptors are 816 added or removed from this flow queue. 817 818 MSDU link descriptors related with MPDUs stored in the 819 re-order buffer shall also be included in this count. 820 821 822 823 <legal 0-2> 824 */ 825 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 826 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 827 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 828 829 /* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION 830 831 When set, do not perform any duplicate detection. 832 833 834 835 <legal all> 836 */ 837 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 838 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 839 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 840 841 /* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE 842 843 When set, REO has been instructed to not perform the 844 actual re-ordering of frames for this queue, but just to 845 insert the reorder opcodes. 846 847 848 849 Note that this implies that REO is also not going to 850 perform any MSDU level operations, and the entire MPDU (and 851 thus pointer to the MSDU link descriptor) will be pushed to 852 a destination ring that SW has programmed in a SW 853 programmable configuration register in REO 854 855 856 857 <legal all> 858 */ 859 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 860 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 861 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 862 863 /* Description RX_REO_QUEUE_2_AC 864 865 Indicates which access category the queue descriptor 866 belongs to(filled by SW) 867 868 <legal all> 869 */ 870 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 871 #define RX_REO_QUEUE_2_AC_LSB 5 872 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 873 874 /* Description RX_REO_QUEUE_2_BAR 875 876 Indicates if BAR has been received (mostly used for 877 debug purpose and this is filled by REO) 878 879 <legal all> 880 */ 881 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 882 #define RX_REO_QUEUE_2_BAR_LSB 7 883 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 884 885 /* Description RX_REO_QUEUE_2_RTY 886 887 Retry bit is checked if this bit is set. 888 889 <legal all> 890 */ 891 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 892 #define RX_REO_QUEUE_2_RTY_LSB 8 893 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 894 895 /* Description RX_REO_QUEUE_2_CHK_2K_MODE 896 897 Indicates what type of operation is expected from Reo 898 when the received frame SN falls within the 2K window 899 900 901 902 See REO MLD document for programming details. 903 904 <legal all> 905 */ 906 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 907 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 908 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 909 910 /* Description RX_REO_QUEUE_2_OOR_MODE 911 912 Out of Order mode: 913 914 Indicates what type of operation is expected when the 915 received frame falls within the OOR window. 916 917 918 919 See REO MLD document for programming details. 920 921 <legal all> 922 */ 923 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 924 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 925 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 926 927 /* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE 928 929 Indicates the negotiated (window size + 1). 930 931 it can go up to Max of 256bits. 932 933 934 935 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 936 (means non-BA session, with window size of 0). The 3 values 937 here are the main values validated, but other values should 938 work as well. 939 940 941 942 A BA window size of 0 (=> one frame entry bitmat), means 943 that there is NO RX_REO_QUEUE_EXT descriptor following this 944 RX_REO_QUEUE STRUCT in memory 945 946 947 948 A BA window size of 1 - 105, means that there is 1 949 RX_REO_QUEUE_EXT descriptor directly following this 950 RX_REO_QUEUE STRUCT in memory. 951 952 953 954 A BA window size of 106 - 210, means that there are 2 955 RX_REO_QUEUE_EXT descriptors directly following this 956 RX_REO_QUEUE STRUCT in memory 957 958 959 960 A BA window size of 211 - 256, means that there are 3 961 RX_REO_QUEUE_EXT descriptors directly following this 962 RX_REO_QUEUE STRUCT in memory 963 964 965 966 <legal 0 - 255> 967 */ 968 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 969 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 970 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 971 972 /* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED 973 974 When set, REO shall perform the PN increment check 975 976 <legal all> 977 */ 978 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 979 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 980 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 981 982 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN 983 984 Field only valid when 'pn_check_needed' is set. 985 986 987 988 When set, REO shall confirm that the received PN number 989 is not only incremented, but also always an even number 990 991 <legal all> 992 */ 993 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 994 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 995 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 996 997 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN 998 999 Field only valid when 'pn_check_needed' is set. 1000 1001 1002 1003 When set, REO shall confirm that the received PN number 1004 is not only incremented, but also always an uneven number 1005 1006 <legal all> 1007 */ 1008 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1009 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 1010 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1011 1012 /* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE 1013 1014 Field only valid when 'pn_check_needed' is set. 1015 1016 1017 1018 When set, and REO detected a PN error, HW shall set the 1019 'pn_error_detected_flag'. 1020 1021 <legal all> 1022 */ 1023 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 1024 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 1025 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 1026 1027 /* Description RX_REO_QUEUE_2_PN_SIZE 1028 1029 Size of the PN field check. 1030 1031 Needed for wrap around handling... 1032 1033 1034 1035 <enum 0 pn_size_24> 1036 1037 <enum 1 pn_size_48> 1038 1039 <enum 2 pn_size_128> 1040 1041 1042 1043 <legal 0-2> 1044 */ 1045 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 1046 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 1047 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 1048 1049 /* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG 1050 1051 When set, REO shall ignore the ampdu_flag on the 1052 entrance descriptor for this queue. 1053 1054 <legal all> 1055 */ 1056 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1057 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 1058 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 1059 1060 /* Description RX_REO_QUEUE_2_RESERVED_2B 1061 1062 <legal 0> 1063 */ 1064 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 1065 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 1066 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 1067 1068 /* Description RX_REO_QUEUE_3_SVLD 1069 1070 Sequence number in next field is valid one. It can be 1071 filled by SW if the want to fill in the any negotiated SSN, 1072 otherwise REO will fill the sequence number of first 1073 received packet and set this bit to 1. 1074 1075 <legal all> 1076 */ 1077 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 1078 #define RX_REO_QUEUE_3_SVLD_LSB 0 1079 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 1080 1081 /* Description RX_REO_QUEUE_3_SSN 1082 1083 Starting Sequence number of the session, this changes 1084 whenever window moves. (can be filled by SW then maintained 1085 by REO) 1086 1087 <legal all> 1088 */ 1089 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 1090 #define RX_REO_QUEUE_3_SSN_LSB 1 1091 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 1092 1093 /* Description RX_REO_QUEUE_3_CURRENT_INDEX 1094 1095 Points to last forwarded packet 1096 1097 <legal all> 1098 */ 1099 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 1100 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 1101 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 1102 1103 /* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG 1104 1105 Set by REO, can only be cleared by SW 1106 1107 1108 1109 When set, REO has detected a 2k error jump in the 1110 sequence number and from that moment forward, all new frames 1111 are forwarded directly to FW, without duplicate detect, 1112 reordering, etc. 1113 1114 <legal all> 1115 */ 1116 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1117 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 1118 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 1119 1120 /* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG 1121 1122 Set by REO, can only be cleared by SW 1123 1124 1125 1126 When set, REO has detected a PN error and from that 1127 moment forward, all new frames are forwarded directly to FW, 1128 without duplicate detect, reordering, etc. 1129 1130 <legal all> 1131 */ 1132 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1133 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 1134 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 1135 1136 /* Description RX_REO_QUEUE_3_RESERVED_3A 1137 1138 <legal 0> 1139 */ 1140 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 1141 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 1142 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 1143 1144 /* Description RX_REO_QUEUE_3_PN_VALID 1145 1146 PN number in next fields are valid. It can be filled by 1147 SW if it wants to fill in the any negotiated SSN, otherwise 1148 REO will fill the pn based on the first received packet and 1149 set this bit to 1. 1150 1151 <legal all> 1152 */ 1153 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 1154 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 1155 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 1156 1157 /* Description RX_REO_QUEUE_4_PN_31_0 1158 1159 1160 <legal all> 1161 */ 1162 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 1163 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 1164 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 1165 1166 /* Description RX_REO_QUEUE_5_PN_63_32 1167 1168 Bits [63:32] of the PN number. 1169 1170 <legal all> 1171 */ 1172 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 1173 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 1174 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 1175 1176 /* Description RX_REO_QUEUE_6_PN_95_64 1177 1178 Bits [95:64] of the PN number. 1179 1180 <legal all> 1181 */ 1182 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 1183 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 1184 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 1185 1186 /* Description RX_REO_QUEUE_7_PN_127_96 1187 1188 Bits [127:96] of the PN number. 1189 1190 <legal all> 1191 */ 1192 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 1193 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 1194 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 1195 1196 /* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP 1197 1198 This timestamp is updated when an MPDU is received and 1199 accesses this Queue Descriptor. It does not include the 1200 access due to Command TLVs or Aging (which will be updated 1201 in Last_rx_dequeue_timestamp). 1202 1203 <legal all> 1204 */ 1205 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 1206 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 1207 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 1208 1209 /* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP 1210 1211 This timestamp is used for Aging. When an MPDU or 1212 multiple MPDUs are forwarded, either due to window movement, 1213 bar, aging or command flush, this timestamp is updated. Also 1214 when the bitmap is all zero and the first time an MPDU is 1215 queued (opcode=QCUR), this timestamp is updated for aging. 1216 1217 <legal all> 1218 */ 1219 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 1220 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 1221 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 1222 1223 /* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 1224 1225 Address (address bits 31-0)of next RX_REO_QUEUE 1226 descriptor in the 'receive timestamp' ordered list. 1227 1228 From it the Position of this queue descriptor in the per 1229 AC aging waitlist can be derived. 1230 1231 Value 0x0 indicates the 'NULL' pointer which implies 1232 that this is the last entry in the list. 1233 1234 <legal all> 1235 */ 1236 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 1237 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 1238 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 1239 1240 /* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 1241 1242 Address (address bits 39-32)of next RX_REO_QUEUE 1243 descriptor in the 'receive timestamp' ordered list. 1244 1245 From it the Position of this queue descriptor in the per 1246 AC aging waitlist can be derived. 1247 1248 Value 0x0 indicates the 'NULL' pointer which implies 1249 that this is the last entry in the list. 1250 1251 <legal all> 1252 */ 1253 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 1254 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 1255 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 1256 1257 /* Description RX_REO_QUEUE_11_RESERVED_11A 1258 1259 <legal 0> 1260 */ 1261 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 1262 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 1263 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 1264 1265 /* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 1266 1267 Address (address bits 31-0)of next RX_REO_QUEUE 1268 descriptor in the 'receive timestamp' ordered list. 1269 1270 From it the Position of this queue descriptor in the per 1271 AC aging waitlist can be derived. 1272 1273 Value 0x0 indicates the 'NULL' pointer which implies 1274 that this is the first entry in the list. 1275 1276 <legal all> 1277 */ 1278 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 1279 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 1280 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 1281 1282 /* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 1283 1284 Address (address bits 39-32)of next RX_REO_QUEUE 1285 descriptor in the 'receive timestamp' ordered list. 1286 1287 From it the Position of this queue descriptor in the per 1288 AC aging waitlist can be derived. 1289 1290 Value 0x0 indicates the 'NULL' pointer which implies 1291 that this is the first entry in the list. 1292 1293 <legal all> 1294 */ 1295 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 1296 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 1297 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 1298 1299 /* Description RX_REO_QUEUE_13_RESERVED_13A 1300 1301 <legal 0> 1302 */ 1303 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 1304 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 1305 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 1306 1307 /* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 1308 1309 When a bit is set, the corresponding frame is currently 1310 held in the re-order queue. 1311 1312 The bitmap is Fully managed by HW. 1313 1314 SW shall init this to 0, and then never ever change it 1315 1316 <legal all> 1317 */ 1318 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 1319 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 1320 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 1321 1322 /* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 1323 1324 See Rx_bitmap_31_0 description 1325 1326 <legal all> 1327 */ 1328 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 1329 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 1330 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 1331 1332 /* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 1333 1334 See Rx_bitmap_31_0 description 1335 1336 <legal all> 1337 */ 1338 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 1339 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 1340 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 1341 1342 /* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 1343 1344 See Rx_bitmap_31_0 description 1345 1346 <legal all> 1347 */ 1348 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 1349 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 1350 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 1351 1352 /* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 1353 1354 See Rx_bitmap_31_0 description 1355 1356 <legal all> 1357 */ 1358 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 1359 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 1360 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 1361 1362 /* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 1363 1364 See Rx_bitmap_31_0 description 1365 1366 <legal all> 1367 */ 1368 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 1369 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 1370 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 1371 1372 /* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 1373 1374 See Rx_bitmap_31_0 description 1375 1376 <legal all> 1377 */ 1378 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 1379 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 1380 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 1381 1382 /* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 1383 1384 See Rx_bitmap_31_0 description 1385 1386 <legal all> 1387 */ 1388 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 1389 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 1390 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 1391 1392 /* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT 1393 1394 The number of MPDUs in the queue. 1395 1396 1397 1398 <legal all> 1399 */ 1400 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 1401 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 1402 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 1403 1404 /* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT 1405 1406 The number of MSDUs in the queue. 1407 1408 <legal all> 1409 */ 1410 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 1411 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 1412 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 1413 1414 /* Description RX_REO_QUEUE_23_RESERVED_23 1415 1416 <legal 0> 1417 */ 1418 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 1419 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 1420 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 1421 1422 /* Description RX_REO_QUEUE_23_TIMEOUT_COUNT 1423 1424 The number of times that REO started forwarding frames 1425 even though there is a hole in the bitmap. Forwarding reason 1426 is Timeout 1427 1428 1429 1430 The counter saturates and freezes at 0x3F 1431 1432 1433 1434 <legal all> 1435 */ 1436 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 1437 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 1438 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 1439 1440 /* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT 1441 1442 The number of times that REO started forwarding frames 1443 even though there is a hole in the bitmap. Forwarding reason 1444 is reception of BAR frame. 1445 1446 1447 1448 The counter saturates and freezes at 0x3F 1449 1450 1451 1452 <legal all> 1453 */ 1454 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 1455 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1456 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1457 1458 /* Description RX_REO_QUEUE_23_DUPLICATE_COUNT 1459 1460 The number of duplicate frames that have been detected 1461 1462 <legal all> 1463 */ 1464 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 1465 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 1466 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 1467 1468 /* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT 1469 1470 The number of frames that have been received in order 1471 (without a hole that prevented them from being forwarded 1472 immediately) 1473 1474 1475 1476 This corresponds to the Reorder opcodes: 1477 1478 'FWDCUR' and 'FWD BUF' 1479 1480 1481 1482 <legal all> 1483 */ 1484 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 1485 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 1486 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1487 1488 /* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT 1489 1490 The number of times a BAR frame is received. 1491 1492 1493 1494 This corresponds to the Reorder opcodes with 'DROP' 1495 1496 1497 1498 The counter saturates and freezes at 0xFF 1499 1500 <legal all> 1501 */ 1502 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 1503 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 1504 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 1505 1506 /* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT 1507 1508 The total number of MPDU frames that have been processed 1509 by REO. 'Processing' here means that REO has received them 1510 out of the entrance ring, and retrieved the corresponding 1511 RX_REO_QUEUE Descriptor. 1512 1513 1514 1515 Note that this count includes duplicates, frames that 1516 later had errors, etc. 1517 1518 1519 1520 Note that field 'Duplicate_count' indicates how many of 1521 these MPDUs were duplicates. 1522 1523 1524 1525 <legal all> 1526 */ 1527 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 1528 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1529 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1530 1531 /* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT 1532 1533 The total number of MSDU frames that have been processed 1534 by REO. 'Processing' here means that REO has received them 1535 out of the entrance ring, and retrieved the corresponding 1536 RX_REO_QUEUE Descriptor. 1537 1538 1539 1540 Note that this count includes duplicates, frames that 1541 later had errors, etc. 1542 1543 1544 1545 <legal all> 1546 */ 1547 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1548 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1549 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1550 1551 /* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT 1552 1553 An approximation of the number of bytes processed for 1554 this queue. 1555 1556 'Processing' here means that REO has received them out 1557 of the entrance ring, and retrieved the corresponding 1558 RX_REO_QUEUE Descriptor. 1559 1560 1561 1562 Note that this count includes duplicates, frames that 1563 later had errors, etc. 1564 1565 1566 1567 In 64 byte units 1568 1569 <legal all> 1570 */ 1571 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 1572 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1573 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1574 1575 /* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT 1576 1577 The number of MPDUs received after the window had 1578 already moved on. The 'late' sequence window is defined as 1579 (Window SSN - 256) - (Window SSN - 1) 1580 1581 1582 1583 This corresponds with Out of order detection in 1584 duplicate detect FSM 1585 1586 1587 1588 The counter saturates and freezes at 0xFFF 1589 1590 1591 1592 <legal all> 1593 */ 1594 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 1595 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 1596 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1597 1598 /* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K 1599 1600 The number of times the window moved more then 2K 1601 1602 1603 1604 The counter saturates and freezes at 0xF 1605 1606 1607 1608 (Note: field name can not start with number: previous 1609 2k_window_jump) 1610 1611 1612 1613 <legal all> 1614 */ 1615 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 1616 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 1617 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 1618 1619 /* Description RX_REO_QUEUE_28_HOLE_COUNT 1620 1621 The number of times a hole was created in the receive 1622 bitmap. 1623 1624 1625 1626 This corresponds to the Reorder opcodes with 'QCUR' 1627 1628 1629 1630 <legal all> 1631 */ 1632 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 1633 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 1634 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 1635 1636 /* Description RX_REO_QUEUE_29_RESERVED_29 1637 1638 <legal 0> 1639 */ 1640 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 1641 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 1642 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 1643 1644 /* Description RX_REO_QUEUE_30_RESERVED_30 1645 1646 <legal 0> 1647 */ 1648 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 1649 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 1650 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 1651 1652 /* Description RX_REO_QUEUE_31_RESERVED_31 1653 1654 <legal 0> 1655 */ 1656 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 1657 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 1658 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 1659 1660 1661 #endif // _RX_REO_QUEUE_H_ 1662