1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/8/2017 22 // User Name:gunjans 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 29 #define __MAC_TCL_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "mac_tcl_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block MAC_TCL_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 45 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 48 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 49 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 50 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 51 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 52 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 53 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 55 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 56 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 65 66 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 67 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 68 69 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 70 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 73 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 74 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 75 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 76 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 77 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 78 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 80 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 81 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 82 do {\ 83 HWIO_INTLOCK(); \ 84 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 85 HWIO_INTFREE();\ 86 } while (0) 87 88 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 90 91 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 92 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 93 94 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 95 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 98 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 99 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 100 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 101 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 102 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 103 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 105 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 106 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 107 do {\ 108 HWIO_INTLOCK(); \ 109 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 110 HWIO_INTFREE();\ 111 } while (0) 112 113 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 115 116 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 117 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 118 119 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 120 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 123 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 124 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 125 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 126 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 127 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 128 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 130 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 131 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 132 do {\ 133 HWIO_INTLOCK(); \ 134 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 135 HWIO_INTFREE();\ 136 } while (0) 137 138 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 140 141 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 142 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 143 144 //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// 145 146 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) 147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) 148 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 149 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 150 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ 151 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) 152 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ 153 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ 155 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) 156 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ 157 do {\ 158 HWIO_INTLOCK(); \ 159 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ 160 HWIO_INTFREE();\ 161 } while (0) 162 163 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 165 166 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 167 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 168 169 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 170 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 173 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x0001ffff 174 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 175 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 176 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 177 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 178 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 180 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 181 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 182 do {\ 183 HWIO_INTLOCK(); \ 184 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 185 HWIO_INTFREE();\ 186 } while (0) 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 226 227 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 229 230 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 232 233 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 234 235 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 236 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 237 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00000fff 238 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 239 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 240 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 241 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 242 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 243 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 244 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 245 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 246 do {\ 247 HWIO_INTLOCK(); \ 248 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 249 HWIO_INTFREE();\ 250 } while (0) 251 252 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 253 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 254 255 //// Register TCL_R0_TCL2FW_RING_CTRL //// 256 257 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 258 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 259 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 260 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 261 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 262 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 263 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 264 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 265 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 266 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 267 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 268 do {\ 269 HWIO_INTLOCK(); \ 270 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 271 HWIO_INTFREE();\ 272 } while (0) 273 274 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 275 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 276 277 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 278 279 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 280 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 281 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 282 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 283 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 284 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 285 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 286 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 287 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 288 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 289 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 290 do {\ 291 HWIO_INTLOCK(); \ 292 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 293 HWIO_INTFREE();\ 294 } while (0) 295 296 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 297 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 298 299 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 300 301 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 302 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 303 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 304 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 305 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 306 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 307 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 308 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 309 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 310 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 311 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 312 do {\ 313 HWIO_INTLOCK(); \ 314 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 315 HWIO_INTFREE();\ 316 } while (0) 317 318 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 319 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 320 321 //// Register TCL_R0_GEN_CTRL //// 322 323 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 324 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 325 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffffffff 326 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 327 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 328 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 329 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 330 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 331 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 332 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 333 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 334 do {\ 335 HWIO_INTLOCK(); \ 336 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 337 HWIO_INTFREE();\ 338 } while (0) 339 340 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 341 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 342 343 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 344 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 345 346 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 347 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 348 349 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 350 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 351 352 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 353 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 354 355 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK 0x00000e00 356 #define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT 0x9 357 358 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 359 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 360 361 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 362 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 363 364 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 365 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 366 367 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 368 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 369 370 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 371 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 372 373 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 374 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 375 376 #define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK 0x00000004 377 #define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT 0x2 378 379 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 380 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 381 382 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 383 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 384 385 //// Register TCL_R0_DSCP_TID1_MAP_0 //// 386 387 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x) (x+0x0000002c) 388 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x) (x+0x0000002c) 389 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK 0x3fffffff 390 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT 0 391 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x) \ 392 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK) 393 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask) \ 394 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) 395 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val) \ 396 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val) 397 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val) \ 398 do {\ 399 HWIO_INTLOCK(); \ 400 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \ 401 HWIO_INTFREE();\ 402 } while (0) 403 404 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK 0x38000000 405 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT 0x1b 406 407 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK 0x07000000 408 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT 0x18 409 410 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK 0x00e00000 411 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT 0x15 412 413 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK 0x001c0000 414 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT 0x12 415 416 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK 0x00038000 417 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT 0xf 418 419 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK 0x00007000 420 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT 0xc 421 422 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK 0x00000e00 423 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT 0x9 424 425 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK 0x000001c0 426 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT 0x6 427 428 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK 0x00000038 429 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT 0x3 430 431 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK 0x00000007 432 #define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT 0x0 433 434 //// Register TCL_R0_DSCP_TID1_MAP_1 //// 435 436 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x) (x+0x00000030) 437 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x) (x+0x00000030) 438 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK 0x3fffffff 439 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT 0 440 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x) \ 441 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK) 442 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask) \ 443 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) 444 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val) \ 445 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val) 446 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val) \ 447 do {\ 448 HWIO_INTLOCK(); \ 449 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \ 450 HWIO_INTFREE();\ 451 } while (0) 452 453 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK 0x38000000 454 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT 0x1b 455 456 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK 0x07000000 457 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT 0x18 458 459 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK 0x00e00000 460 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT 0x15 461 462 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK 0x001c0000 463 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT 0x12 464 465 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK 0x00038000 466 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT 0xf 467 468 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK 0x00007000 469 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT 0xc 470 471 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK 0x00000e00 472 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT 0x9 473 474 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK 0x000001c0 475 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT 0x6 476 477 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK 0x00000038 478 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT 0x3 479 480 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK 0x00000007 481 #define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT 0x0 482 483 //// Register TCL_R0_DSCP_TID1_MAP_2 //// 484 485 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x) (x+0x00000034) 486 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x) (x+0x00000034) 487 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK 0x3fffffff 488 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT 0 489 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x) \ 490 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK) 491 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask) \ 492 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) 493 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val) \ 494 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val) 495 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val) \ 496 do {\ 497 HWIO_INTLOCK(); \ 498 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \ 499 HWIO_INTFREE();\ 500 } while (0) 501 502 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK 0x38000000 503 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT 0x1b 504 505 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK 0x07000000 506 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT 0x18 507 508 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK 0x00e00000 509 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT 0x15 510 511 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK 0x001c0000 512 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT 0x12 513 514 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK 0x00038000 515 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT 0xf 516 517 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK 0x00007000 518 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT 0xc 519 520 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK 0x00000e00 521 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT 0x9 522 523 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK 0x000001c0 524 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT 0x6 525 526 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK 0x00000038 527 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT 0x3 528 529 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK 0x00000007 530 #define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT 0x0 531 532 //// Register TCL_R0_DSCP_TID1_MAP_3 //// 533 534 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x) (x+0x00000038) 535 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x) (x+0x00000038) 536 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK 0x3fffffff 537 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT 0 538 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x) \ 539 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK) 540 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask) \ 541 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) 542 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val) \ 543 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val) 544 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val) \ 545 do {\ 546 HWIO_INTLOCK(); \ 547 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \ 548 HWIO_INTFREE();\ 549 } while (0) 550 551 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK 0x38000000 552 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT 0x1b 553 554 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK 0x07000000 555 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT 0x18 556 557 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK 0x00e00000 558 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT 0x15 559 560 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK 0x001c0000 561 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT 0x12 562 563 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK 0x00038000 564 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT 0xf 565 566 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK 0x00007000 567 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT 0xc 568 569 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK 0x00000e00 570 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT 0x9 571 572 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK 0x000001c0 573 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT 0x6 574 575 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK 0x00000038 576 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT 0x3 577 578 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK 0x00000007 579 #define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT 0x0 580 581 //// Register TCL_R0_DSCP_TID1_MAP_4 //// 582 583 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x) (x+0x0000003c) 584 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x) (x+0x0000003c) 585 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK 0x3fffffff 586 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT 0 587 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x) \ 588 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK) 589 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask) \ 590 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) 591 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val) \ 592 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val) 593 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val) \ 594 do {\ 595 HWIO_INTLOCK(); \ 596 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \ 597 HWIO_INTFREE();\ 598 } while (0) 599 600 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK 0x38000000 601 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT 0x1b 602 603 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK 0x07000000 604 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT 0x18 605 606 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK 0x00e00000 607 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT 0x15 608 609 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK 0x001c0000 610 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT 0x12 611 612 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK 0x00038000 613 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT 0xf 614 615 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK 0x00007000 616 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT 0xc 617 618 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK 0x00000e00 619 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT 0x9 620 621 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK 0x000001c0 622 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT 0x6 623 624 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK 0x00000038 625 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT 0x3 626 627 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK 0x00000007 628 #define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT 0x0 629 630 //// Register TCL_R0_DSCP_TID1_MAP_5 //// 631 632 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x) (x+0x00000040) 633 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x) (x+0x00000040) 634 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK 0x3fffffff 635 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT 0 636 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x) \ 637 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK) 638 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask) \ 639 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) 640 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val) \ 641 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val) 642 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val) \ 643 do {\ 644 HWIO_INTLOCK(); \ 645 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \ 646 HWIO_INTFREE();\ 647 } while (0) 648 649 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK 0x38000000 650 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT 0x1b 651 652 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK 0x07000000 653 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT 0x18 654 655 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK 0x00e00000 656 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT 0x15 657 658 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK 0x001c0000 659 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT 0x12 660 661 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK 0x00038000 662 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT 0xf 663 664 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK 0x00007000 665 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT 0xc 666 667 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK 0x00000e00 668 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT 0x9 669 670 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK 0x000001c0 671 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT 0x6 672 673 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK 0x00000038 674 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT 0x3 675 676 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK 0x00000007 677 #define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT 0x0 678 679 //// Register TCL_R0_DSCP_TID1_MAP_6 //// 680 681 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x) (x+0x00000044) 682 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x) (x+0x00000044) 683 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK 0x00000fff 684 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT 0 685 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x) \ 686 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK) 687 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask) \ 688 in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) 689 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val) \ 690 out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val) 691 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val) \ 692 do {\ 693 HWIO_INTLOCK(); \ 694 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \ 695 HWIO_INTFREE();\ 696 } while (0) 697 698 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK 0x00000e00 699 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT 0x9 700 701 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK 0x000001c0 702 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT 0x6 703 704 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK 0x00000038 705 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT 0x3 706 707 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK 0x00000007 708 #define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT 0x0 709 710 //// Register TCL_R0_DSCP_TID2_MAP_0 //// 711 712 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x) (x+0x00000048) 713 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x) (x+0x00000048) 714 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK 0x3fffffff 715 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT 0 716 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x) \ 717 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK) 718 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask) \ 719 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) 720 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val) \ 721 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val) 722 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val) \ 723 do {\ 724 HWIO_INTLOCK(); \ 725 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \ 726 HWIO_INTFREE();\ 727 } while (0) 728 729 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK 0x38000000 730 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT 0x1b 731 732 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK 0x07000000 733 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT 0x18 734 735 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK 0x00e00000 736 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT 0x15 737 738 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK 0x001c0000 739 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT 0x12 740 741 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK 0x00038000 742 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT 0xf 743 744 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK 0x00007000 745 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT 0xc 746 747 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK 0x00000e00 748 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT 0x9 749 750 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK 0x000001c0 751 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT 0x6 752 753 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK 0x00000038 754 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT 0x3 755 756 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK 0x00000007 757 #define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT 0x0 758 759 //// Register TCL_R0_DSCP_TID2_MAP_1 //// 760 761 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x) (x+0x0000004c) 762 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x) (x+0x0000004c) 763 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK 0x3fffffff 764 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT 0 765 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x) \ 766 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK) 767 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask) \ 768 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) 769 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val) \ 770 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val) 771 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val) \ 772 do {\ 773 HWIO_INTLOCK(); \ 774 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \ 775 HWIO_INTFREE();\ 776 } while (0) 777 778 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK 0x38000000 779 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT 0x1b 780 781 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK 0x07000000 782 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT 0x18 783 784 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK 0x00e00000 785 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT 0x15 786 787 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK 0x001c0000 788 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT 0x12 789 790 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK 0x00038000 791 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT 0xf 792 793 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK 0x00007000 794 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT 0xc 795 796 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK 0x00000e00 797 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT 0x9 798 799 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK 0x000001c0 800 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT 0x6 801 802 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK 0x00000038 803 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT 0x3 804 805 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK 0x00000007 806 #define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT 0x0 807 808 //// Register TCL_R0_DSCP_TID2_MAP_2 //// 809 810 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x) (x+0x00000050) 811 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x) (x+0x00000050) 812 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK 0x3fffffff 813 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT 0 814 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x) \ 815 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK) 816 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask) \ 817 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) 818 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val) \ 819 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val) 820 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val) \ 821 do {\ 822 HWIO_INTLOCK(); \ 823 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \ 824 HWIO_INTFREE();\ 825 } while (0) 826 827 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK 0x38000000 828 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT 0x1b 829 830 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK 0x07000000 831 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT 0x18 832 833 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK 0x00e00000 834 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT 0x15 835 836 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK 0x001c0000 837 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT 0x12 838 839 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK 0x00038000 840 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT 0xf 841 842 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK 0x00007000 843 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT 0xc 844 845 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK 0x00000e00 846 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT 0x9 847 848 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK 0x000001c0 849 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT 0x6 850 851 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK 0x00000038 852 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT 0x3 853 854 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK 0x00000007 855 #define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT 0x0 856 857 //// Register TCL_R0_DSCP_TID2_MAP_3 //// 858 859 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x) (x+0x00000054) 860 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x) (x+0x00000054) 861 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK 0x3fffffff 862 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT 0 863 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x) \ 864 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK) 865 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask) \ 866 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) 867 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val) \ 868 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val) 869 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val) \ 870 do {\ 871 HWIO_INTLOCK(); \ 872 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \ 873 HWIO_INTFREE();\ 874 } while (0) 875 876 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK 0x38000000 877 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT 0x1b 878 879 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK 0x07000000 880 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT 0x18 881 882 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK 0x00e00000 883 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT 0x15 884 885 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK 0x001c0000 886 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT 0x12 887 888 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK 0x00038000 889 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT 0xf 890 891 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK 0x00007000 892 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT 0xc 893 894 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK 0x00000e00 895 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT 0x9 896 897 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK 0x000001c0 898 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT 0x6 899 900 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK 0x00000038 901 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT 0x3 902 903 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK 0x00000007 904 #define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT 0x0 905 906 //// Register TCL_R0_DSCP_TID2_MAP_4 //// 907 908 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x) (x+0x00000058) 909 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x) (x+0x00000058) 910 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK 0x3fffffff 911 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT 0 912 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x) \ 913 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK) 914 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask) \ 915 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) 916 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val) \ 917 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val) 918 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val) \ 919 do {\ 920 HWIO_INTLOCK(); \ 921 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \ 922 HWIO_INTFREE();\ 923 } while (0) 924 925 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK 0x38000000 926 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT 0x1b 927 928 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK 0x07000000 929 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT 0x18 930 931 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK 0x00e00000 932 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT 0x15 933 934 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK 0x001c0000 935 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT 0x12 936 937 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK 0x00038000 938 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT 0xf 939 940 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK 0x00007000 941 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT 0xc 942 943 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK 0x00000e00 944 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT 0x9 945 946 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK 0x000001c0 947 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT 0x6 948 949 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK 0x00000038 950 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT 0x3 951 952 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK 0x00000007 953 #define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT 0x0 954 955 //// Register TCL_R0_DSCP_TID2_MAP_5 //// 956 957 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x) (x+0x0000005c) 958 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x) (x+0x0000005c) 959 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK 0x3fffffff 960 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT 0 961 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x) \ 962 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK) 963 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask) \ 964 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) 965 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val) \ 966 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val) 967 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val) \ 968 do {\ 969 HWIO_INTLOCK(); \ 970 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \ 971 HWIO_INTFREE();\ 972 } while (0) 973 974 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK 0x38000000 975 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT 0x1b 976 977 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK 0x07000000 978 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT 0x18 979 980 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK 0x00e00000 981 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT 0x15 982 983 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK 0x001c0000 984 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT 0x12 985 986 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK 0x00038000 987 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT 0xf 988 989 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK 0x00007000 990 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT 0xc 991 992 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK 0x00000e00 993 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT 0x9 994 995 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK 0x000001c0 996 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT 0x6 997 998 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK 0x00000038 999 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT 0x3 1000 1001 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK 0x00000007 1002 #define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT 0x0 1003 1004 //// Register TCL_R0_DSCP_TID2_MAP_6 //// 1005 1006 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x) (x+0x00000060) 1007 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x) (x+0x00000060) 1008 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK 0x00000fff 1009 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT 0 1010 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x) \ 1011 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK) 1012 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask) \ 1013 in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) 1014 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val) \ 1015 out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val) 1016 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val) \ 1017 do {\ 1018 HWIO_INTLOCK(); \ 1019 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \ 1020 HWIO_INTFREE();\ 1021 } while (0) 1022 1023 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK 0x00000e00 1024 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT 0x9 1025 1026 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK 0x000001c0 1027 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT 0x6 1028 1029 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK 0x00000038 1030 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT 0x3 1031 1032 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK 0x00000007 1033 #define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT 0x0 1034 1035 //// Register TCL_R0_PCP_TID_MAP //// 1036 1037 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x00000064) 1038 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x00000064) 1039 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 1040 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 1041 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 1042 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 1043 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 1044 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 1045 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 1046 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 1047 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 1048 do {\ 1049 HWIO_INTLOCK(); \ 1050 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 1051 HWIO_INTFREE();\ 1052 } while (0) 1053 1054 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 1055 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 1056 1057 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 1058 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 1059 1060 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 1061 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 1062 1063 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 1064 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 1065 1066 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 1067 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 1068 1069 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 1070 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 1071 1072 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 1073 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 1074 1075 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 1076 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 1077 1078 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 1079 1080 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x00000068) 1081 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x00000068) 1082 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 1083 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 1084 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 1085 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 1086 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 1087 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 1088 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 1089 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 1090 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 1091 do {\ 1092 HWIO_INTLOCK(); \ 1093 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 1094 HWIO_INTFREE();\ 1095 } while (0) 1096 1097 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 1098 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 1099 1100 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 1101 1102 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x0000006c) 1103 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x0000006c) 1104 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 1105 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 1106 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 1107 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 1108 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 1109 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 1110 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 1111 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 1112 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 1113 do {\ 1114 HWIO_INTLOCK(); \ 1115 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 1116 HWIO_INTFREE();\ 1117 } while (0) 1118 1119 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 1120 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 1121 1122 //// Register TCL_R0_ASE_HASH_KEY_64 //// 1123 1124 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x00000070) 1125 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x00000070) 1126 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 1127 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 1128 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 1129 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 1130 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 1131 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 1132 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 1133 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 1134 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 1135 do {\ 1136 HWIO_INTLOCK(); \ 1137 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 1138 HWIO_INTFREE();\ 1139 } while (0) 1140 1141 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 1142 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 1143 1144 //// Register TCL_R0_FSE_HASH_KEY_31_0 //// 1145 1146 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x00000074) 1147 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x00000074) 1148 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff 1149 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 1150 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ 1151 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) 1152 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ 1153 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 1154 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ 1155 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) 1156 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ 1157 do {\ 1158 HWIO_INTLOCK(); \ 1159 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ 1160 HWIO_INTFREE();\ 1161 } while (0) 1162 1163 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 1164 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 1165 1166 //// Register TCL_R0_FSE_HASH_KEY_63_32 //// 1167 1168 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x00000078) 1169 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x00000078) 1170 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff 1171 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 1172 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ 1173 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) 1174 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ 1175 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 1176 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ 1177 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) 1178 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ 1179 do {\ 1180 HWIO_INTLOCK(); \ 1181 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ 1182 HWIO_INTFREE();\ 1183 } while (0) 1184 1185 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 1186 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 1187 1188 //// Register TCL_R0_FSE_HASH_KEY_95_64 //// 1189 1190 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x0000007c) 1191 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x0000007c) 1192 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff 1193 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 1194 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ 1195 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) 1196 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ 1197 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 1198 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ 1199 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) 1200 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ 1201 do {\ 1202 HWIO_INTLOCK(); \ 1203 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ 1204 HWIO_INTFREE();\ 1205 } while (0) 1206 1207 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff 1208 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 1209 1210 //// Register TCL_R0_FSE_HASH_KEY_127_96 //// 1211 1212 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x00000080) 1213 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x00000080) 1214 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff 1215 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 1216 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ 1217 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) 1218 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ 1219 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 1220 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ 1221 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) 1222 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ 1223 do {\ 1224 HWIO_INTLOCK(); \ 1225 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ 1226 HWIO_INTFREE();\ 1227 } while (0) 1228 1229 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff 1230 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 1231 1232 //// Register TCL_R0_FSE_HASH_KEY_159_128 //// 1233 1234 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x00000084) 1235 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x00000084) 1236 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff 1237 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 1238 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ 1239 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) 1240 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ 1241 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 1242 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ 1243 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) 1244 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ 1245 do {\ 1246 HWIO_INTLOCK(); \ 1247 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ 1248 HWIO_INTFREE();\ 1249 } while (0) 1250 1251 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff 1252 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 1253 1254 //// Register TCL_R0_FSE_HASH_KEY_191_160 //// 1255 1256 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x00000088) 1257 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x00000088) 1258 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff 1259 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 1260 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ 1261 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) 1262 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ 1263 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 1264 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ 1265 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) 1266 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ 1267 do {\ 1268 HWIO_INTLOCK(); \ 1269 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ 1270 HWIO_INTFREE();\ 1271 } while (0) 1272 1273 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff 1274 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 1275 1276 //// Register TCL_R0_FSE_HASH_KEY_223_192 //// 1277 1278 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x0000008c) 1279 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x0000008c) 1280 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff 1281 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 1282 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ 1283 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) 1284 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ 1285 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 1286 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ 1287 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) 1288 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ 1289 do {\ 1290 HWIO_INTLOCK(); \ 1291 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ 1292 HWIO_INTFREE();\ 1293 } while (0) 1294 1295 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff 1296 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 1297 1298 //// Register TCL_R0_FSE_HASH_KEY_255_224 //// 1299 1300 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x00000090) 1301 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x00000090) 1302 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff 1303 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 1304 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ 1305 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) 1306 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ 1307 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 1308 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ 1309 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) 1310 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ 1311 do {\ 1312 HWIO_INTLOCK(); \ 1313 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ 1314 HWIO_INTFREE();\ 1315 } while (0) 1316 1317 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff 1318 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 1319 1320 //// Register TCL_R0_FSE_HASH_KEY_287_256 //// 1321 1322 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x00000094) 1323 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x00000094) 1324 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff 1325 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 1326 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ 1327 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) 1328 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ 1329 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 1330 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ 1331 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) 1332 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ 1333 do {\ 1334 HWIO_INTLOCK(); \ 1335 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ 1336 HWIO_INTFREE();\ 1337 } while (0) 1338 1339 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff 1340 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 1341 1342 //// Register TCL_R0_FSE_HASH_KEY_314_288 //// 1343 1344 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x00000098) 1345 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x00000098) 1346 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff 1347 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 1348 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ 1349 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) 1350 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ 1351 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 1352 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ 1353 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) 1354 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ 1355 do {\ 1356 HWIO_INTLOCK(); \ 1357 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ 1358 HWIO_INTFREE();\ 1359 } while (0) 1360 1361 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff 1362 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 1363 1364 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 1365 1366 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x0000009c) 1367 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x0000009c) 1368 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00003dfc 1369 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 1370 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 1371 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 1372 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 1373 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 1374 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 1375 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 1376 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 1377 do {\ 1378 HWIO_INTLOCK(); \ 1379 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 1380 HWIO_INTFREE();\ 1381 } while (0) 1382 1383 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 1384 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 1385 1386 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 1387 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 1388 1389 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 1390 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 1391 1392 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 1393 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 1394 1395 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 1396 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 1397 1398 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 1399 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 1400 1401 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 1402 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 1403 1404 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 1405 1406 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a0) 1407 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a0) 1408 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 1409 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 1410 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 1411 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 1412 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 1413 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 1414 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 1415 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 1416 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 1417 do {\ 1418 HWIO_INTLOCK(); \ 1419 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 1420 HWIO_INTFREE();\ 1421 } while (0) 1422 1423 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 1424 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 1425 1426 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 1427 1428 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000a4) 1429 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000a4) 1430 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 1431 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 1432 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 1433 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 1434 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 1435 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 1436 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 1437 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 1438 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 1439 do {\ 1440 HWIO_INTLOCK(); \ 1441 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 1442 HWIO_INTFREE();\ 1443 } while (0) 1444 1445 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 1446 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 1447 1448 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 1449 1450 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000000a8) 1451 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000000a8) 1452 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 1453 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 1454 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 1455 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 1456 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 1457 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 1458 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 1459 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 1460 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 1461 do {\ 1462 HWIO_INTLOCK(); \ 1463 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 1464 HWIO_INTFREE();\ 1465 } while (0) 1466 1467 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 1468 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 1469 1470 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 1471 1472 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000000ac) 1473 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000000ac) 1474 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 1475 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 1476 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 1477 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 1478 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 1479 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 1480 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 1481 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 1482 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 1483 do {\ 1484 HWIO_INTLOCK(); \ 1485 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 1486 HWIO_INTFREE();\ 1487 } while (0) 1488 1489 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 1490 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 1491 1492 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 1493 1494 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000000b0) 1495 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000000b0) 1496 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 1497 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 1498 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 1499 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 1500 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 1501 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 1502 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 1503 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 1504 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 1505 do {\ 1506 HWIO_INTLOCK(); \ 1507 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 1508 HWIO_INTFREE();\ 1509 } while (0) 1510 1511 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 1512 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 1513 1514 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 1515 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 1516 1517 //// Register TCL_R0_TID_MAP_PRTY //// 1518 1519 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000000b4) 1520 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000000b4) 1521 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 1522 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 1523 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 1524 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 1525 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 1526 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 1527 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 1528 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 1529 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 1530 do {\ 1531 HWIO_INTLOCK(); \ 1532 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 1533 HWIO_INTFREE();\ 1534 } while (0) 1535 1536 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 1537 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 1538 1539 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 1540 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 1541 1542 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 1543 1544 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000000b8) 1545 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000000b8) 1546 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 1547 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 1548 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 1549 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 1550 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 1551 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 1552 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 1553 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 1554 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 1555 do {\ 1556 HWIO_INTLOCK(); \ 1557 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 1558 HWIO_INTFREE();\ 1559 } while (0) 1560 1561 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 1562 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 1563 1564 //// Register TCL_R0_WATCHDOG //// 1565 1566 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000000bc) 1567 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000000bc) 1568 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 1569 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 1570 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 1571 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 1572 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 1573 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 1574 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 1575 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 1576 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 1577 do {\ 1578 HWIO_INTLOCK(); \ 1579 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 1580 HWIO_INTFREE();\ 1581 } while (0) 1582 1583 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 1584 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 1585 1586 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 1587 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 1588 1589 //// Register TCL_R0_CLKGATE_DISABLE //// 1590 1591 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x000000c0) 1592 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x000000c0) 1593 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 1594 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 1595 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 1596 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 1597 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 1598 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 1599 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 1600 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 1601 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 1602 do {\ 1603 HWIO_INTLOCK(); \ 1604 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 1605 HWIO_INTFREE();\ 1606 } while (0) 1607 1608 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 1609 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 1610 1611 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 1612 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 1613 1614 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 1615 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 1616 1617 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 1618 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 1619 1620 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 1621 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 1622 1623 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 1624 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 1625 1626 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 1627 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 1628 1629 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 1630 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 1631 1632 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 1633 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 1634 1635 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 1636 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 1637 1638 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 1639 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 1640 1641 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 1642 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 1643 1644 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 1645 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 1646 1647 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 1648 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 1649 1650 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 1651 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 1652 1653 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 1654 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 1655 1656 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 1657 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 1658 1659 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 1660 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 1661 1662 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 1663 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 1664 1665 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 1666 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 1667 1668 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 1669 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 1670 1671 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 1672 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 1673 1674 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 1675 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 1676 1677 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 1678 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 1679 1680 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 1681 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 1682 1683 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 1684 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 1685 1686 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 1687 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 1688 1689 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 1690 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 1691 1692 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 1693 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 1694 1695 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 1696 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 1697 1698 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_BMSK 0x00000002 1699 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_SHFT 0x1 1700 1701 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 1702 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 1703 1704 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 1705 1706 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000000c4) 1707 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000000c4) 1708 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 1709 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1710 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1711 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1712 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1713 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1714 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1715 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1716 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1717 do {\ 1718 HWIO_INTLOCK(); \ 1719 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1720 HWIO_INTFREE();\ 1721 } while (0) 1722 1723 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1724 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1725 1726 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1727 1728 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000000c8) 1729 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000000c8) 1730 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 1731 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1732 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1733 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1734 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1735 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1736 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1737 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1738 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1739 do {\ 1740 HWIO_INTLOCK(); \ 1741 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1742 HWIO_INTFREE();\ 1743 } while (0) 1744 1745 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1746 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1747 1748 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1749 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1750 1751 //// Register TCL_R0_SW2TCL1_RING_ID //// 1752 1753 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x000000cc) 1754 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x000000cc) 1755 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1756 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1757 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1758 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1759 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1760 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1761 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1762 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1763 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1764 do {\ 1765 HWIO_INTLOCK(); \ 1766 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1767 HWIO_INTFREE();\ 1768 } while (0) 1769 1770 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1771 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1772 1773 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1774 1775 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000000d0) 1776 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000000d0) 1777 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1778 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1779 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1780 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1781 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1782 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1783 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1784 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1785 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1786 do {\ 1787 HWIO_INTLOCK(); \ 1788 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1789 HWIO_INTFREE();\ 1790 } while (0) 1791 1792 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1793 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1794 1795 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1796 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1797 1798 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1799 1800 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000000d4) 1801 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000000d4) 1802 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1803 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1804 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1805 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1806 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1807 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1808 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1809 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1810 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1811 do {\ 1812 HWIO_INTLOCK(); \ 1813 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1814 HWIO_INTFREE();\ 1815 } while (0) 1816 1817 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1818 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1819 1820 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1821 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1822 1823 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1824 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1825 1826 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1827 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1828 1829 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1830 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1831 1832 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1833 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1834 1835 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1836 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1837 1838 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1839 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1840 1841 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1842 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1843 1844 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1845 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1846 1847 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1848 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1849 1850 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1851 1852 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000e0) 1853 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000e0) 1854 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1855 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1856 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1857 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1858 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1859 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1860 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1861 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1862 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1863 do {\ 1864 HWIO_INTLOCK(); \ 1865 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1866 HWIO_INTFREE();\ 1867 } while (0) 1868 1869 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1870 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1871 1872 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1873 1874 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000e4) 1875 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000e4) 1876 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1877 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1878 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1879 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1880 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1881 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1882 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1883 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1884 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1885 do {\ 1886 HWIO_INTLOCK(); \ 1887 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1888 HWIO_INTFREE();\ 1889 } while (0) 1890 1891 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1892 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1893 1894 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1895 1896 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000f4) 1897 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000f4) 1898 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1899 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1900 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1901 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1902 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1903 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1904 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1905 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1906 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1907 do {\ 1908 HWIO_INTLOCK(); \ 1909 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1910 HWIO_INTFREE();\ 1911 } while (0) 1912 1913 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1914 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1915 1916 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1917 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1918 1919 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1920 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1921 1922 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1923 1924 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000f8) 1925 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000f8) 1926 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1927 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1928 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1929 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1930 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1931 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1932 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1933 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1934 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1935 do {\ 1936 HWIO_INTLOCK(); \ 1937 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1938 HWIO_INTFREE();\ 1939 } while (0) 1940 1941 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1942 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1943 1944 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1945 1946 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000fc) 1947 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000fc) 1948 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1949 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1950 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1951 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1952 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1953 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1954 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1955 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1956 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1957 do {\ 1958 HWIO_INTLOCK(); \ 1959 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1960 HWIO_INTFREE();\ 1961 } while (0) 1962 1963 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1964 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1965 1966 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1967 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1968 1969 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1970 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1971 1972 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1973 1974 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000100) 1975 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000100) 1976 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1977 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1978 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1979 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1980 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1981 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1982 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1983 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1984 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1985 do {\ 1986 HWIO_INTLOCK(); \ 1987 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1988 HWIO_INTFREE();\ 1989 } while (0) 1990 1991 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1992 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1993 1994 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1995 1996 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000104) 1997 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000104) 1998 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1999 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2000 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2001 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2002 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2003 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2004 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2005 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2006 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2007 do {\ 2008 HWIO_INTLOCK(); \ 2009 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2010 HWIO_INTFREE();\ 2011 } while (0) 2012 2013 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2014 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2015 2016 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 2017 2018 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000108) 2019 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000108) 2020 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2021 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2022 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2023 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2024 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2025 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2026 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2027 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2028 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2029 do {\ 2030 HWIO_INTLOCK(); \ 2031 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2032 HWIO_INTFREE();\ 2033 } while (0) 2034 2035 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2036 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2037 2038 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2039 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2040 2041 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 2042 2043 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000010c) 2044 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000010c) 2045 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2046 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 2047 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 2048 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 2049 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 2050 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 2051 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 2052 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 2053 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2054 do {\ 2055 HWIO_INTLOCK(); \ 2056 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 2057 HWIO_INTFREE();\ 2058 } while (0) 2059 2060 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2061 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2062 2063 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 2064 2065 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000110) 2066 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000110) 2067 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2068 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 2069 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 2070 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 2071 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 2072 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 2073 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 2074 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 2075 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2076 do {\ 2077 HWIO_INTLOCK(); \ 2078 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 2079 HWIO_INTFREE();\ 2080 } while (0) 2081 2082 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2083 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2084 2085 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2086 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2087 2088 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 2089 2090 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000114) 2091 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000114) 2092 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 2093 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 2094 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 2095 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 2096 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 2097 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 2098 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 2099 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 2100 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 2101 do {\ 2102 HWIO_INTLOCK(); \ 2103 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 2104 HWIO_INTFREE();\ 2105 } while (0) 2106 2107 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2108 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 2109 2110 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 2111 2112 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000118) 2113 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000118) 2114 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2115 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 2116 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 2117 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 2118 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2119 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2120 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2121 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2122 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2123 do {\ 2124 HWIO_INTLOCK(); \ 2125 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 2126 HWIO_INTFREE();\ 2127 } while (0) 2128 2129 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2130 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2131 2132 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 2133 2134 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x0000011c) 2135 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x0000011c) 2136 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 2137 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 2138 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 2139 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 2140 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 2141 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 2142 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 2143 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 2144 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 2145 do {\ 2146 HWIO_INTLOCK(); \ 2147 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 2148 HWIO_INTFREE();\ 2149 } while (0) 2150 2151 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2152 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2153 2154 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 2155 2156 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x00000120) 2157 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x00000120) 2158 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x00ffffff 2159 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 2160 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 2161 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 2162 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 2163 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 2164 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 2165 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 2166 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 2167 do {\ 2168 HWIO_INTLOCK(); \ 2169 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 2170 HWIO_INTFREE();\ 2171 } while (0) 2172 2173 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2174 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2175 2176 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2177 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2178 2179 //// Register TCL_R0_SW2TCL2_RING_ID //// 2180 2181 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000124) 2182 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000124) 2183 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 2184 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 2185 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 2186 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 2187 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 2188 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 2189 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 2190 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 2191 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 2192 do {\ 2193 HWIO_INTLOCK(); \ 2194 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 2195 HWIO_INTFREE();\ 2196 } while (0) 2197 2198 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2199 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 2200 2201 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 2202 2203 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000128) 2204 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000128) 2205 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 2206 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 2207 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 2208 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 2209 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 2210 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 2211 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 2212 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 2213 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 2214 do {\ 2215 HWIO_INTLOCK(); \ 2216 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 2217 HWIO_INTFREE();\ 2218 } while (0) 2219 2220 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2221 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2222 2223 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2224 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2225 2226 //// Register TCL_R0_SW2TCL2_RING_MISC //// 2227 2228 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x0000012c) 2229 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x0000012c) 2230 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 2231 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 2232 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 2233 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 2234 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 2235 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 2236 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 2237 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 2238 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 2239 do {\ 2240 HWIO_INTLOCK(); \ 2241 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 2242 HWIO_INTFREE();\ 2243 } while (0) 2244 2245 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2246 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 2247 2248 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2249 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2250 2251 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2252 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2253 2254 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2255 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2256 2257 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2258 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 2259 2260 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2261 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2262 2263 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2264 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2265 2266 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2267 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2268 2269 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2270 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 2271 2272 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2273 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2274 2275 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2276 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2277 2278 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 2279 2280 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000138) 2281 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000138) 2282 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 2283 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 2284 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 2285 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 2286 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 2287 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 2288 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 2289 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 2290 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2291 do {\ 2292 HWIO_INTLOCK(); \ 2293 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 2294 HWIO_INTFREE();\ 2295 } while (0) 2296 2297 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2298 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2299 2300 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 2301 2302 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000013c) 2303 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000013c) 2304 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 2305 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 2306 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 2307 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 2308 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 2309 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 2310 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 2311 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 2312 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2313 do {\ 2314 HWIO_INTLOCK(); \ 2315 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 2316 HWIO_INTFREE();\ 2317 } while (0) 2318 2319 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2320 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2321 2322 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 2323 2324 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000014c) 2325 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000014c) 2326 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2327 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2328 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2329 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2330 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2331 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2332 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2333 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2334 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2335 do {\ 2336 HWIO_INTLOCK(); \ 2337 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2338 HWIO_INTFREE();\ 2339 } while (0) 2340 2341 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2342 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2343 2344 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2345 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2346 2347 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2348 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2349 2350 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 2351 2352 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000150) 2353 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000150) 2354 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2355 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2356 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2357 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2358 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2359 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2360 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2361 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2362 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2363 do {\ 2364 HWIO_INTLOCK(); \ 2365 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2366 HWIO_INTFREE();\ 2367 } while (0) 2368 2369 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2370 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2371 2372 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 2373 2374 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000154) 2375 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000154) 2376 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2377 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 2378 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 2379 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 2380 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2381 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2382 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2383 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2384 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2385 do {\ 2386 HWIO_INTLOCK(); \ 2387 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 2388 HWIO_INTFREE();\ 2389 } while (0) 2390 2391 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2392 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2393 2394 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2395 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2396 2397 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2398 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2399 2400 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 2401 2402 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000158) 2403 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000158) 2404 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2405 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2406 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2407 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2408 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2409 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2410 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2411 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2412 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2413 do {\ 2414 HWIO_INTLOCK(); \ 2415 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2416 HWIO_INTFREE();\ 2417 } while (0) 2418 2419 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2420 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2421 2422 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 2423 2424 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000015c) 2425 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000015c) 2426 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2427 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2428 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2429 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2430 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2431 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2432 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2433 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2434 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2435 do {\ 2436 HWIO_INTLOCK(); \ 2437 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2438 HWIO_INTFREE();\ 2439 } while (0) 2440 2441 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2442 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2443 2444 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 2445 2446 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000160) 2447 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000160) 2448 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2449 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2450 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2451 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2452 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2453 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2454 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2455 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2456 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2457 do {\ 2458 HWIO_INTLOCK(); \ 2459 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2460 HWIO_INTFREE();\ 2461 } while (0) 2462 2463 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2464 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2465 2466 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2467 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2468 2469 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 2470 2471 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000164) 2472 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000164) 2473 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2474 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 2475 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 2476 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 2477 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 2478 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 2479 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 2480 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 2481 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2482 do {\ 2483 HWIO_INTLOCK(); \ 2484 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 2485 HWIO_INTFREE();\ 2486 } while (0) 2487 2488 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2489 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2490 2491 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 2492 2493 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000168) 2494 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000168) 2495 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2496 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 2497 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 2498 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 2499 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 2500 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 2501 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 2502 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 2503 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2504 do {\ 2505 HWIO_INTLOCK(); \ 2506 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 2507 HWIO_INTFREE();\ 2508 } while (0) 2509 2510 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2511 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2512 2513 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2514 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2515 2516 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 2517 2518 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000016c) 2519 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000016c) 2520 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 2521 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 2522 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 2523 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 2524 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 2525 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 2526 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 2527 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 2528 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 2529 do {\ 2530 HWIO_INTLOCK(); \ 2531 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 2532 HWIO_INTFREE();\ 2533 } while (0) 2534 2535 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2536 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 2537 2538 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 2539 2540 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000170) 2541 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000170) 2542 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2543 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 2544 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 2545 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 2546 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2547 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2548 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2549 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2550 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2551 do {\ 2552 HWIO_INTLOCK(); \ 2553 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 2554 HWIO_INTFREE();\ 2555 } while (0) 2556 2557 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2558 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2559 2560 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 2561 2562 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000174) 2563 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000174) 2564 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 2565 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 2566 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 2567 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 2568 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 2569 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 2570 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 2571 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 2572 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 2573 do {\ 2574 HWIO_INTLOCK(); \ 2575 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 2576 HWIO_INTFREE();\ 2577 } while (0) 2578 2579 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2580 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2581 2582 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 2583 2584 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000178) 2585 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000178) 2586 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x00ffffff 2587 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 2588 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 2589 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 2590 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 2591 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 2592 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 2593 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 2594 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 2595 do {\ 2596 HWIO_INTLOCK(); \ 2597 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 2598 HWIO_INTFREE();\ 2599 } while (0) 2600 2601 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2602 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2603 2604 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2605 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2606 2607 //// Register TCL_R0_SW2TCL3_RING_ID //// 2608 2609 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000017c) 2610 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000017c) 2611 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 2612 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 2613 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 2614 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 2615 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 2616 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 2617 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 2618 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 2619 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 2620 do {\ 2621 HWIO_INTLOCK(); \ 2622 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 2623 HWIO_INTFREE();\ 2624 } while (0) 2625 2626 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2627 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 2628 2629 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 2630 2631 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000180) 2632 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000180) 2633 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 2634 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 2635 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 2636 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 2637 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 2638 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 2639 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 2640 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 2641 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 2642 do {\ 2643 HWIO_INTLOCK(); \ 2644 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 2645 HWIO_INTFREE();\ 2646 } while (0) 2647 2648 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2649 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2650 2651 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2652 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2653 2654 //// Register TCL_R0_SW2TCL3_RING_MISC //// 2655 2656 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000184) 2657 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000184) 2658 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 2659 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 2660 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 2661 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 2662 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 2663 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 2664 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 2665 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 2666 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 2667 do {\ 2668 HWIO_INTLOCK(); \ 2669 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 2670 HWIO_INTFREE();\ 2671 } while (0) 2672 2673 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2674 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 2675 2676 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2677 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2678 2679 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2680 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2681 2682 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2683 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2684 2685 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2686 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 2687 2688 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2689 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2690 2691 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2692 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2693 2694 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2695 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2696 2697 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2698 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 2699 2700 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2701 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2702 2703 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2704 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2705 2706 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 2707 2708 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000190) 2709 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000190) 2710 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2711 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2712 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2713 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2714 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2715 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2716 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2717 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2718 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2719 do {\ 2720 HWIO_INTLOCK(); \ 2721 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2722 HWIO_INTFREE();\ 2723 } while (0) 2724 2725 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2726 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2727 2728 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2729 2730 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000194) 2731 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000194) 2732 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2733 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2734 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2735 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2736 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2737 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2738 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2739 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2740 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2741 do {\ 2742 HWIO_INTLOCK(); \ 2743 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2744 HWIO_INTFREE();\ 2745 } while (0) 2746 2747 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2748 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2749 2750 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2751 2752 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001a4) 2753 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001a4) 2754 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2755 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2756 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2757 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2758 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2759 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2760 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2761 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2762 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2763 do {\ 2764 HWIO_INTLOCK(); \ 2765 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2766 HWIO_INTFREE();\ 2767 } while (0) 2768 2769 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2770 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2771 2772 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2773 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2774 2775 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2776 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2777 2778 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2779 2780 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001a8) 2781 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001a8) 2782 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2783 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2784 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2785 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2786 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2787 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2788 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2789 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2790 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2791 do {\ 2792 HWIO_INTLOCK(); \ 2793 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2794 HWIO_INTFREE();\ 2795 } while (0) 2796 2797 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2798 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2799 2800 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2801 2802 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001ac) 2803 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001ac) 2804 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2805 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2806 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2807 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2808 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2809 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2810 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2811 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2812 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2813 do {\ 2814 HWIO_INTLOCK(); \ 2815 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2816 HWIO_INTFREE();\ 2817 } while (0) 2818 2819 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2820 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2821 2822 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2823 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2824 2825 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2826 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2827 2828 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2829 2830 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001b0) 2831 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001b0) 2832 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2833 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2834 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2835 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2836 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2837 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2838 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2839 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2840 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2841 do {\ 2842 HWIO_INTLOCK(); \ 2843 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2844 HWIO_INTFREE();\ 2845 } while (0) 2846 2847 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2848 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2849 2850 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2851 2852 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b4) 2853 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b4) 2854 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2855 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2856 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2857 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2858 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2859 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2860 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2861 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2862 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2863 do {\ 2864 HWIO_INTLOCK(); \ 2865 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2866 HWIO_INTFREE();\ 2867 } while (0) 2868 2869 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2870 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2871 2872 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2873 2874 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001b8) 2875 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001b8) 2876 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2877 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2878 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2879 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2880 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2881 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2882 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2883 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2884 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2885 do {\ 2886 HWIO_INTLOCK(); \ 2887 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2888 HWIO_INTFREE();\ 2889 } while (0) 2890 2891 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2892 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2893 2894 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2895 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2896 2897 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2898 2899 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001bc) 2900 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001bc) 2901 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2902 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2903 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2904 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2905 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2906 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2907 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2908 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2909 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2910 do {\ 2911 HWIO_INTLOCK(); \ 2912 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2913 HWIO_INTFREE();\ 2914 } while (0) 2915 2916 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2917 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2918 2919 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2920 2921 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001c0) 2922 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001c0) 2923 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2924 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2925 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2926 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2927 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2928 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2929 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2930 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2931 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2932 do {\ 2933 HWIO_INTLOCK(); \ 2934 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2935 HWIO_INTFREE();\ 2936 } while (0) 2937 2938 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2939 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2940 2941 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2942 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2943 2944 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2945 2946 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x000001c4) 2947 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x000001c4) 2948 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2949 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2950 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2951 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2952 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2953 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2954 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2955 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2956 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2957 do {\ 2958 HWIO_INTLOCK(); \ 2959 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2960 HWIO_INTFREE();\ 2961 } while (0) 2962 2963 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2964 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2965 2966 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2967 2968 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001c8) 2969 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001c8) 2970 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2971 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2972 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2973 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2974 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2975 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2976 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2977 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2978 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2979 do {\ 2980 HWIO_INTLOCK(); \ 2981 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2982 HWIO_INTFREE();\ 2983 } while (0) 2984 2985 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2986 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2987 2988 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// 2989 2990 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x000001cc) 2991 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x000001cc) 2992 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff 2993 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 2994 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ 2995 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) 2996 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ 2997 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 2998 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ 2999 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) 3000 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 3001 do {\ 3002 HWIO_INTLOCK(); \ 3003 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ 3004 HWIO_INTFREE();\ 3005 } while (0) 3006 3007 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3008 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3009 3010 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// 3011 3012 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x000001d0) 3013 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x000001d0) 3014 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x00ffffff 3015 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 3016 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ 3017 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) 3018 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ 3019 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 3020 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ 3021 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) 3022 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 3023 do {\ 3024 HWIO_INTLOCK(); \ 3025 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ 3026 HWIO_INTFREE();\ 3027 } while (0) 3028 3029 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3030 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3031 3032 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3033 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3034 3035 //// Register TCL_R0_SW2TCL_CMD_RING_ID //// 3036 3037 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x000001d4) 3038 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x000001d4) 3039 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff 3040 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 3041 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ 3042 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) 3043 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ 3044 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 3045 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ 3046 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) 3047 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ 3048 do {\ 3049 HWIO_INTLOCK(); \ 3050 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ 3051 HWIO_INTFREE();\ 3052 } while (0) 3053 3054 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3055 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 3056 3057 //// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// 3058 3059 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x000001d8) 3060 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x000001d8) 3061 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff 3062 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 3063 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ 3064 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) 3065 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ 3066 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 3067 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ 3068 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) 3069 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ 3070 do {\ 3071 HWIO_INTLOCK(); \ 3072 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ 3073 HWIO_INTFREE();\ 3074 } while (0) 3075 3076 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3077 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3078 3079 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3080 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3081 3082 //// Register TCL_R0_SW2TCL_CMD_RING_MISC //// 3083 3084 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x000001dc) 3085 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x000001dc) 3086 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x003fffff 3087 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 3088 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ 3089 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) 3090 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ 3091 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 3092 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ 3093 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) 3094 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ 3095 do {\ 3096 HWIO_INTLOCK(); \ 3097 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ 3098 HWIO_INTFREE();\ 3099 } while (0) 3100 3101 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3102 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 3103 3104 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3105 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3106 3107 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3108 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3109 3110 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3111 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3112 3113 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3114 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 3115 3116 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3117 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3118 3119 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3120 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3121 3122 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3123 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3124 3125 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3126 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 3127 3128 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3129 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3130 3131 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3132 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3133 3134 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// 3135 3136 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001e8) 3137 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001e8) 3138 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 3139 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 3140 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ 3141 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) 3142 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 3143 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 3144 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 3145 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 3146 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 3147 do {\ 3148 HWIO_INTLOCK(); \ 3149 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ 3150 HWIO_INTFREE();\ 3151 } while (0) 3152 3153 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3155 3156 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// 3157 3158 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001ec) 3159 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001ec) 3160 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 3161 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 3162 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ 3163 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) 3164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 3165 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 3166 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 3167 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 3168 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3169 do {\ 3170 HWIO_INTLOCK(); \ 3171 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ 3172 HWIO_INTFREE();\ 3173 } while (0) 3174 3175 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3176 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3177 3178 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 3179 3180 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001fc) 3181 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001fc) 3182 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3183 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3184 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3185 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3186 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3187 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3188 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3189 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3190 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3191 do {\ 3192 HWIO_INTLOCK(); \ 3193 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3194 HWIO_INTFREE();\ 3195 } while (0) 3196 3197 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3198 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3199 3200 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3201 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3202 3203 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3204 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3205 3206 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 3207 3208 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000200) 3209 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000200) 3210 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3211 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3212 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3213 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3214 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3215 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3216 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3217 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3218 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3219 do {\ 3220 HWIO_INTLOCK(); \ 3221 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3222 HWIO_INTFREE();\ 3223 } while (0) 3224 3225 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3226 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3227 3228 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// 3229 3230 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000204) 3231 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000204) 3232 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3233 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 3234 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 3235 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) 3236 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3237 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3238 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3239 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3240 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3241 do {\ 3242 HWIO_INTLOCK(); \ 3243 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 3244 HWIO_INTFREE();\ 3245 } while (0) 3246 3247 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3248 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3249 3250 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3251 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3252 3253 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3254 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3255 3256 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// 3257 3258 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000208) 3259 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000208) 3260 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3261 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3262 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3263 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3264 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3265 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3266 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3267 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3268 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3269 do {\ 3270 HWIO_INTLOCK(); \ 3271 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3272 HWIO_INTFREE();\ 3273 } while (0) 3274 3275 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3276 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3277 3278 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// 3279 3280 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000020c) 3281 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000020c) 3282 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3283 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3284 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3285 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3286 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3287 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3288 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3289 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3290 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3291 do {\ 3292 HWIO_INTLOCK(); \ 3293 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3294 HWIO_INTFREE();\ 3295 } while (0) 3296 3297 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3298 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3299 3300 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// 3301 3302 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210) 3303 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210) 3304 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3305 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3306 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3307 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3308 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3309 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3310 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3311 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3312 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3313 do {\ 3314 HWIO_INTLOCK(); \ 3315 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3316 HWIO_INTFREE();\ 3317 } while (0) 3318 3319 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3320 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3321 3322 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3323 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3324 3325 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// 3326 3327 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000214) 3328 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000214) 3329 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3330 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 3331 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ 3332 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) 3333 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 3334 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 3335 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 3336 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 3337 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3338 do {\ 3339 HWIO_INTLOCK(); \ 3340 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 3341 HWIO_INTFREE();\ 3342 } while (0) 3343 3344 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3345 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3346 3347 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// 3348 3349 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000218) 3350 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000218) 3351 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3352 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 3353 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ 3354 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) 3355 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 3356 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 3357 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 3358 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 3359 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3360 do {\ 3361 HWIO_INTLOCK(); \ 3362 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 3363 HWIO_INTFREE();\ 3364 } while (0) 3365 3366 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3367 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3368 3369 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3370 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3371 3372 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// 3373 3374 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x0000021c) 3375 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x0000021c) 3376 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff 3377 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 3378 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ 3379 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) 3380 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ 3381 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 3382 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ 3383 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) 3384 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 3385 do {\ 3386 HWIO_INTLOCK(); \ 3387 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ 3388 HWIO_INTFREE();\ 3389 } while (0) 3390 3391 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3392 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 3393 3394 //// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// 3395 3396 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000220) 3397 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000220) 3398 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3399 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 3400 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 3401 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) 3402 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3403 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3404 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3405 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3406 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3407 do {\ 3408 HWIO_INTLOCK(); \ 3409 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 3410 HWIO_INTFREE();\ 3411 } while (0) 3412 3413 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3414 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3415 3416 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 3417 3418 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000224) 3419 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000224) 3420 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 3421 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 3422 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 3423 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 3424 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 3425 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 3426 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 3427 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 3428 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 3429 do {\ 3430 HWIO_INTLOCK(); \ 3431 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 3432 HWIO_INTFREE();\ 3433 } while (0) 3434 3435 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3436 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3437 3438 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 3439 3440 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000228) 3441 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000228) 3442 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 3443 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 3444 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 3445 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 3446 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 3447 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 3448 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 3449 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 3450 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 3451 do {\ 3452 HWIO_INTLOCK(); \ 3453 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 3454 HWIO_INTFREE();\ 3455 } while (0) 3456 3457 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3458 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3459 3460 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3461 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3462 3463 //// Register TCL_R0_FW2TCL1_RING_ID //// 3464 3465 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x0000022c) 3466 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x0000022c) 3467 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 3468 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 3469 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 3470 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 3471 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 3472 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 3473 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 3474 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 3475 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 3476 do {\ 3477 HWIO_INTLOCK(); \ 3478 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 3479 HWIO_INTFREE();\ 3480 } while (0) 3481 3482 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3483 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 3484 3485 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 3486 3487 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000230) 3488 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000230) 3489 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 3490 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 3491 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 3492 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 3493 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 3494 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 3495 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 3496 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 3497 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 3498 do {\ 3499 HWIO_INTLOCK(); \ 3500 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 3501 HWIO_INTFREE();\ 3502 } while (0) 3503 3504 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3505 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3506 3507 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3508 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3509 3510 //// Register TCL_R0_FW2TCL1_RING_MISC //// 3511 3512 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000234) 3513 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000234) 3514 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 3515 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 3516 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 3517 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 3518 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 3519 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 3520 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 3521 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 3522 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 3523 do {\ 3524 HWIO_INTLOCK(); \ 3525 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 3526 HWIO_INTFREE();\ 3527 } while (0) 3528 3529 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3530 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3531 3532 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3533 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3534 3535 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3536 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3537 3538 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3539 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3540 3541 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3542 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3543 3544 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3545 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3546 3547 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3548 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3549 3550 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3551 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3552 3553 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3554 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 3555 3556 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3557 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3558 3559 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3560 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3561 3562 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 3563 3564 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000240) 3565 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000240) 3566 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 3567 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 3568 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 3569 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 3570 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 3571 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 3572 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 3573 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 3574 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 3575 do {\ 3576 HWIO_INTLOCK(); \ 3577 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 3578 HWIO_INTFREE();\ 3579 } while (0) 3580 3581 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 3582 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 3583 3584 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 3585 3586 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000244) 3587 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000244) 3588 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 3589 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 3590 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 3591 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 3592 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 3593 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 3594 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 3595 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 3596 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3597 do {\ 3598 HWIO_INTLOCK(); \ 3599 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 3600 HWIO_INTFREE();\ 3601 } while (0) 3602 3603 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3604 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3605 3606 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 3607 3608 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000254) 3609 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000254) 3610 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3611 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3612 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3613 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3614 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3615 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3616 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3617 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3618 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3619 do {\ 3620 HWIO_INTLOCK(); \ 3621 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3622 HWIO_INTFREE();\ 3623 } while (0) 3624 3625 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3626 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3627 3628 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3629 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3630 3631 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3632 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3633 3634 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 3635 3636 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000258) 3637 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000258) 3638 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3639 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3640 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3641 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3642 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3643 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3644 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3645 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3646 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3647 do {\ 3648 HWIO_INTLOCK(); \ 3649 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3650 HWIO_INTFREE();\ 3651 } while (0) 3652 3653 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3654 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3655 3656 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 3657 3658 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000025c) 3659 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000025c) 3660 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3661 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 3662 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 3663 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 3664 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3665 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3666 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3667 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3668 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3669 do {\ 3670 HWIO_INTLOCK(); \ 3671 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3672 HWIO_INTFREE();\ 3673 } while (0) 3674 3675 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3676 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3677 3678 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3679 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3680 3681 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3682 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3683 3684 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 3685 3686 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000260) 3687 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000260) 3688 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3689 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3690 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3691 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3692 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3693 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3694 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3695 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3696 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3697 do {\ 3698 HWIO_INTLOCK(); \ 3699 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3700 HWIO_INTFREE();\ 3701 } while (0) 3702 3703 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3704 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3705 3706 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 3707 3708 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000264) 3709 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000264) 3710 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3711 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3712 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3713 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3714 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3715 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3716 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3717 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3718 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3719 do {\ 3720 HWIO_INTLOCK(); \ 3721 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3722 HWIO_INTFREE();\ 3723 } while (0) 3724 3725 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3726 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3727 3728 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3729 3730 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000268) 3731 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000268) 3732 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3733 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3734 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3735 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3736 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3737 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3738 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3739 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3740 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3741 do {\ 3742 HWIO_INTLOCK(); \ 3743 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3744 HWIO_INTFREE();\ 3745 } while (0) 3746 3747 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3748 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3749 3750 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3751 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3752 3753 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3754 3755 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000026c) 3756 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000026c) 3757 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3758 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3759 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3760 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3761 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3762 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3763 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3764 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3765 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3766 do {\ 3767 HWIO_INTLOCK(); \ 3768 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3769 HWIO_INTFREE();\ 3770 } while (0) 3771 3772 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3773 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3774 3775 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3776 3777 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000270) 3778 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000270) 3779 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3780 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3781 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3782 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3783 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3784 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3785 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3786 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3787 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3788 do {\ 3789 HWIO_INTLOCK(); \ 3790 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3791 HWIO_INTFREE();\ 3792 } while (0) 3793 3794 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3795 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3796 3797 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3798 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3799 3800 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3801 3802 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000274) 3803 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000274) 3804 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3805 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3806 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3807 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3808 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3809 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3810 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3811 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3812 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3813 do {\ 3814 HWIO_INTLOCK(); \ 3815 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3816 HWIO_INTFREE();\ 3817 } while (0) 3818 3819 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3820 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3821 3822 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3823 3824 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000278) 3825 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000278) 3826 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3827 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3828 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3829 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3830 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3831 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3832 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3833 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3834 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3835 do {\ 3836 HWIO_INTLOCK(); \ 3837 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3838 HWIO_INTFREE();\ 3839 } while (0) 3840 3841 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3842 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3843 3844 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3845 3846 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000027c) 3847 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000027c) 3848 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3849 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3850 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3851 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3852 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3853 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3854 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3855 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3856 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3857 do {\ 3858 HWIO_INTLOCK(); \ 3859 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3860 HWIO_INTFREE();\ 3861 } while (0) 3862 3863 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3864 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3865 3866 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3867 3868 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000280) 3869 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000280) 3870 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3871 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3872 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3873 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3874 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3875 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3876 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3877 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3878 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3879 do {\ 3880 HWIO_INTLOCK(); \ 3881 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3882 HWIO_INTFREE();\ 3883 } while (0) 3884 3885 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3886 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3887 3888 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3889 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3890 3891 //// Register TCL_R0_TCL2TQM_RING_ID //// 3892 3893 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000284) 3894 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000284) 3895 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3896 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3897 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3898 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3899 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3900 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3901 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3902 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3903 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3904 do {\ 3905 HWIO_INTLOCK(); \ 3906 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3907 HWIO_INTFREE();\ 3908 } while (0) 3909 3910 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3911 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3912 3913 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3914 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3915 3916 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3917 3918 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000288) 3919 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000288) 3920 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3921 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3922 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3923 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3924 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3925 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3926 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3927 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3928 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3929 do {\ 3930 HWIO_INTLOCK(); \ 3931 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3932 HWIO_INTFREE();\ 3933 } while (0) 3934 3935 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3936 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3937 3938 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3939 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3940 3941 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3942 3943 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000028c) 3944 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000028c) 3945 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3946 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3947 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3948 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3949 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3950 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3951 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3952 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3953 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3954 do {\ 3955 HWIO_INTLOCK(); \ 3956 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3957 HWIO_INTFREE();\ 3958 } while (0) 3959 3960 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3961 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3962 3963 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3964 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3965 3966 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3967 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3968 3969 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3970 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3971 3972 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3973 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3974 3975 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3976 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3977 3978 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3979 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3980 3981 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3982 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3983 3984 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3985 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3986 3987 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3988 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3989 3990 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3991 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3992 3993 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3994 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3995 3996 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3997 3998 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000290) 3999 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000290) 4000 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 4001 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 4002 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 4003 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 4004 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 4005 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 4006 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 4007 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 4008 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4009 do {\ 4010 HWIO_INTLOCK(); \ 4011 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 4012 HWIO_INTFREE();\ 4013 } while (0) 4014 4015 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4016 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4017 4018 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 4019 4020 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000294) 4021 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000294) 4022 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 4023 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 4024 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 4025 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 4026 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 4027 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 4028 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 4029 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 4030 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4031 do {\ 4032 HWIO_INTLOCK(); \ 4033 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 4034 HWIO_INTFREE();\ 4035 } while (0) 4036 4037 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4038 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4039 4040 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 4041 4042 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002a0) 4043 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002a0) 4044 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4045 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 4046 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 4047 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 4048 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4049 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4050 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4051 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4052 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4053 do {\ 4054 HWIO_INTLOCK(); \ 4055 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 4056 HWIO_INTFREE();\ 4057 } while (0) 4058 4059 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4060 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4061 4062 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4063 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4064 4065 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4066 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4067 4068 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 4069 4070 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002a4) 4071 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002a4) 4072 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4073 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 4074 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 4075 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 4076 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4077 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4078 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4079 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4080 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4081 do {\ 4082 HWIO_INTLOCK(); \ 4083 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 4084 HWIO_INTFREE();\ 4085 } while (0) 4086 4087 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4088 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4089 4090 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4091 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4092 4093 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4094 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4095 4096 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 4097 4098 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002a8) 4099 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002a8) 4100 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4101 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 4102 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4103 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 4104 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4105 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4106 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4107 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4108 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4109 do {\ 4110 HWIO_INTLOCK(); \ 4111 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4112 HWIO_INTFREE();\ 4113 } while (0) 4114 4115 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4116 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4117 4118 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 4119 4120 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002d0) 4121 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002d0) 4122 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4123 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 4124 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 4125 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 4126 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4127 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4128 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4129 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4130 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4131 do {\ 4132 HWIO_INTLOCK(); \ 4133 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 4134 HWIO_INTFREE();\ 4135 } while (0) 4136 4137 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4138 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4139 4140 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 4141 4142 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000002d4) 4143 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000002d4) 4144 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 4145 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 4146 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 4147 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 4148 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 4149 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 4150 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 4151 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 4152 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 4153 do {\ 4154 HWIO_INTLOCK(); \ 4155 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 4156 HWIO_INTFREE();\ 4157 } while (0) 4158 4159 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4160 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4161 4162 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 4163 4164 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000002d8) 4165 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000002d8) 4166 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 4167 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 4168 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 4169 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 4170 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 4171 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 4172 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 4173 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 4174 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 4175 do {\ 4176 HWIO_INTLOCK(); \ 4177 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 4178 HWIO_INTFREE();\ 4179 } while (0) 4180 4181 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4182 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4183 4184 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4185 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4186 4187 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 4188 4189 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000002dc) 4190 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000002dc) 4191 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 4192 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 4193 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 4194 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 4195 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 4196 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 4197 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 4198 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 4199 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 4200 do {\ 4201 HWIO_INTLOCK(); \ 4202 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 4203 HWIO_INTFREE();\ 4204 } while (0) 4205 4206 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 4207 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 4208 4209 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4210 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 4211 4212 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 4213 4214 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000002e0) 4215 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000002e0) 4216 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 4217 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 4218 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 4219 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 4220 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 4221 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 4222 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 4223 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 4224 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 4225 do {\ 4226 HWIO_INTLOCK(); \ 4227 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 4228 HWIO_INTFREE();\ 4229 } while (0) 4230 4231 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4232 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4233 4234 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4235 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4236 4237 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 4238 4239 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000002e4) 4240 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000002e4) 4241 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 4242 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 4243 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 4244 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 4245 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 4246 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 4247 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 4248 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 4249 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 4250 do {\ 4251 HWIO_INTLOCK(); \ 4252 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 4253 HWIO_INTFREE();\ 4254 } while (0) 4255 4256 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4257 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 4258 4259 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4260 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 4261 4262 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4263 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4264 4265 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4266 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4267 4268 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4269 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4270 4271 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4272 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 4273 4274 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4275 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4276 4277 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4278 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4279 4280 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4281 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4282 4283 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4284 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 4285 4286 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4287 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4288 4289 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4290 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4291 4292 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 4293 4294 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002e8) 4295 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002e8) 4296 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 4297 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 4298 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 4299 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 4300 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 4301 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 4302 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 4303 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 4304 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4305 do {\ 4306 HWIO_INTLOCK(); \ 4307 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 4308 HWIO_INTFREE();\ 4309 } while (0) 4310 4311 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4312 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4313 4314 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 4315 4316 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002ec) 4317 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002ec) 4318 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 4319 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 4320 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 4321 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 4322 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 4323 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 4324 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 4325 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 4326 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4327 do {\ 4328 HWIO_INTLOCK(); \ 4329 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 4330 HWIO_INTFREE();\ 4331 } while (0) 4332 4333 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4334 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4335 4336 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 4337 4338 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002f8) 4339 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002f8) 4340 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4341 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 4342 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 4343 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 4344 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4345 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4346 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4347 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4348 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4349 do {\ 4350 HWIO_INTLOCK(); \ 4351 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 4352 HWIO_INTFREE();\ 4353 } while (0) 4354 4355 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4356 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4357 4358 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4359 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4360 4361 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4362 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4363 4364 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 4365 4366 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002fc) 4367 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002fc) 4368 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4369 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 4370 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 4371 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 4372 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4373 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4374 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4375 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4376 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4377 do {\ 4378 HWIO_INTLOCK(); \ 4379 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 4380 HWIO_INTFREE();\ 4381 } while (0) 4382 4383 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4384 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4385 4386 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4387 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4388 4389 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4390 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4391 4392 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 4393 4394 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000300) 4395 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000300) 4396 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4397 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 4398 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4399 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 4400 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4401 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4402 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4403 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4404 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4405 do {\ 4406 HWIO_INTLOCK(); \ 4407 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4408 HWIO_INTFREE();\ 4409 } while (0) 4410 4411 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4412 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4413 4414 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 4415 4416 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000031c) 4417 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000031c) 4418 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4419 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 4420 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 4421 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 4422 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 4423 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 4424 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 4425 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 4426 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4427 do {\ 4428 HWIO_INTLOCK(); \ 4429 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 4430 HWIO_INTFREE();\ 4431 } while (0) 4432 4433 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4434 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4435 4436 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 4437 4438 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000320) 4439 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000320) 4440 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4441 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 4442 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 4443 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 4444 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 4445 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 4446 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 4447 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 4448 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4449 do {\ 4450 HWIO_INTLOCK(); \ 4451 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 4452 HWIO_INTFREE();\ 4453 } while (0) 4454 4455 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4456 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4457 4458 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4459 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4460 4461 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 4462 4463 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000324) 4464 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000324) 4465 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 4466 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 4467 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 4468 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 4469 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 4470 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 4471 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 4472 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 4473 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 4474 do {\ 4475 HWIO_INTLOCK(); \ 4476 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 4477 HWIO_INTFREE();\ 4478 } while (0) 4479 4480 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4481 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 4482 4483 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 4484 4485 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000328) 4486 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000328) 4487 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4488 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 4489 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 4490 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 4491 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4492 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4493 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4494 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4495 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4496 do {\ 4497 HWIO_INTLOCK(); \ 4498 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 4499 HWIO_INTFREE();\ 4500 } while (0) 4501 4502 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4503 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4504 4505 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 4506 4507 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x0000032c) 4508 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x0000032c) 4509 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 4510 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 4511 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 4512 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 4513 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 4514 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 4515 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 4516 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 4517 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 4518 do {\ 4519 HWIO_INTLOCK(); \ 4520 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 4521 HWIO_INTFREE();\ 4522 } while (0) 4523 4524 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4525 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4526 4527 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 4528 4529 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000330) 4530 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000330) 4531 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 4532 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 4533 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 4534 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 4535 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 4536 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 4537 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 4538 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 4539 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 4540 do {\ 4541 HWIO_INTLOCK(); \ 4542 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 4543 HWIO_INTFREE();\ 4544 } while (0) 4545 4546 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4547 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4548 4549 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4550 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4551 4552 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 4553 4554 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000334) 4555 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000334) 4556 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 4557 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 4558 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 4559 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 4560 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 4561 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 4562 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 4563 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 4564 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 4565 do {\ 4566 HWIO_INTLOCK(); \ 4567 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 4568 HWIO_INTFREE();\ 4569 } while (0) 4570 4571 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 4572 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 4573 4574 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4575 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 4576 4577 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 4578 4579 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000338) 4580 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000338) 4581 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 4582 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 4583 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 4584 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 4585 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 4586 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 4587 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 4588 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 4589 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 4590 do {\ 4591 HWIO_INTLOCK(); \ 4592 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 4593 HWIO_INTFREE();\ 4594 } while (0) 4595 4596 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4597 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4598 4599 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4600 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4601 4602 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 4603 4604 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000033c) 4605 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000033c) 4606 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 4607 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 4608 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 4609 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 4610 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 4611 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 4612 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 4613 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 4614 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 4615 do {\ 4616 HWIO_INTLOCK(); \ 4617 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 4618 HWIO_INTFREE();\ 4619 } while (0) 4620 4621 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4622 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 4623 4624 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4625 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 4626 4627 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4628 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4629 4630 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4631 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4632 4633 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4634 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4635 4636 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4637 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 4638 4639 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4640 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4641 4642 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4643 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4644 4645 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4646 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4647 4648 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4649 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 4650 4651 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4652 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4653 4654 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4655 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4656 4657 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 4658 4659 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000340) 4660 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000340) 4661 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4662 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 4663 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 4664 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 4665 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 4666 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 4667 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 4668 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 4669 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4670 do {\ 4671 HWIO_INTLOCK(); \ 4672 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 4673 HWIO_INTFREE();\ 4674 } while (0) 4675 4676 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4677 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4678 4679 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 4680 4681 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000344) 4682 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000344) 4683 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4684 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 4685 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 4686 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 4687 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 4688 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 4689 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 4690 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 4691 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4692 do {\ 4693 HWIO_INTLOCK(); \ 4694 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 4695 HWIO_INTFREE();\ 4696 } while (0) 4697 4698 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4699 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4700 4701 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 4702 4703 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000350) 4704 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000350) 4705 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4706 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 4707 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 4708 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 4709 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4710 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4711 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4712 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4713 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4714 do {\ 4715 HWIO_INTLOCK(); \ 4716 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4717 HWIO_INTFREE();\ 4718 } while (0) 4719 4720 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4721 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4722 4723 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4724 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4725 4726 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4727 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4728 4729 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4730 4731 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000354) 4732 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000354) 4733 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4734 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4735 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4736 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4737 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4738 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4739 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4740 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4741 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4742 do {\ 4743 HWIO_INTLOCK(); \ 4744 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4745 HWIO_INTFREE();\ 4746 } while (0) 4747 4748 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4749 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4750 4751 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4752 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4753 4754 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4755 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4756 4757 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4758 4759 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000358) 4760 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000358) 4761 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4762 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4763 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4764 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4765 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4766 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4767 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4768 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4769 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4770 do {\ 4771 HWIO_INTLOCK(); \ 4772 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4773 HWIO_INTFREE();\ 4774 } while (0) 4775 4776 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4777 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4778 4779 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4780 4781 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000374) 4782 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000374) 4783 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4784 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4785 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4786 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4787 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4788 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4789 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4790 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4791 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4792 do {\ 4793 HWIO_INTLOCK(); \ 4794 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4795 HWIO_INTFREE();\ 4796 } while (0) 4797 4798 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4799 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4800 4801 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4802 4803 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000378) 4804 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000378) 4805 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4806 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4807 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4808 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4809 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4810 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4811 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4812 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4813 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4814 do {\ 4815 HWIO_INTLOCK(); \ 4816 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4817 HWIO_INTFREE();\ 4818 } while (0) 4819 4820 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4821 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4822 4823 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4824 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4825 4826 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4827 4828 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000037c) 4829 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000037c) 4830 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4831 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4832 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4833 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4834 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4835 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4836 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4837 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4838 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4839 do {\ 4840 HWIO_INTLOCK(); \ 4841 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4842 HWIO_INTFREE();\ 4843 } while (0) 4844 4845 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4846 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4847 4848 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4849 4850 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000380) 4851 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000380) 4852 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4853 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4854 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4855 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4856 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4857 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4858 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4859 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4860 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4861 do {\ 4862 HWIO_INTLOCK(); \ 4863 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4864 HWIO_INTFREE();\ 4865 } while (0) 4866 4867 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4868 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4869 4870 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4871 4872 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000384) 4873 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000384) 4874 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4875 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4876 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4877 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4878 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4879 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4880 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4881 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4882 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4883 do {\ 4884 HWIO_INTLOCK(); \ 4885 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4886 HWIO_INTFREE();\ 4887 } while (0) 4888 4889 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4890 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4891 4892 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4893 4894 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000388) 4895 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000388) 4896 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4897 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4898 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4899 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4900 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4901 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4902 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4903 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4904 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4905 do {\ 4906 HWIO_INTLOCK(); \ 4907 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4908 HWIO_INTFREE();\ 4909 } while (0) 4910 4911 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4912 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4913 4914 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4915 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4916 4917 //// Register TCL_R0_TCL2FW_RING_ID //// 4918 4919 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000038c) 4920 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000038c) 4921 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4922 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4923 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4924 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4925 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4926 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4927 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4928 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4929 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4930 do {\ 4931 HWIO_INTLOCK(); \ 4932 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4933 HWIO_INTFREE();\ 4934 } while (0) 4935 4936 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4937 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4938 4939 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4940 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4941 4942 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4943 4944 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000390) 4945 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000390) 4946 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4947 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4948 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4949 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4950 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4951 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4952 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4953 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4954 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4955 do {\ 4956 HWIO_INTLOCK(); \ 4957 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4958 HWIO_INTFREE();\ 4959 } while (0) 4960 4961 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4962 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4963 4964 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4965 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4966 4967 //// Register TCL_R0_TCL2FW_RING_MISC //// 4968 4969 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000394) 4970 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000394) 4971 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4972 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4973 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4974 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4975 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4976 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4977 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4978 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4979 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4980 do {\ 4981 HWIO_INTLOCK(); \ 4982 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4983 HWIO_INTFREE();\ 4984 } while (0) 4985 4986 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4987 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4988 4989 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4990 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4991 4992 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4993 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4994 4995 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4996 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4997 4998 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4999 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5000 5001 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5002 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 5003 5004 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5005 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5006 5007 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5008 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5009 5010 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5011 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5012 5013 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5014 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 5015 5016 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5017 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5018 5019 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5020 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5021 5022 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 5023 5024 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000398) 5025 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000398) 5026 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 5027 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 5028 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 5029 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 5030 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 5031 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 5032 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 5033 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 5034 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5035 do {\ 5036 HWIO_INTLOCK(); \ 5037 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 5038 HWIO_INTFREE();\ 5039 } while (0) 5040 5041 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5042 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5043 5044 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 5045 5046 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000039c) 5047 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000039c) 5048 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 5049 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 5050 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 5051 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 5052 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 5053 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 5054 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 5055 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 5056 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5057 do {\ 5058 HWIO_INTLOCK(); \ 5059 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 5060 HWIO_INTFREE();\ 5061 } while (0) 5062 5063 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5064 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5065 5066 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 5067 5068 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003a8) 5069 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003a8) 5070 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5071 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 5072 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 5073 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 5074 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5075 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5076 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5077 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5078 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5079 do {\ 5080 HWIO_INTLOCK(); \ 5081 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 5082 HWIO_INTFREE();\ 5083 } while (0) 5084 5085 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5086 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5087 5088 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5089 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5090 5091 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5092 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5093 5094 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 5095 5096 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003ac) 5097 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003ac) 5098 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5099 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 5100 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 5101 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 5102 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5103 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5104 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5105 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5106 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5107 do {\ 5108 HWIO_INTLOCK(); \ 5109 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 5110 HWIO_INTFREE();\ 5111 } while (0) 5112 5113 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5114 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5115 5116 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5117 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5118 5119 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5120 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5121 5122 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 5123 5124 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003b0) 5125 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003b0) 5126 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5127 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 5128 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5129 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 5130 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5131 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5132 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5133 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5134 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5135 do {\ 5136 HWIO_INTLOCK(); \ 5137 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5138 HWIO_INTFREE();\ 5139 } while (0) 5140 5141 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5142 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5143 5144 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 5145 5146 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003d8) 5147 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003d8) 5148 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5149 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 5150 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 5151 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 5152 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5153 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5154 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5155 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5156 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5157 do {\ 5158 HWIO_INTLOCK(); \ 5159 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 5160 HWIO_INTFREE();\ 5161 } while (0) 5162 5163 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5164 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5165 5166 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 5167 5168 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000003dc) 5169 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000003dc) 5170 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 5171 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 5172 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 5173 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 5174 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 5175 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 5176 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 5177 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 5178 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 5179 do {\ 5180 HWIO_INTLOCK(); \ 5181 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 5182 HWIO_INTFREE();\ 5183 } while (0) 5184 5185 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 5186 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 5187 5188 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 5189 5190 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000003e0) 5191 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000003e0) 5192 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 5193 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 5194 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 5195 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 5196 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 5197 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 5198 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 5199 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 5200 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 5201 do {\ 5202 HWIO_INTLOCK(); \ 5203 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 5204 HWIO_INTFREE();\ 5205 } while (0) 5206 5207 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 5208 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 5209 5210 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 5211 5212 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000003e4) 5213 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000003e4) 5214 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 5215 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 5216 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 5217 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 5218 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 5219 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 5220 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 5221 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 5222 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 5223 do {\ 5224 HWIO_INTLOCK(); \ 5225 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 5226 HWIO_INTFREE();\ 5227 } while (0) 5228 5229 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 5230 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 5231 5232 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 5233 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 5234 5235 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 5236 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 5237 5238 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 5239 5240 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000003e8) 5241 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000003e8) 5242 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 5243 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 5244 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 5245 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 5246 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 5247 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 5248 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 5249 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 5250 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5251 do {\ 5252 HWIO_INTLOCK(); \ 5253 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 5254 HWIO_INTFREE();\ 5255 } while (0) 5256 5257 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5258 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5259 5260 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 5261 5262 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000003ec) 5263 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000003ec) 5264 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 5265 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 5266 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 5267 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 5268 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 5269 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 5270 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 5271 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 5272 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 5273 do {\ 5274 HWIO_INTLOCK(); \ 5275 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 5276 HWIO_INTFREE();\ 5277 } while (0) 5278 5279 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 5280 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 5281 5282 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff 5283 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 5284 5285 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 5286 5287 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000003f0) 5288 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000003f0) 5289 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 5290 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 5291 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 5292 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 5293 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 5294 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 5295 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 5296 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 5297 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 5298 do {\ 5299 HWIO_INTLOCK(); \ 5300 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 5301 HWIO_INTFREE();\ 5302 } while (0) 5303 5304 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 5305 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 5306 5307 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 5308 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 5309 5310 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 5311 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 5312 5313 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 5314 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 5315 5316 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 5317 5318 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000003f4) 5319 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000003f4) 5320 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 5321 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 5322 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 5323 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 5324 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 5325 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 5326 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 5327 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 5328 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 5329 do {\ 5330 HWIO_INTLOCK(); \ 5331 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 5332 HWIO_INTFREE();\ 5333 } while (0) 5334 5335 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 5336 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 5337 5338 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 5339 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 5340 5341 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 5342 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 5343 5344 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 5345 5346 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000003f8) 5347 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000003f8) 5348 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 5349 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 5350 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 5351 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 5352 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 5353 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 5354 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 5355 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 5356 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 5357 do {\ 5358 HWIO_INTLOCK(); \ 5359 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 5360 HWIO_INTFREE();\ 5361 } while (0) 5362 5363 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 5364 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 5365 5366 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 5367 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 5368 5369 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 5370 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 5371 5372 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 5373 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 5374 5375 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 5376 5377 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000003fc) 5378 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000003fc) 5379 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 5380 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 5381 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 5382 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 5383 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 5384 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 5385 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 5386 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 5387 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 5388 do {\ 5389 HWIO_INTLOCK(); \ 5390 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 5391 HWIO_INTFREE();\ 5392 } while (0) 5393 5394 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 5395 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 5396 5397 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 5398 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 5399 5400 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 5401 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 5402 5403 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 5404 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 5405 5406 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 5407 5408 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000400) 5409 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000400) 5410 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff 5411 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 5412 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 5413 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 5414 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 5415 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 5416 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 5417 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 5418 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 5419 do {\ 5420 HWIO_INTLOCK(); \ 5421 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 5422 HWIO_INTFREE();\ 5423 } while (0) 5424 5425 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 5426 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 5427 5428 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 5429 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 5430 5431 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 5432 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 5433 5434 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 5435 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 5436 5437 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 5438 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 5439 5440 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 5441 5442 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000404) 5443 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000404) 5444 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 5445 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 5446 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 5447 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 5448 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 5449 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 5450 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 5451 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 5452 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 5453 do {\ 5454 HWIO_INTLOCK(); \ 5455 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 5456 HWIO_INTFREE();\ 5457 } while (0) 5458 5459 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 5460 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 5461 5462 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 5463 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 5464 5465 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 5466 5467 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000408) 5468 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000408) 5469 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 5470 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 5471 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 5472 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 5473 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 5474 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 5475 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 5476 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 5477 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 5478 do {\ 5479 HWIO_INTLOCK(); \ 5480 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 5481 HWIO_INTFREE();\ 5482 } while (0) 5483 5484 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 5485 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 5486 5487 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 5488 5489 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x0000040c) 5490 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x0000040c) 5491 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 5492 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 5493 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 5494 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 5495 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 5496 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 5497 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 5498 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 5499 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 5500 do {\ 5501 HWIO_INTLOCK(); \ 5502 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 5503 HWIO_INTFREE();\ 5504 } while (0) 5505 5506 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 5507 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 5508 5509 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 5510 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 5511 5512 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 5513 5514 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000410) 5515 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000410) 5516 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5517 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 5518 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 5519 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 5520 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5521 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5522 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5523 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 5524 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5525 do {\ 5526 HWIO_INTLOCK(); \ 5527 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 5528 HWIO_INTFREE();\ 5529 } while (0) 5530 5531 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5532 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5533 5534 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 5535 5536 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000414) 5537 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000414) 5538 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5539 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 5540 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 5541 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 5542 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5543 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5544 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5545 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5546 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5547 do {\ 5548 HWIO_INTLOCK(); \ 5549 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 5550 HWIO_INTFREE();\ 5551 } while (0) 5552 5553 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5554 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5555 5556 //// Register TCL_R0_ASE_GST_SIZE //// 5557 5558 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000418) 5559 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000418) 5560 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 5561 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 5562 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 5563 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 5564 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 5565 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 5566 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 5567 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 5568 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 5569 do {\ 5570 HWIO_INTLOCK(); \ 5571 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5572 HWIO_INTFREE();\ 5573 } while (0) 5574 5575 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5576 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5577 5578 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5579 5580 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x0000041c) 5581 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x0000041c) 5582 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff03ff 5583 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5584 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5585 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5586 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5587 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5588 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5589 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5590 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5591 do {\ 5592 HWIO_INTLOCK(); \ 5593 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5594 HWIO_INTFREE();\ 5595 } while (0) 5596 5597 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5598 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5599 5600 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5601 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5602 5603 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5604 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5605 5606 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5607 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5608 5609 //// Register TCL_R0_ASE_WATCHDOG //// 5610 5611 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000420) 5612 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000420) 5613 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5614 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5615 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5616 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5617 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5618 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5619 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5620 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5621 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5622 do {\ 5623 HWIO_INTLOCK(); \ 5624 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5625 HWIO_INTFREE();\ 5626 } while (0) 5627 5628 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5629 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5630 5631 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5632 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5633 5634 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5635 5636 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000424) 5637 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000424) 5638 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5639 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5640 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5641 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5642 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5643 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5644 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5645 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5646 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5647 do {\ 5648 HWIO_INTLOCK(); \ 5649 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5650 HWIO_INTFREE();\ 5651 } while (0) 5652 5653 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5654 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5655 5656 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5657 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5658 5659 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSVD_BMSK 0x3ffffc00 5660 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSVD_SHFT 0xa 5661 5662 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000200 5663 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x9 5664 5665 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000100 5666 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x8 5667 5668 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5669 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5670 5671 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5672 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5673 5674 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5675 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5676 5677 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5678 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5679 5680 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5681 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5682 5683 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5684 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5685 5686 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5687 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5688 5689 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5690 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5691 5692 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5693 5694 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000428) 5695 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000428) 5696 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5697 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5698 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5699 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5700 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5701 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5702 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5703 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5704 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5705 do {\ 5706 HWIO_INTLOCK(); \ 5707 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5708 HWIO_INTFREE();\ 5709 } while (0) 5710 5711 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5712 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5713 5714 //// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// 5715 5716 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x0000042c) 5717 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x0000042c) 5718 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5719 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 5720 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ 5721 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) 5722 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5723 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5724 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5725 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) 5726 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5727 do {\ 5728 HWIO_INTLOCK(); \ 5729 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ 5730 HWIO_INTFREE();\ 5731 } while (0) 5732 5733 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5734 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5735 5736 //// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// 5737 5738 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000430) 5739 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000430) 5740 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5741 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 5742 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ 5743 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) 5744 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5745 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5746 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5747 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5748 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5749 do {\ 5750 HWIO_INTLOCK(); \ 5751 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ 5752 HWIO_INTFREE();\ 5753 } while (0) 5754 5755 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5756 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5757 5758 //// Register TCL_R0_FSE_GST_SIZE //// 5759 5760 #define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x00000434) 5761 #define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x00000434) 5762 #define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff 5763 #define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 5764 #define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ 5765 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) 5766 #define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ 5767 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 5768 #define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ 5769 out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) 5770 #define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ 5771 do {\ 5772 HWIO_INTLOCK(); \ 5773 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ 5774 HWIO_INTFREE();\ 5775 } while (0) 5776 5777 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff 5778 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 5779 5780 //// Register TCL_R0_FSE_SEARCH_CTRL //// 5781 5782 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x00000438) 5783 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x00000438) 5784 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff03ff 5785 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 5786 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ 5787 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) 5788 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ 5789 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 5790 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ 5791 out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) 5792 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ 5793 do {\ 5794 HWIO_INTLOCK(); \ 5795 out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ 5796 HWIO_INTFREE();\ 5797 } while (0) 5798 5799 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5800 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5801 5802 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5803 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5804 5805 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5806 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5807 5808 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5809 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5810 5811 //// Register TCL_R0_FSE_WATCHDOG //// 5812 5813 #define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x0000043c) 5814 #define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x0000043c) 5815 #define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff 5816 #define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 5817 #define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ 5818 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) 5819 #define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ 5820 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 5821 #define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ 5822 out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) 5823 #define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ 5824 do {\ 5825 HWIO_INTLOCK(); \ 5826 out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ 5827 HWIO_INTFREE();\ 5828 } while (0) 5829 5830 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 5831 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 5832 5833 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5834 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 5835 5836 //// Register TCL_R0_FSE_CLKGATE_DISABLE //// 5837 5838 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000440) 5839 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000440) 5840 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff 5841 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 5842 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ 5843 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) 5844 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ 5845 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 5846 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ 5847 out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) 5848 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5849 do {\ 5850 HWIO_INTLOCK(); \ 5851 out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ 5852 HWIO_INTFREE();\ 5853 } while (0) 5854 5855 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5856 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5857 5858 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5859 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5860 5861 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSVD_BMSK 0x3ffffc00 5862 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSVD_SHFT 0xa 5863 5864 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000200 5865 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x9 5866 5867 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_BMSK 0x00000100 5868 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_SHFT 0x8 5869 5870 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5871 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5872 5873 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5874 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5875 5876 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5877 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5878 5879 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5880 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5881 5882 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5883 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5884 5885 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5886 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5887 5888 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5889 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5890 5891 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5892 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5893 5894 //// Register TCL_R0_FSE_WRITE_BACK_PENDING //// 5895 5896 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000444) 5897 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000444) 5898 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 5899 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 5900 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ 5901 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) 5902 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ 5903 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 5904 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ 5905 out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) 5906 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5907 do {\ 5908 HWIO_INTLOCK(); \ 5909 out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ 5910 HWIO_INTFREE();\ 5911 } while (0) 5912 5913 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5914 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5915 5916 //// Register TCL_R1_SM_STATES_IX_0 //// 5917 5918 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) 5919 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) 5920 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5921 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5922 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5923 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5924 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5925 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5926 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5927 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5928 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5929 do {\ 5930 HWIO_INTLOCK(); \ 5931 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5932 HWIO_INTFREE();\ 5933 } while (0) 5934 5935 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5936 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5937 5938 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5939 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5940 5941 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5942 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5943 5944 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5945 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5946 5947 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 5948 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc 5949 5950 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5951 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5952 5953 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5954 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5955 5956 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5957 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5958 5959 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5960 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5961 5962 //// Register TCL_R1_SM_STATES_IX_1 //// 5963 5964 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) 5965 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) 5966 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x00007fff 5967 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5968 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5969 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5970 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5971 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5972 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5973 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5974 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5975 do {\ 5976 HWIO_INTLOCK(); \ 5977 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5978 HWIO_INTFREE();\ 5979 } while (0) 5980 5981 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5982 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5983 5984 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5985 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5986 5987 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5988 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5989 5990 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5991 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5992 5993 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5994 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5995 5996 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5997 5998 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) 5999 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) 6000 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x1fffffff 6001 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 6002 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 6003 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 6004 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 6005 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 6006 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 6007 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 6008 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 6009 do {\ 6010 HWIO_INTLOCK(); \ 6011 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 6012 HWIO_INTFREE();\ 6013 } while (0) 6014 6015 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 6016 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 6017 6018 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 6019 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 6020 6021 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 6022 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 6023 6024 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 6025 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 6026 6027 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 6028 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 6029 6030 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 6031 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 6032 6033 //// Register TCL_R1_TESTBUS_LOW //// 6034 6035 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) 6036 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) 6037 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 6038 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 6039 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 6040 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 6041 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 6042 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 6043 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 6044 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 6045 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 6046 do {\ 6047 HWIO_INTLOCK(); \ 6048 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 6049 HWIO_INTFREE();\ 6050 } while (0) 6051 6052 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 6053 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 6054 6055 //// Register TCL_R1_TESTBUS_HIGH //// 6056 6057 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) 6058 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) 6059 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 6060 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 6061 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 6062 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 6063 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 6064 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 6065 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 6066 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 6067 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 6068 do {\ 6069 HWIO_INTLOCK(); \ 6070 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 6071 HWIO_INTFREE();\ 6072 } while (0) 6073 6074 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 6075 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 6076 6077 //// Register TCL_R1_EVENTMASK_IX_0 //// 6078 6079 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) 6080 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) 6081 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 6082 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 6083 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 6084 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 6085 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 6086 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 6087 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 6088 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 6089 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 6090 do {\ 6091 HWIO_INTLOCK(); \ 6092 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 6093 HWIO_INTFREE();\ 6094 } while (0) 6095 6096 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 6097 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 6098 6099 //// Register TCL_R1_EVENTMASK_IX_1 //// 6100 6101 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) 6102 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) 6103 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 6104 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 6105 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 6106 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 6107 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 6108 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 6109 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 6110 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 6111 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 6112 do {\ 6113 HWIO_INTLOCK(); \ 6114 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 6115 HWIO_INTFREE();\ 6116 } while (0) 6117 6118 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 6119 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 6120 6121 //// Register TCL_R1_EVENTMASK_IX_2 //// 6122 6123 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) 6124 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) 6125 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 6126 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 6127 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 6128 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 6129 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 6130 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 6131 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 6132 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 6133 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 6134 do {\ 6135 HWIO_INTLOCK(); \ 6136 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 6137 HWIO_INTFREE();\ 6138 } while (0) 6139 6140 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 6141 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 6142 6143 //// Register TCL_R1_EVENTMASK_IX_3 //// 6144 6145 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) 6146 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) 6147 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 6148 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 6149 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 6150 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 6151 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 6152 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 6153 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 6154 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 6155 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 6156 do {\ 6157 HWIO_INTLOCK(); \ 6158 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 6159 HWIO_INTFREE();\ 6160 } while (0) 6161 6162 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 6163 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 6164 6165 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 6166 6167 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) 6168 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) 6169 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 6170 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 6171 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 6172 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 6173 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 6174 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 6175 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 6176 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 6177 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 6178 do {\ 6179 HWIO_INTLOCK(); \ 6180 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 6181 HWIO_INTFREE();\ 6182 } while (0) 6183 6184 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 6185 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 6186 6187 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 6188 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 6189 6190 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 6191 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 6192 6193 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 6194 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 6195 6196 //// Register TCL_R1_END_OF_TEST_CHECK //// 6197 6198 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) 6199 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) 6200 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 6201 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 6202 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 6203 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 6204 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 6205 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 6206 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 6207 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 6208 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6209 do {\ 6210 HWIO_INTLOCK(); \ 6211 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 6212 HWIO_INTFREE();\ 6213 } while (0) 6214 6215 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6216 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6217 6218 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 6219 6220 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 6221 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 6222 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 6223 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 6224 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 6225 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 6226 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 6227 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 6228 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 6229 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 6230 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6231 do {\ 6232 HWIO_INTLOCK(); \ 6233 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 6234 HWIO_INTFREE();\ 6235 } while (0) 6236 6237 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6238 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6239 6240 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 6241 6242 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) 6243 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) 6244 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 6245 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 6246 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 6247 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 6248 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 6249 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 6250 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 6251 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 6252 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 6253 do {\ 6254 HWIO_INTLOCK(); \ 6255 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 6256 HWIO_INTFREE();\ 6257 } while (0) 6258 6259 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 6260 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 6261 6262 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 6263 6264 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) 6265 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) 6266 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 6267 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 6268 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 6269 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 6270 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 6271 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 6272 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 6273 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 6274 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 6275 do {\ 6276 HWIO_INTLOCK(); \ 6277 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 6278 HWIO_INTFREE();\ 6279 } while (0) 6280 6281 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 6282 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 6283 6284 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 6285 6286 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) 6287 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) 6288 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 6289 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 6290 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 6291 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6292 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6293 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6294 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6295 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6296 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6297 do {\ 6298 HWIO_INTLOCK(); \ 6299 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6300 HWIO_INTFREE();\ 6301 } while (0) 6302 6303 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6304 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6305 6306 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6307 6308 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) 6309 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) 6310 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6311 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6312 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6313 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6314 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6315 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6316 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6317 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6318 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6319 do {\ 6320 HWIO_INTLOCK(); \ 6321 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6322 HWIO_INTFREE();\ 6323 } while (0) 6324 6325 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6326 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6327 6328 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6329 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6330 6331 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 6332 6333 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) 6334 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) 6335 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6336 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6337 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6338 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6339 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6340 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6341 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6342 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6343 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6344 do {\ 6345 HWIO_INTLOCK(); \ 6346 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6347 HWIO_INTFREE();\ 6348 } while (0) 6349 6350 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6351 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6352 6353 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6354 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6355 6356 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6357 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6358 6359 //// Register TCL_R1_ASE_SM_STATES //// 6360 6361 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) 6362 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) 6363 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff 6364 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 6365 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 6366 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 6367 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 6368 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 6369 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 6370 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 6371 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 6372 do {\ 6373 HWIO_INTLOCK(); \ 6374 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 6375 HWIO_INTFREE();\ 6376 } while (0) 6377 6378 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6379 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6380 6381 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6382 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6383 6384 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6385 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6386 6387 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6388 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6389 6390 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6391 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6392 6393 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6394 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6395 6396 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6397 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6398 6399 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6400 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6401 6402 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6403 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6404 6405 //// Register TCL_R1_ASE_CACHE_DEBUG //// 6406 6407 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) 6408 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) 6409 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 6410 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 6411 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 6412 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 6413 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 6414 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 6415 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 6416 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 6417 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 6418 do {\ 6419 HWIO_INTLOCK(); \ 6420 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 6421 HWIO_INTFREE();\ 6422 } while (0) 6423 6424 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6425 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6426 6427 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 6428 6429 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) 6430 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) 6431 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6432 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6433 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6434 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6435 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6436 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6437 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6438 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6439 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6440 do {\ 6441 HWIO_INTLOCK(); \ 6442 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6443 HWIO_INTFREE();\ 6444 } while (0) 6445 6446 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6447 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6448 6449 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6450 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6451 6452 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6453 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6454 6455 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6456 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6457 6458 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 6459 6460 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) 6461 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) 6462 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6463 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 6464 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 6465 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6466 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 6467 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6468 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6469 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6470 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6471 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6472 do {\ 6473 HWIO_INTLOCK(); \ 6474 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6475 HWIO_INTFREE();\ 6476 } while (0) 6477 6478 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6479 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6480 6481 //// Register TCL_R1_FSE_END_OF_TEST_CHECK //// 6482 6483 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) 6484 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) 6485 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 6486 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 6487 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ 6488 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) 6489 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ 6490 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 6491 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ 6492 out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) 6493 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6494 do {\ 6495 HWIO_INTLOCK(); \ 6496 out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ 6497 HWIO_INTFREE();\ 6498 } while (0) 6499 6500 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6501 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6502 6503 //// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// 6504 6505 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) 6506 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) 6507 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 6508 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 6509 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ 6510 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) 6511 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 6512 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 6513 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 6514 out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 6515 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 6516 do {\ 6517 HWIO_INTLOCK(); \ 6518 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 6519 HWIO_INTFREE();\ 6520 } while (0) 6521 6522 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 6523 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 6524 6525 //// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// 6526 6527 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) 6528 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) 6529 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 6530 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 6531 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 6532 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 6533 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 6534 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 6535 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 6536 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 6537 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 6538 do {\ 6539 HWIO_INTLOCK(); \ 6540 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 6541 HWIO_INTFREE();\ 6542 } while (0) 6543 6544 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 6545 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 6546 6547 //// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// 6548 6549 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) 6550 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) 6551 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 6552 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 6553 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 6554 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6555 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6556 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6557 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6558 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6559 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6560 do {\ 6561 HWIO_INTLOCK(); \ 6562 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6563 HWIO_INTFREE();\ 6564 } while (0) 6565 6566 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6567 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6568 6569 //// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6570 6571 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) 6572 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) 6573 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6574 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6575 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6576 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6577 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6578 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6579 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6580 out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6581 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6582 do {\ 6583 HWIO_INTLOCK(); \ 6584 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6585 HWIO_INTFREE();\ 6586 } while (0) 6587 6588 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6589 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6590 6591 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6592 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6593 6594 //// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// 6595 6596 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) 6597 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) 6598 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6599 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6600 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6601 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6602 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6603 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6604 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6605 out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6606 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6607 do {\ 6608 HWIO_INTLOCK(); \ 6609 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6610 HWIO_INTFREE();\ 6611 } while (0) 6612 6613 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6614 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6615 6616 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6617 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6618 6619 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6620 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6621 6622 //// Register TCL_R1_FSE_SM_STATES //// 6623 6624 #define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) 6625 #define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) 6626 #define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff 6627 #define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 6628 #define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ 6629 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) 6630 #define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ 6631 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 6632 #define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ 6633 out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) 6634 #define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ 6635 do {\ 6636 HWIO_INTLOCK(); \ 6637 out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ 6638 HWIO_INTFREE();\ 6639 } while (0) 6640 6641 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6642 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6643 6644 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6645 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6646 6647 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6648 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6649 6650 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6651 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6652 6653 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6654 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6655 6656 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6657 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6658 6659 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6660 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6661 6662 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6663 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6664 6665 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6666 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6667 6668 //// Register TCL_R1_FSE_CACHE_DEBUG //// 6669 6670 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) 6671 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) 6672 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff 6673 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 6674 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ 6675 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) 6676 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ 6677 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 6678 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ 6679 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) 6680 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ 6681 do {\ 6682 HWIO_INTLOCK(); \ 6683 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ 6684 HWIO_INTFREE();\ 6685 } while (0) 6686 6687 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6688 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6689 6690 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// 6691 6692 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) 6693 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) 6694 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6695 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6696 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6697 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6698 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6699 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6700 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6701 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6702 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6703 do {\ 6704 HWIO_INTLOCK(); \ 6705 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6706 HWIO_INTFREE();\ 6707 } while (0) 6708 6709 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6710 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6711 6712 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6713 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6714 6715 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6716 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6717 6718 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6719 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6720 6721 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// 6722 6723 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) 6724 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) 6725 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6726 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 6727 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 6728 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6729 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) 6730 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6731 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6732 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6733 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6734 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6735 do {\ 6736 HWIO_INTLOCK(); \ 6737 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6738 HWIO_INTFREE();\ 6739 } while (0) 6740 6741 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6742 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6743 6744 //// Register TCL_R2_SW2TCL1_RING_HP //// 6745 6746 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 6747 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 6748 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x0000ffff 6749 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 6750 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 6751 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 6752 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 6753 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 6754 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 6755 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 6756 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 6757 do {\ 6758 HWIO_INTLOCK(); \ 6759 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 6760 HWIO_INTFREE();\ 6761 } while (0) 6762 6763 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6764 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6765 6766 //// Register TCL_R2_SW2TCL1_RING_TP //// 6767 6768 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 6769 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 6770 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x0000ffff 6771 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 6772 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 6773 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 6774 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 6775 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 6776 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 6777 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 6778 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 6779 do {\ 6780 HWIO_INTLOCK(); \ 6781 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 6782 HWIO_INTFREE();\ 6783 } while (0) 6784 6785 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6786 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6787 6788 //// Register TCL_R2_SW2TCL2_RING_HP //// 6789 6790 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 6791 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 6792 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x0000ffff 6793 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 6794 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 6795 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 6796 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 6797 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 6798 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 6799 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 6800 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 6801 do {\ 6802 HWIO_INTLOCK(); \ 6803 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 6804 HWIO_INTFREE();\ 6805 } while (0) 6806 6807 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6808 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 6809 6810 //// Register TCL_R2_SW2TCL2_RING_TP //// 6811 6812 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 6813 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 6814 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x0000ffff 6815 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 6816 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 6817 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 6818 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 6819 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 6820 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 6821 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 6822 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 6823 do {\ 6824 HWIO_INTLOCK(); \ 6825 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 6826 HWIO_INTFREE();\ 6827 } while (0) 6828 6829 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6830 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 6831 6832 //// Register TCL_R2_SW2TCL3_RING_HP //// 6833 6834 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 6835 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 6836 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x0000ffff 6837 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 6838 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 6839 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 6840 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 6841 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 6842 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 6843 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 6844 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 6845 do {\ 6846 HWIO_INTLOCK(); \ 6847 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 6848 HWIO_INTFREE();\ 6849 } while (0) 6850 6851 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6852 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 6853 6854 //// Register TCL_R2_SW2TCL3_RING_TP //// 6855 6856 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 6857 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 6858 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x0000ffff 6859 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 6860 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 6861 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 6862 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 6863 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 6864 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 6865 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 6866 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 6867 do {\ 6868 HWIO_INTLOCK(); \ 6869 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 6870 HWIO_INTFREE();\ 6871 } while (0) 6872 6873 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6874 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 6875 6876 //// Register TCL_R2_SW2TCL_CMD_RING_HP //// 6877 6878 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) 6879 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) 6880 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x0000ffff 6881 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 6882 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ 6883 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) 6884 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ 6885 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 6886 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ 6887 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) 6888 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ 6889 do {\ 6890 HWIO_INTLOCK(); \ 6891 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ 6892 HWIO_INTFREE();\ 6893 } while (0) 6894 6895 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6896 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 6897 6898 //// Register TCL_R2_SW2TCL_CMD_RING_TP //// 6899 6900 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) 6901 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) 6902 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x0000ffff 6903 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 6904 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ 6905 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) 6906 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ 6907 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 6908 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ 6909 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) 6910 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ 6911 do {\ 6912 HWIO_INTLOCK(); \ 6913 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ 6914 HWIO_INTFREE();\ 6915 } while (0) 6916 6917 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6918 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 6919 6920 //// Register TCL_R2_FW2TCL1_RING_HP //// 6921 6922 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 6923 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 6924 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 6925 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 6926 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 6927 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 6928 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 6929 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 6930 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 6931 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 6932 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 6933 do {\ 6934 HWIO_INTLOCK(); \ 6935 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 6936 HWIO_INTFREE();\ 6937 } while (0) 6938 6939 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6940 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6941 6942 //// Register TCL_R2_FW2TCL1_RING_TP //// 6943 6944 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 6945 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 6946 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 6947 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 6948 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 6949 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 6950 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 6951 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 6952 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 6953 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 6954 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 6955 do {\ 6956 HWIO_INTLOCK(); \ 6957 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 6958 HWIO_INTFREE();\ 6959 } while (0) 6960 6961 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6962 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6963 6964 //// Register TCL_R2_TCL2TQM_RING_HP //// 6965 6966 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 6967 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 6968 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 6969 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 6970 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 6971 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 6972 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 6973 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 6974 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6975 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6976 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6977 do {\ 6978 HWIO_INTLOCK(); \ 6979 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6980 HWIO_INTFREE();\ 6981 } while (0) 6982 6983 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6984 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6985 6986 //// Register TCL_R2_TCL2TQM_RING_TP //// 6987 6988 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6989 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6990 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6991 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6992 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6993 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6994 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6995 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6996 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6997 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6998 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6999 do {\ 7000 HWIO_INTLOCK(); \ 7001 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 7002 HWIO_INTFREE();\ 7003 } while (0) 7004 7005 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 7006 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 7007 7008 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 7009 7010 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 7011 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 7012 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 7013 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 7014 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 7015 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 7016 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 7017 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 7018 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 7019 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 7020 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 7021 do {\ 7022 HWIO_INTLOCK(); \ 7023 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 7024 HWIO_INTFREE();\ 7025 } while (0) 7026 7027 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 7028 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 7029 7030 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 7031 7032 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 7033 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 7034 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 7035 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 7036 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 7037 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 7038 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 7039 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 7040 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 7041 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 7042 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 7043 do {\ 7044 HWIO_INTLOCK(); \ 7045 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 7046 HWIO_INTFREE();\ 7047 } while (0) 7048 7049 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 7050 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 7051 7052 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 7053 7054 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 7055 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 7056 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 7057 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 7058 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 7059 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 7060 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 7061 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 7062 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 7063 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 7064 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 7065 do {\ 7066 HWIO_INTLOCK(); \ 7067 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 7068 HWIO_INTFREE();\ 7069 } while (0) 7070 7071 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 7072 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 7073 7074 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 7075 7076 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 7077 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 7078 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 7079 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 7080 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 7081 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 7082 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 7083 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 7084 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 7085 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 7086 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 7087 do {\ 7088 HWIO_INTLOCK(); \ 7089 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 7090 HWIO_INTFREE();\ 7091 } while (0) 7092 7093 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 7094 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 7095 7096 //// Register TCL_R2_TCL2FW_RING_HP //// 7097 7098 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 7099 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 7100 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 7101 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 7102 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 7103 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 7104 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 7105 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 7106 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 7107 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 7108 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 7109 do {\ 7110 HWIO_INTLOCK(); \ 7111 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 7112 HWIO_INTFREE();\ 7113 } while (0) 7114 7115 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 7116 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 7117 7118 //// Register TCL_R2_TCL2FW_RING_TP //// 7119 7120 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 7121 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 7122 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 7123 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 7124 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 7125 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 7126 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 7127 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 7128 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 7129 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 7130 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 7131 do {\ 7132 HWIO_INTLOCK(); \ 7133 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 7134 HWIO_INTFREE();\ 7135 } while (0) 7136 7137 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 7138 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 7139 7140 7141 #endif 7142 7143