1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 10/27/2016 22 // User Name:kanalas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WFSS_CE_REG_SEQ_REG_H__ 29 #define __WFSS_CE_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "wfss_ce_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block WFSS_CE_CHANNEL_DST_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB //// 45 46 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) (x+0x00000000) 47 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) (x+0x00000000) 48 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 49 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT 0 50 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ 51 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 52 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ 53 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) 54 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ 55 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) 56 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 64 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 65 66 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB //// 67 68 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) (x+0x00000004) 69 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) (x+0x00000004) 70 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0x00ffffff 71 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT 0 72 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ 73 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 74 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ 75 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) 76 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ 77 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) 78 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ 79 do {\ 80 HWIO_INTLOCK(); \ 81 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ 82 HWIO_INTFREE();\ 83 } while (0) 84 85 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 86 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 87 88 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 89 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 90 91 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID //// 92 93 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) 94 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) 95 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x000000ff 96 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 97 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ 98 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 99 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ 100 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) 101 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ 102 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) 103 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ 104 do {\ 105 HWIO_INTLOCK(); \ 106 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ 107 HWIO_INTFREE();\ 108 } while (0) 109 110 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 111 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 112 113 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS //// 114 115 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) (x+0x0000000c) 116 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) (x+0x0000000c) 117 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 118 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT 0 119 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ 120 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 121 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ 122 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) 123 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ 124 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) 125 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ 126 do {\ 127 HWIO_INTLOCK(); \ 128 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ 129 HWIO_INTFREE();\ 130 } while (0) 131 132 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 133 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 134 135 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 136 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 137 138 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC //// 139 140 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) (x+0x00000010) 141 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) (x+0x00000010) 142 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x0000003f 143 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT 0 144 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ 145 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 146 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ 147 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) 148 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ 149 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) 150 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ 151 do {\ 152 HWIO_INTLOCK(); \ 153 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ 154 HWIO_INTFREE();\ 155 } while (0) 156 157 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 158 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 159 160 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 161 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 162 163 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 164 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 165 166 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004 167 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 168 169 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 170 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 171 172 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 173 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 174 175 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB //// 176 177 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 178 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 179 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 180 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT 0 181 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ 182 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 183 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ 184 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) 185 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ 186 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) 187 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 188 do {\ 189 HWIO_INTLOCK(); \ 190 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ 191 HWIO_INTFREE();\ 192 } while (0) 193 194 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 195 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 196 197 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB //// 198 199 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 200 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 201 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0x000000ff 202 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT 0 203 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ 204 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 205 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ 206 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) 207 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ 208 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) 209 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 210 do {\ 211 HWIO_INTLOCK(); \ 212 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ 213 HWIO_INTFREE();\ 214 } while (0) 215 216 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 217 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 218 219 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 //// 220 221 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 222 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 223 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 224 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 225 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 226 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 227 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 228 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 229 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 230 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 231 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 232 do {\ 233 HWIO_INTLOCK(); \ 234 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 235 HWIO_INTFREE();\ 236 } while (0) 237 238 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 239 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 240 241 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 242 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 243 244 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 245 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 246 247 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 //// 248 249 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 250 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 251 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 252 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 253 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 254 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 255 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 256 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 257 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 258 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 259 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 260 do {\ 261 HWIO_INTLOCK(); \ 262 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 263 HWIO_INTFREE();\ 264 } while (0) 265 266 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 267 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 268 269 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS //// 270 271 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 272 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 273 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 274 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT 0 275 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ 276 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 277 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 278 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 279 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 280 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) 281 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 282 do {\ 283 HWIO_INTLOCK(); \ 284 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ 285 HWIO_INTFREE();\ 286 } while (0) 287 288 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 289 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 290 291 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 292 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 293 294 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 295 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 296 297 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER //// 298 299 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 300 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 301 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 302 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 303 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 304 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 305 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 306 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 307 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 308 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 309 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 310 do {\ 311 HWIO_INTLOCK(); \ 312 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 313 HWIO_INTFREE();\ 314 } while (0) 315 316 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 317 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 318 319 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// 320 321 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 322 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 323 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 324 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 325 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 326 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 327 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 328 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 329 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 330 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 331 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 332 do {\ 333 HWIO_INTLOCK(); \ 334 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 335 HWIO_INTFREE();\ 336 } while (0) 337 338 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 339 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 340 341 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS //// 342 343 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 344 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 345 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 346 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 347 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 348 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 349 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 350 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 351 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 352 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 353 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 354 do {\ 355 HWIO_INTLOCK(); \ 356 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 357 HWIO_INTFREE();\ 358 } while (0) 359 360 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 361 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 362 363 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 364 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 365 366 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB //// 367 368 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 369 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 370 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 371 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT 0 372 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ 373 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 374 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ 375 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) 376 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ 377 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) 378 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 379 do {\ 380 HWIO_INTLOCK(); \ 381 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ 382 HWIO_INTFREE();\ 383 } while (0) 384 385 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 386 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 387 388 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB //// 389 390 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 391 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 392 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x000001ff 393 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT 0 394 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ 395 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 396 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ 397 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) 398 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ 399 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) 400 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 401 do {\ 402 HWIO_INTLOCK(); \ 403 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ 404 HWIO_INTFREE();\ 405 } while (0) 406 407 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 408 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 409 410 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 411 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 412 413 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA //// 414 415 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 416 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 417 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 418 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT 0 419 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ 420 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 421 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ 422 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) 423 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ 424 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) 425 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ 426 do {\ 427 HWIO_INTLOCK(); \ 428 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ 429 HWIO_INTFREE();\ 430 } while (0) 431 432 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 433 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 434 435 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET //// 436 437 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 438 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 439 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 440 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 441 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ 442 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 443 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 444 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 445 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 446 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) 447 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 448 do {\ 449 HWIO_INTLOCK(); \ 450 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ 451 HWIO_INTFREE();\ 452 } while (0) 453 454 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 455 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 456 457 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// 458 459 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000058) 460 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000058) 461 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 462 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT 0 463 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ 464 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 465 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ 466 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) 467 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ 468 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) 469 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 470 do {\ 471 HWIO_INTLOCK(); \ 472 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ 473 HWIO_INTFREE();\ 474 } while (0) 475 476 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 477 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 478 479 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB //// 480 481 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) (x+0x0000005c) 482 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) (x+0x0000005c) 483 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 484 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT 0 485 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ 486 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 487 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ 488 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) 489 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ 490 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) 491 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 492 do {\ 493 HWIO_INTLOCK(); \ 494 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ 495 HWIO_INTFREE();\ 496 } while (0) 497 498 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 499 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 500 501 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 502 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 503 504 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID //// 505 506 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) (x+0x00000060) 507 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) (x+0x00000060) 508 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0x0000ffff 509 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT 0 510 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ 511 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 512 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ 513 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) 514 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ 515 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) 516 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ 517 do {\ 518 HWIO_INTLOCK(); \ 519 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ 520 HWIO_INTFREE();\ 521 } while (0) 522 523 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 524 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 525 526 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 527 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 528 529 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS //// 530 531 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) (x+0x00000064) 532 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) (x+0x00000064) 533 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 534 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT 0 535 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ 536 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 537 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ 538 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) 539 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ 540 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) 541 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ 542 do {\ 543 HWIO_INTLOCK(); \ 544 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ 545 HWIO_INTFREE();\ 546 } while (0) 547 548 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 549 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 550 551 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 552 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 553 554 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC //// 555 556 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) (x+0x00000068) 557 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) (x+0x00000068) 558 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x0000003f 559 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT 0 560 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ 561 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 562 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ 563 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) 564 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ 565 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) 566 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ 567 do {\ 568 HWIO_INTLOCK(); \ 569 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ 570 HWIO_INTFREE();\ 571 } while (0) 572 573 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 574 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 575 576 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 577 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 578 579 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 580 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 581 582 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 583 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 584 585 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 586 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 587 588 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 589 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 590 591 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB //// 592 593 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000006c) 594 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000006c) 595 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 596 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT 0 597 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ 598 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 599 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 600 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 601 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 602 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 603 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 604 do {\ 605 HWIO_INTLOCK(); \ 606 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 607 HWIO_INTFREE();\ 608 } while (0) 609 610 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 611 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 612 613 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB //// 614 615 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000070) 616 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000070) 617 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 618 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT 0 619 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ 620 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 621 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 622 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 623 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 624 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 625 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 626 do {\ 627 HWIO_INTLOCK(); \ 628 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 629 HWIO_INTFREE();\ 630 } while (0) 631 632 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 633 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 634 635 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP //// 636 637 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c) 638 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c) 639 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 640 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 641 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 642 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 643 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 644 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 645 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 646 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 647 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 648 do {\ 649 HWIO_INTLOCK(); \ 650 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 651 HWIO_INTFREE();\ 652 } while (0) 653 654 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 655 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 656 657 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 658 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 659 660 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 661 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 662 663 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS //// 664 665 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080) 666 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080) 667 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 668 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 669 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 670 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 671 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 672 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 673 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 674 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 675 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 676 do {\ 677 HWIO_INTLOCK(); \ 678 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 679 HWIO_INTFREE();\ 680 } while (0) 681 682 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 683 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 684 685 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 686 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 687 688 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 689 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 690 691 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER //// 692 693 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) 694 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) 695 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 696 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 697 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 698 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 699 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 700 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 701 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 702 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 703 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 704 do {\ 705 HWIO_INTLOCK(); \ 706 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 707 HWIO_INTFREE();\ 708 } while (0) 709 710 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 711 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 712 713 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// 714 715 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0) 716 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0) 717 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 718 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT 0 719 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 720 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 721 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 722 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 723 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 724 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 725 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 726 do {\ 727 HWIO_INTLOCK(); \ 728 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 729 HWIO_INTFREE();\ 730 } while (0) 731 732 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 733 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 734 735 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB //// 736 737 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4) 738 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4) 739 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 740 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT 0 741 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 742 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 743 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 744 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 745 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 746 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 747 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 748 do {\ 749 HWIO_INTLOCK(); \ 750 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 751 HWIO_INTFREE();\ 752 } while (0) 753 754 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 755 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 756 757 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 758 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 759 760 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA //// 761 762 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000000a8) 763 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000000a8) 764 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 765 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT 0 766 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ 767 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 768 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ 769 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) 770 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ 771 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) 772 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 773 do {\ 774 HWIO_INTLOCK(); \ 775 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ 776 HWIO_INTFREE();\ 777 } while (0) 778 779 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 780 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 781 782 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET //// 783 784 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) 785 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) 786 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 787 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 788 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 789 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 790 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 791 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 792 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 793 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 794 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 795 do {\ 796 HWIO_INTLOCK(); \ 797 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 798 HWIO_INTFREE();\ 799 } while (0) 800 801 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 802 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 803 804 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// 805 806 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) 807 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) (x+0x000000b0) 808 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x0001ffff 809 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT 0 810 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ 811 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 812 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ 813 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) 814 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ 815 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) 816 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ 817 do {\ 818 HWIO_INTLOCK(); \ 819 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ 820 HWIO_INTFREE();\ 821 } while (0) 822 823 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 824 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 825 826 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 827 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 828 829 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS //// 830 831 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) (x+0x000000b4) 832 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) (x+0x000000b4) 833 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x0000003f 834 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT 0 835 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ 836 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 837 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ 838 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) 839 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ 840 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) 841 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ 842 do {\ 843 HWIO_INTLOCK(); \ 844 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ 845 HWIO_INTFREE();\ 846 } while (0) 847 848 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 849 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 850 851 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010 852 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 853 854 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008 855 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 856 857 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x00000004 858 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 859 860 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x00000002 861 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 862 863 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x00000001 864 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 865 866 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 //// 867 868 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) (x+0x000000b8) 869 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) (x+0x000000b8) 870 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0x0000000f 871 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT 0 872 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ 873 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 874 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ 875 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) 876 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ 877 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) 878 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ 879 do {\ 880 HWIO_INTLOCK(); \ 881 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ 882 HWIO_INTFREE();\ 883 } while (0) 884 885 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 886 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 887 888 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004 889 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 890 891 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002 892 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 893 894 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x00000001 895 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 896 897 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP //// 898 899 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) (x+0x00000400) 900 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) (x+0x00000400) 901 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0x0000ffff 902 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT 0 903 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ 904 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 905 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ 906 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) 907 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ 908 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) 909 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ 910 do {\ 911 HWIO_INTLOCK(); \ 912 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ 913 HWIO_INTFREE();\ 914 } while (0) 915 916 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff 917 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 918 919 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP //// 920 921 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) (x+0x00000404) 922 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) (x+0x00000404) 923 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0x0000ffff 924 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT 0 925 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ 926 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 927 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ 928 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) 929 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ 930 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) 931 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ 932 do {\ 933 HWIO_INTLOCK(); \ 934 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ 935 HWIO_INTFREE();\ 936 } while (0) 937 938 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff 939 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 940 941 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP //// 942 943 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) (x+0x00000408) 944 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) (x+0x00000408) 945 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0x0000ffff 946 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT 0 947 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ 948 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 949 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ 950 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) 951 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ 952 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) 953 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ 954 do {\ 955 HWIO_INTLOCK(); \ 956 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ 957 HWIO_INTFREE();\ 958 } while (0) 959 960 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 961 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 962 963 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP //// 964 965 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) (x+0x0000040c) 966 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) (x+0x0000040c) 967 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0x0000ffff 968 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT 0 969 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ 970 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 971 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ 972 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) 973 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ 974 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) 975 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ 976 do {\ 977 HWIO_INTLOCK(); \ 978 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ 979 HWIO_INTFREE();\ 980 } while (0) 981 982 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 983 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 984 985 986 /////////////////////////////////////////////////////////////////////////////////////////////// 987 // Register Data for Block WFSS_CE_CHANNEL_SRC_REG 988 /////////////////////////////////////////////////////////////////////////////////////////////// 989 990 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB //// 991 992 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) (x+0x00000000) 993 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) (x+0x00000000) 994 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 995 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT 0 996 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ 997 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 998 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ 999 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) 1000 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ 1001 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) 1002 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ 1003 do {\ 1004 HWIO_INTLOCK(); \ 1005 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ 1006 HWIO_INTFREE();\ 1007 } while (0) 1008 1009 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1010 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1011 1012 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB //// 1013 1014 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) (x+0x00000004) 1015 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) (x+0x00000004) 1016 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0x00ffffff 1017 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT 0 1018 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ 1019 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 1020 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ 1021 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) 1022 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ 1023 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) 1024 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ 1025 do {\ 1026 HWIO_INTLOCK(); \ 1027 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ 1028 HWIO_INTFREE();\ 1029 } while (0) 1030 1031 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1032 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1033 1034 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1035 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1036 1037 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID //// 1038 1039 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) 1040 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) 1041 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x000000ff 1042 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 1043 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ 1044 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 1045 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ 1046 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) 1047 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ 1048 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) 1049 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ 1050 do {\ 1051 HWIO_INTLOCK(); \ 1052 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ 1053 HWIO_INTFREE();\ 1054 } while (0) 1055 1056 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1057 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 1058 1059 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS //// 1060 1061 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) (x+0x0000000c) 1062 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) (x+0x0000000c) 1063 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 1064 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT 0 1065 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ 1066 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 1067 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ 1068 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) 1069 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ 1070 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) 1071 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ 1072 do {\ 1073 HWIO_INTLOCK(); \ 1074 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ 1075 HWIO_INTFREE();\ 1076 } while (0) 1077 1078 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1079 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1080 1081 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1082 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1083 1084 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC //// 1085 1086 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) (x+0x00000010) 1087 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) (x+0x00000010) 1088 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x0000003f 1089 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT 0 1090 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ 1091 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 1092 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ 1093 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) 1094 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ 1095 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) 1096 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ 1097 do {\ 1098 HWIO_INTLOCK(); \ 1099 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ 1100 HWIO_INTFREE();\ 1101 } while (0) 1102 1103 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1104 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1105 1106 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1107 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1108 1109 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1110 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1111 1112 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1113 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 1114 1115 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1116 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1117 1118 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1119 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1120 1121 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB //// 1122 1123 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 1124 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 1125 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 1126 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT 0 1127 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ 1128 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 1129 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ 1130 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) 1131 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ 1132 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) 1133 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1134 do {\ 1135 HWIO_INTLOCK(); \ 1136 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ 1137 HWIO_INTFREE();\ 1138 } while (0) 1139 1140 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1141 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1142 1143 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB //// 1144 1145 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 1146 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 1147 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0x000000ff 1148 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT 0 1149 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ 1150 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 1151 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ 1152 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) 1153 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ 1154 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) 1155 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1156 do {\ 1157 HWIO_INTLOCK(); \ 1158 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ 1159 HWIO_INTFREE();\ 1160 } while (0) 1161 1162 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1163 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1164 1165 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 //// 1166 1167 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 1168 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 1169 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1170 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1171 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1172 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1173 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1174 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1175 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1176 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1177 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1178 do {\ 1179 HWIO_INTLOCK(); \ 1180 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1181 HWIO_INTFREE();\ 1182 } while (0) 1183 1184 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1185 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1186 1187 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1188 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1189 1190 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1191 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1192 1193 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 //// 1194 1195 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 1196 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 1197 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1198 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1199 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1200 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1201 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1202 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1203 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1204 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1205 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1206 do {\ 1207 HWIO_INTLOCK(); \ 1208 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1209 HWIO_INTFREE();\ 1210 } while (0) 1211 1212 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1213 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1214 1215 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS //// 1216 1217 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 1218 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 1219 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1220 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT 0 1221 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ 1222 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 1223 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1224 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1225 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1226 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1227 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1228 do {\ 1229 HWIO_INTLOCK(); \ 1230 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ 1231 HWIO_INTFREE();\ 1232 } while (0) 1233 1234 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1235 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1236 1237 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1238 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1239 1240 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1241 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1242 1243 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER //// 1244 1245 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 1246 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 1247 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1248 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1249 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1250 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1251 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1252 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1253 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1254 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1255 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1256 do {\ 1257 HWIO_INTLOCK(); \ 1258 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1259 HWIO_INTFREE();\ 1260 } while (0) 1261 1262 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1263 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1264 1265 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// 1266 1267 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 1268 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 1269 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1270 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1271 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1272 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1273 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1274 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1275 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1276 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1277 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1278 do {\ 1279 HWIO_INTLOCK(); \ 1280 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1281 HWIO_INTFREE();\ 1282 } while (0) 1283 1284 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1285 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1286 1287 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS //// 1288 1289 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 1290 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 1291 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1292 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1293 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1294 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1295 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1296 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1297 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1298 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1299 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1300 do {\ 1301 HWIO_INTLOCK(); \ 1302 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1303 HWIO_INTFREE();\ 1304 } while (0) 1305 1306 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1307 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1308 1309 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1310 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1311 1312 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB //// 1313 1314 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 1315 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 1316 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1317 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT 0 1318 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ 1319 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 1320 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ 1321 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) 1322 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ 1323 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) 1324 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1325 do {\ 1326 HWIO_INTLOCK(); \ 1327 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ 1328 HWIO_INTFREE();\ 1329 } while (0) 1330 1331 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1332 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1333 1334 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB //// 1335 1336 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 1337 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 1338 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1339 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT 0 1340 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ 1341 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 1342 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ 1343 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) 1344 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ 1345 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) 1346 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1347 do {\ 1348 HWIO_INTLOCK(); \ 1349 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ 1350 HWIO_INTFREE();\ 1351 } while (0) 1352 1353 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1354 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1355 1356 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1357 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1358 1359 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA //// 1360 1361 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 1362 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 1363 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 1364 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT 0 1365 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ 1366 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 1367 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ 1368 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) 1369 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ 1370 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) 1371 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ 1372 do {\ 1373 HWIO_INTLOCK(); \ 1374 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ 1375 HWIO_INTFREE();\ 1376 } while (0) 1377 1378 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1379 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 1380 1381 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET //// 1382 1383 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 1384 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 1385 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1386 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 1387 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ 1388 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 1389 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1390 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1391 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1392 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1393 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1394 do {\ 1395 HWIO_INTLOCK(); \ 1396 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ 1397 HWIO_INTFREE();\ 1398 } while (0) 1399 1400 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1401 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1402 1403 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// 1404 1405 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) (x+0x00000058) 1406 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) (x+0x00000058) 1407 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x0000001f 1408 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT 0 1409 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ 1410 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 1411 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ 1412 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) 1413 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ 1414 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) 1415 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ 1416 do {\ 1417 HWIO_INTLOCK(); \ 1418 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ 1419 HWIO_INTFREE();\ 1420 } while (0) 1421 1422 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 1423 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 1424 1425 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x00000008 1426 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 1427 1428 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x00000004 1429 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 1430 1431 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x00000002 1432 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 1433 1434 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001 1435 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 1436 1437 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS //// 1438 1439 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) (x+0x0000005c) 1440 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) (x+0x0000005c) 1441 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x0000001f 1442 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT 0 1443 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ 1444 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 1445 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ 1446 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) 1447 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ 1448 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) 1449 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ 1450 do {\ 1451 HWIO_INTLOCK(); \ 1452 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ 1453 HWIO_INTFREE();\ 1454 } while (0) 1455 1456 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 1457 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 1458 1459 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008 1460 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 1461 1462 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004 1463 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 1464 1465 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x00000002 1466 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 1467 1468 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x00000001 1469 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 1470 1471 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG //// 1472 1473 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) (x+0x00000060) 1474 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) (x+0x00000060) 1475 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 1476 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT 0 1477 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ 1478 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 1479 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ 1480 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) 1481 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ 1482 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) 1483 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ 1484 do {\ 1485 HWIO_INTLOCK(); \ 1486 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ 1487 HWIO_INTFREE();\ 1488 } while (0) 1489 1490 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 1491 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 1492 1493 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0x0000ffff 1494 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 1495 1496 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP //// 1497 1498 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) (x+0x00000400) 1499 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) (x+0x00000400) 1500 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0x0000ffff 1501 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT 0 1502 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ 1503 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 1504 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ 1505 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) 1506 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ 1507 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) 1508 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ 1509 do {\ 1510 HWIO_INTLOCK(); \ 1511 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ 1512 HWIO_INTFREE();\ 1513 } while (0) 1514 1515 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff 1516 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 1517 1518 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP //// 1519 1520 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) (x+0x00000404) 1521 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) (x+0x00000404) 1522 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0x0000ffff 1523 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT 0 1524 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ 1525 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 1526 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ 1527 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) 1528 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ 1529 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) 1530 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ 1531 do {\ 1532 HWIO_INTLOCK(); \ 1533 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ 1534 HWIO_INTFREE();\ 1535 } while (0) 1536 1537 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff 1538 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 1539 1540 1541 /////////////////////////////////////////////////////////////////////////////////////////////// 1542 // Register Data for Block WFSS_CE_COMMON_REG 1543 /////////////////////////////////////////////////////////////////////////////////////////////// 1544 1545 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER //// 1546 1547 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) (x+0x00000000) 1548 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) (x+0x00000000) 1549 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff 1550 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT 0 1551 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ 1552 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) 1553 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ 1554 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) 1555 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ 1556 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) 1557 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ 1558 do {\ 1559 HWIO_INTLOCK(); \ 1560 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ 1561 HWIO_INTFREE();\ 1562 } while (0) 1563 1564 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 1565 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 1566 1567 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER //// 1568 1569 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) (x+0x00000004) 1570 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) (x+0x00000004) 1571 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0x000000ff 1572 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT 0 1573 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ 1574 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) 1575 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ 1576 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) 1577 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ 1578 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) 1579 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ 1580 do {\ 1581 HWIO_INTLOCK(); \ 1582 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ 1583 HWIO_INTFREE();\ 1584 } while (0) 1585 1586 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 1587 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 1588 1589 //// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 //// 1590 1591 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) (x+0x00000008) 1592 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) (x+0x00000008) 1593 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0x00000fff 1594 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT 0 1595 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ 1596 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) 1597 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ 1598 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) 1599 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ 1600 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) 1601 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ 1602 do {\ 1603 HWIO_INTLOCK(); \ 1604 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ 1605 HWIO_INTFREE();\ 1606 } while (0) 1607 1608 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 1609 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 1610 1611 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 1612 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 1613 1614 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 1615 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 1616 1617 //// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK //// 1618 1619 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000000c) 1620 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000000c) 1621 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x00000001 1622 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT 0 1623 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ 1624 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) 1625 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ 1626 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) 1627 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ 1628 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) 1629 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 1630 do {\ 1631 HWIO_INTLOCK(); \ 1632 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ 1633 HWIO_INTFREE();\ 1634 } while (0) 1635 1636 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 1637 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 1638 1639 //// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE //// 1640 1641 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000010) 1642 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000010) 1643 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff 1644 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT 0 1645 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ 1646 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) 1647 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ 1648 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) 1649 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ 1650 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) 1651 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 1652 do {\ 1653 HWIO_INTLOCK(); \ 1654 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ 1655 HWIO_INTFREE();\ 1656 } while (0) 1657 1658 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 1659 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 1660 1661 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff 1662 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 1663 1664 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS //// 1665 1666 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) (x+0x00000014) 1667 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) (x+0x00000014) 1668 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x01010101 1669 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT 0 1670 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ 1671 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) 1672 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ 1673 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) 1674 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ 1675 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) 1676 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ 1677 do {\ 1678 HWIO_INTLOCK(); \ 1679 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ 1680 HWIO_INTFREE();\ 1681 } while (0) 1682 1683 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 1684 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 1685 1686 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 1687 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 1688 1689 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 1690 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 1691 1692 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 1693 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 1694 1695 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS //// 1696 1697 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) (x+0x00000018) 1698 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) (x+0x00000018) 1699 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x003f3f3f 1700 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT 0 1701 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ 1702 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) 1703 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ 1704 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) 1705 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ 1706 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) 1707 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ 1708 do {\ 1709 HWIO_INTLOCK(); \ 1710 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ 1711 HWIO_INTFREE();\ 1712 } while (0) 1713 1714 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 1715 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 1716 1717 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 1718 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 1719 1720 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 1721 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 1722 1723 //// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL //// 1724 1725 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x0000001c) 1726 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x0000001c) 1727 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 1728 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT 0 1729 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ 1730 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) 1731 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ 1732 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) 1733 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ 1734 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) 1735 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 1736 do {\ 1737 HWIO_INTLOCK(); \ 1738 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ 1739 HWIO_INTFREE();\ 1740 } while (0) 1741 1742 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 1743 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 1744 1745 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1746 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 1747 1748 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 1749 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 1750 1751 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 1752 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 1753 1754 //// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL //// 1755 1756 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000020) 1757 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000020) 1758 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 1759 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT 0 1760 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ 1761 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) 1762 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ 1763 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) 1764 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ 1765 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) 1766 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 1767 do {\ 1768 HWIO_INTLOCK(); \ 1769 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ 1770 HWIO_INTFREE();\ 1771 } while (0) 1772 1773 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 1774 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 1775 1776 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1777 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 1778 1779 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 1780 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 1781 1782 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 1783 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 1784 1785 //// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL //// 1786 1787 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) (x+0x00000024) 1788 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) (x+0x00000024) 1789 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0x007fffff 1790 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT 0 1791 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ 1792 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) 1793 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ 1794 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) 1795 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ 1796 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) 1797 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 1798 do {\ 1799 HWIO_INTLOCK(); \ 1800 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ 1801 HWIO_INTFREE();\ 1802 } while (0) 1803 1804 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 1805 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 1806 1807 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 1808 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 1809 1810 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 1811 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 1812 1813 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 1814 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 1815 1816 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 1817 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 1818 1819 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL //// 1820 1821 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000028) 1822 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000028) 1823 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 1824 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT 0 1825 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ 1826 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) 1827 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ 1828 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) 1829 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ 1830 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) 1831 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 1832 do {\ 1833 HWIO_INTLOCK(); \ 1834 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ 1835 HWIO_INTFREE();\ 1836 } while (0) 1837 1838 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 1839 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 1840 1841 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 1842 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 1843 1844 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS //// 1845 1846 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) (x+0x0000002c) 1847 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) (x+0x0000002c) 1848 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0x0000ffff 1849 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT 0 1850 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ 1851 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) 1852 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ 1853 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) 1854 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ 1855 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) 1856 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 1857 do {\ 1858 HWIO_INTLOCK(); \ 1859 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ 1860 HWIO_INTFREE();\ 1861 } while (0) 1862 1863 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 1864 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 1865 1866 //// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS //// 1867 1868 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000030) 1869 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000030) 1870 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff 1871 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT 0 1872 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ 1873 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) 1874 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ 1875 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) 1876 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ 1877 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) 1878 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 1879 do {\ 1880 HWIO_INTLOCK(); \ 1881 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ 1882 HWIO_INTFREE();\ 1883 } while (0) 1884 1885 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 1886 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 1887 1888 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 1889 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 1890 1891 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 //// 1892 1893 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) (x+0x00000034) 1894 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) (x+0x00000034) 1895 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x01ffffff 1896 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT 0 1897 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ 1898 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) 1899 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ 1900 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) 1901 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ 1902 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) 1903 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ 1904 do {\ 1905 HWIO_INTLOCK(); \ 1906 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ 1907 HWIO_INTFREE();\ 1908 } while (0) 1909 1910 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 1911 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 1912 1913 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0x00fff000 1914 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc 1915 1916 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0x00000fff 1917 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 1918 1919 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 //// 1920 1921 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) (x+0x00000038) 1922 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) (x+0x00000038) 1923 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x00000fff 1924 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT 0 1925 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ 1926 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) 1927 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ 1928 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) 1929 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ 1930 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) 1931 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ 1932 do {\ 1933 HWIO_INTLOCK(); \ 1934 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ 1935 HWIO_INTFREE();\ 1936 } while (0) 1937 1938 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff 1939 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 1940 1941 //// Register WFSS_CE_COMMON_R0_CE_SECURITY //// 1942 1943 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) (x+0x0000003c) 1944 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) (x+0x0000003c) 1945 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0x00ffffff 1946 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT 0 1947 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ 1948 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) 1949 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ 1950 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) 1951 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ 1952 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) 1953 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ 1954 do {\ 1955 HWIO_INTLOCK(); \ 1956 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ 1957 HWIO_INTFREE();\ 1958 } while (0) 1959 1960 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 1961 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc 1962 1963 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0x00000fff 1964 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 1965 1966 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 //// 1967 1968 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) (x+0x00000040) 1969 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) (x+0x00000040) 1970 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x01ffffff 1971 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT 0 1972 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ 1973 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) 1974 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ 1975 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) 1976 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ 1977 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) 1978 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ 1979 do {\ 1980 HWIO_INTLOCK(); \ 1981 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ 1982 HWIO_INTFREE();\ 1983 } while (0) 1984 1985 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 1986 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 1987 1988 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0x00fff000 1989 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc 1990 1991 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0x00000fff 1992 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 1993 1994 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 //// 1995 1996 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) (x+0x00000044) 1997 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) (x+0x00000044) 1998 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x00000fff 1999 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT 0 2000 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ 2001 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) 2002 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ 2003 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) 2004 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ 2005 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) 2006 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ 2007 do {\ 2008 HWIO_INTLOCK(); \ 2009 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ 2010 HWIO_INTFREE();\ 2011 } while (0) 2012 2013 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff 2014 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 2015 2016 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 //// 2017 2018 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) (x+0x00000048) 2019 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) (x+0x00000048) 2020 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff 2021 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT 0 2022 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ 2023 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) 2024 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ 2025 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) 2026 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ 2027 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) 2028 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ 2029 do {\ 2030 HWIO_INTLOCK(); \ 2031 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ 2032 HWIO_INTFREE();\ 2033 } while (0) 2034 2035 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff 2036 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 2037 2038 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 //// 2039 2040 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) (x+0x0000004c) 2041 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) (x+0x0000004c) 2042 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0x00000001 2043 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT 0 2044 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ 2045 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) 2046 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ 2047 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) 2048 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ 2049 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) 2050 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ 2051 do {\ 2052 HWIO_INTLOCK(); \ 2053 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ 2054 HWIO_INTFREE();\ 2055 } while (0) 2056 2057 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x00000001 2058 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 2059 2060 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 //// 2061 2062 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) (x+0x00000050) 2063 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) (x+0x00000050) 2064 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff 2065 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT 0 2066 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ 2067 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) 2068 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ 2069 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) 2070 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ 2071 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) 2072 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ 2073 do {\ 2074 HWIO_INTLOCK(); \ 2075 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ 2076 HWIO_INTFREE();\ 2077 } while (0) 2078 2079 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff 2080 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 2081 2082 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 //// 2083 2084 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) (x+0x00000054) 2085 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) (x+0x00000054) 2086 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff 2087 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT 0 2088 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ 2089 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) 2090 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ 2091 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) 2092 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ 2093 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) 2094 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ 2095 do {\ 2096 HWIO_INTLOCK(); \ 2097 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ 2098 HWIO_INTFREE();\ 2099 } while (0) 2100 2101 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff 2102 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 2103 2104 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 //// 2105 2106 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) (x+0x00000058) 2107 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) (x+0x00000058) 2108 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff 2109 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT 0 2110 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ 2111 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) 2112 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ 2113 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) 2114 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ 2115 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) 2116 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ 2117 do {\ 2118 HWIO_INTLOCK(); \ 2119 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ 2120 HWIO_INTFREE();\ 2121 } while (0) 2122 2123 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff 2124 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 2125 2126 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 //// 2127 2128 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) (x+0x0000005c) 2129 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) (x+0x0000005c) 2130 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff 2131 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT 0 2132 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ 2133 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) 2134 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ 2135 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) 2136 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ 2137 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) 2138 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ 2139 do {\ 2140 HWIO_INTLOCK(); \ 2141 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ 2142 HWIO_INTFREE();\ 2143 } while (0) 2144 2145 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff 2146 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 2147 2148 //// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS //// 2149 2150 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x) (x+0x00000060) 2151 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x) (x+0x00000060) 2152 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK 0xfffdffff 2153 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT 0 2154 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ 2155 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) 2156 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ 2157 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) 2158 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ 2159 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) 2160 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ 2161 do {\ 2162 HWIO_INTLOCK(); \ 2163 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ 2164 HWIO_INTFREE();\ 2165 } while (0) 2166 2167 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 2168 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f 2169 2170 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK 0x40000000 2171 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT 0x1e 2172 2173 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK 0x3ffc0000 2174 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT 0x12 2175 2176 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK 0x00010000 2177 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT 0x10 2178 2179 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK 0x0000f000 2180 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT 0xc 2181 2182 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff 2183 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 2184 2185 //// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR //// 2186 2187 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x) (x+0x00000064) 2188 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x) (x+0x00000064) 2189 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK 0xffffffff 2190 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT 0 2191 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x) \ 2192 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK) 2193 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask) \ 2194 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) 2195 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val) \ 2196 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val) 2197 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \ 2198 do {\ 2199 HWIO_INTLOCK(); \ 2200 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \ 2201 HWIO_INTFREE();\ 2202 } while (0) 2203 2204 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK 0xffffffff 2205 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT 0x0 2206 2207 //// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// 2208 2209 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) 2210 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) (x+0x00000400) 2211 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x000000ff 2212 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT 0 2213 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ 2214 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) 2215 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ 2216 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) 2217 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ 2218 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) 2219 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 2220 do {\ 2221 HWIO_INTLOCK(); \ 2222 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ 2223 HWIO_INTFREE();\ 2224 } while (0) 2225 2226 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff 2227 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 2228 2229 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 //// 2230 2231 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00000404) 2232 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00000404) 2233 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff 2234 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT 0 2235 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ 2236 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) 2237 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ 2238 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) 2239 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ 2240 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) 2241 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 2242 do {\ 2243 HWIO_INTLOCK(); \ 2244 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ 2245 HWIO_INTFREE();\ 2246 } while (0) 2247 2248 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 2249 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 2250 2251 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 //// 2252 2253 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00000408) 2254 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00000408) 2255 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff 2256 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT 0 2257 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ 2258 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) 2259 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ 2260 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) 2261 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ 2262 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) 2263 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 2264 do {\ 2265 HWIO_INTLOCK(); \ 2266 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ 2267 HWIO_INTFREE();\ 2268 } while (0) 2269 2270 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 2271 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 2272 2273 //// Register WFSS_CE_COMMON_R1_TESTBUS_LOW //// 2274 2275 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) (x+0x0000040c) 2276 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) (x+0x0000040c) 2277 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff 2278 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT 0 2279 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ 2280 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) 2281 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ 2282 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) 2283 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ 2284 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) 2285 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 2286 do {\ 2287 HWIO_INTLOCK(); \ 2288 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ 2289 HWIO_INTFREE();\ 2290 } while (0) 2291 2292 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 2293 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 2294 2295 //// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH //// 2296 2297 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) (x+0x00000410) 2298 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) (x+0x00000410) 2299 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0x000000ff 2300 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT 0 2301 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ 2302 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) 2303 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ 2304 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) 2305 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ 2306 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) 2307 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 2308 do {\ 2309 HWIO_INTLOCK(); \ 2310 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ 2311 HWIO_INTFREE();\ 2312 } while (0) 2313 2314 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 2315 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 2316 2317 //// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL //// 2318 2319 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00000414) 2320 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00000414) 2321 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 2322 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 2323 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 2324 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 2325 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 2326 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 2327 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 2328 out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 2329 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 2330 do {\ 2331 HWIO_INTLOCK(); \ 2332 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 2333 HWIO_INTFREE();\ 2334 } while (0) 2335 2336 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 2337 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 2338 2339 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 2340 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 2341 2342 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 2343 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 2344 2345 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 2346 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 2347 2348 //// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK //// 2349 2350 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00000418) 2351 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00000418) 2352 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x00000001 2353 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT 0 2354 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ 2355 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) 2356 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ 2357 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) 2358 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ 2359 out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) 2360 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 2361 do {\ 2362 HWIO_INTLOCK(); \ 2363 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ 2364 HWIO_INTFREE();\ 2365 } while (0) 2366 2367 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 2368 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 2369 2370 2371 /////////////////////////////////////////////////////////////////////////////////////////////// 2372 // Register Data for Block WFSS_CE_REG 2373 /////////////////////////////////////////////////////////////////////////////////////////////// 2374 2375 2376 #endif 2377 2378