1 /*
2  * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 // $ATH_LICENSE_HW_HDR_C$
20 //
21 // DO NOT EDIT!  This file is automatically generated
22 //               These definitions are tied to a particular hardware layout
23 
24 
25 #ifndef _RX_MSDU_END_H_
26 #define _RX_MSDU_END_H_
27 #if !defined(__ASSEMBLER__)
28 #endif
29 
30 
31 // ################ START SUMMARY #################
32 //
33 //	Dword	Fields
34 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
35 //	1	ip_hdr_chksum[15:0], tcp_udp_chksum[31:16]
36 //	2	key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16]
37 //	3	ext_wapi_pn_95_64[31:0]
38 //	4	ext_wapi_pn_127_96[31:0]
39 //	5	reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28]
40 //	6	ipv6_options_crc[31:0]
41 //	7	tcp_seq_number[31:0]
42 //	8	tcp_ack_number[31:0]
43 //	9	tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16]
44 //	10	da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21]
45 //	11	rule_indication_31_0[31:0]
46 //	12	rule_indication_63_32[31:0]
47 //	13	sa_idx[15:0], da_idx[31:16]
48 //	14	msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26]
49 //	15	fse_metadata[31:0]
50 //	16	cce_metadata[15:0], sa_sw_peer_id[31:16]
51 //
52 // ################ END SUMMARY #################
53 
54 #define NUM_OF_DWORDS_RX_MSDU_END 17
55 
56 struct rx_msdu_end {
57              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
58                       sw_frame_group_id               :  7, //[8:2]
59                       reserved_0                      :  7, //[15:9]
60                       phy_ppdu_id                     : 16; //[31:16]
61              uint32_t ip_hdr_chksum                   : 16, //[15:0]
62                       tcp_udp_chksum                  : 16; //[31:16]
63              uint32_t key_id_octet                    :  8, //[7:0]
64                       cce_super_rule                  :  6, //[13:8]
65                       cce_classify_not_done_truncate  :  1, //[14]
66                       cce_classify_not_done_cce_dis   :  1, //[15]
67                       ext_wapi_pn_63_48               : 16; //[31:16]
68              uint32_t ext_wapi_pn_95_64               : 32; //[31:0]
69              uint32_t ext_wapi_pn_127_96              : 32; //[31:0]
70              uint32_t reported_mpdu_length            : 14, //[13:0]
71                       first_msdu                      :  1, //[14]
72                       last_msdu                       :  1, //[15]
73                       sa_idx_timeout                  :  1, //[16]
74                       da_idx_timeout                  :  1, //[17]
75                       msdu_limit_error                :  1, //[18]
76                       flow_idx_timeout                :  1, //[19]
77                       flow_idx_invalid                :  1, //[20]
78                       wifi_parser_error               :  1, //[21]
79                       amsdu_parser_error              :  1, //[22]
80                       sa_is_valid                     :  1, //[23]
81                       da_is_valid                     :  1, //[24]
82                       da_is_mcbc                      :  1, //[25]
83                       l3_header_padding               :  2, //[27:26]
84                       reserved_5a                     :  4; //[31:28]
85              uint32_t ipv6_options_crc                : 32; //[31:0]
86              uint32_t tcp_seq_number                  : 32; //[31:0]
87              uint32_t tcp_ack_number                  : 32; //[31:0]
88              uint32_t tcp_flag                        :  9, //[8:0]
89                       lro_eligible                    :  1, //[9]
90                       reserved_9a                     :  6, //[15:10]
91                       window_size                     : 16; //[31:16]
92              uint32_t da_offset                       :  6, //[5:0]
93                       sa_offset                       :  6, //[11:6]
94                       da_offset_valid                 :  1, //[12]
95                       sa_offset_valid                 :  1, //[13]
96                       type_offset                     :  7, //[20:14]
97                       reserved_10a                    : 11; //[31:21]
98              uint32_t rule_indication_31_0            : 32; //[31:0]
99              uint32_t rule_indication_63_32           : 32; //[31:0]
100              uint32_t sa_idx                          : 16, //[15:0]
101                       da_idx                          : 16; //[31:16]
102              uint32_t msdu_drop                       :  1, //[0]
103                       reo_destination_indication      :  5, //[5:1]
104                       flow_idx                        : 20, //[25:6]
105                       reserved_14                     :  6; //[31:26]
106              uint32_t fse_metadata                    : 32; //[31:0]
107              uint32_t cce_metadata                    : 16, //[15:0]
108                       sa_sw_peer_id                   : 16; //[31:16]
109 };
110 
111 /*
112 
113 rxpcu_mpdu_filter_in_category
114 
115 			Field indicates what the reason was that this MPDU frame
116 			was allowed to come into the receive path by RXPCU
117 
118 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
119 			frame filter programming of rxpcu
120 
121 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
122 			regular frame filter and would have been dropped, were it
123 			not for the frame fitting into the 'monitor_client'
124 			category.
125 
126 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
127 			regular frame filter and also did not pass the
128 			rxpcu_monitor_client filter. It would have been dropped
129 			accept that it did pass the 'monitor_other' category.
130 
131 			<legal 0-2>
132 
133 sw_frame_group_id
134 
135 			SW processes frames based on certain classifications.
136 			This field indicates to what sw classification this MPDU is
137 			mapped.
138 
139 			The classification is given in priority order
140 
141 
142 
143 			<enum 0 sw_frame_group_NDP_frame>
144 
145 
146 
147 			<enum 1 sw_frame_group_Multicast_data>
148 
149 			<enum 2 sw_frame_group_Unicast_data>
150 
151 			<enum 3 sw_frame_group_Null_data > This includes mpdus
152 			of type Data Null as well as QoS Data Null
153 
154 
155 
156 			<enum 4 sw_frame_group_mgmt_0000 >
157 
158 			<enum 5 sw_frame_group_mgmt_0001 >
159 
160 			<enum 6 sw_frame_group_mgmt_0010 >
161 
162 			<enum 7 sw_frame_group_mgmt_0011 >
163 
164 			<enum 8 sw_frame_group_mgmt_0100 >
165 
166 			<enum 9 sw_frame_group_mgmt_0101 >
167 
168 			<enum 10 sw_frame_group_mgmt_0110 >
169 
170 			<enum 11 sw_frame_group_mgmt_0111 >
171 
172 			<enum 12 sw_frame_group_mgmt_1000 >
173 
174 			<enum 13 sw_frame_group_mgmt_1001 >
175 
176 			<enum 14 sw_frame_group_mgmt_1010 >
177 
178 			<enum 15 sw_frame_group_mgmt_1011 >
179 
180 			<enum 16 sw_frame_group_mgmt_1100 >
181 
182 			<enum 17 sw_frame_group_mgmt_1101 >
183 
184 			<enum 18 sw_frame_group_mgmt_1110 >
185 
186 			<enum 19 sw_frame_group_mgmt_1111 >
187 
188 
189 
190 			<enum 20 sw_frame_group_ctrl_0000 >
191 
192 			<enum 21 sw_frame_group_ctrl_0001 >
193 
194 			<enum 22 sw_frame_group_ctrl_0010 >
195 
196 			<enum 23 sw_frame_group_ctrl_0011 >
197 
198 			<enum 24 sw_frame_group_ctrl_0100 >
199 
200 			<enum 25 sw_frame_group_ctrl_0101 >
201 
202 			<enum 26 sw_frame_group_ctrl_0110 >
203 
204 			<enum 27 sw_frame_group_ctrl_0111 >
205 
206 			<enum 28 sw_frame_group_ctrl_1000 >
207 
208 			<enum 29 sw_frame_group_ctrl_1001 >
209 
210 			<enum 30 sw_frame_group_ctrl_1010 >
211 
212 			<enum 31 sw_frame_group_ctrl_1011 >
213 
214 			<enum 32 sw_frame_group_ctrl_1100 >
215 
216 			<enum 33 sw_frame_group_ctrl_1101 >
217 
218 			<enum 34 sw_frame_group_ctrl_1110 >
219 
220 			<enum 35 sw_frame_group_ctrl_1111 >
221 
222 
223 
224 			<enum 36 sw_frame_group_unsupported> This covers type 3
225 			and protocol version != 0
226 
227 
228 
229 
230 
231 
232 			<legal 0-37>
233 
234 reserved_0
235 
236 			<legal 0>
237 
238 phy_ppdu_id
239 
240 			A ppdu counter value that PHY increments for every PPDU
241 			received. The counter value wraps around
242 
243 			<legal all>
244 
245 ip_hdr_chksum
246 
247 			This can include the IP header checksum or the pseudo
248 			header checksum used by TCP/UDP checksum.
249 
250 tcp_udp_chksum
251 
252 			The value of the computed TCP/UDP checksum.  A mode bit
253 			selects whether this checksum is the full checksum or the
254 			partial checksum which does not include the pseudo header.
255 
256 key_id_octet
257 
258 			The key ID octet from the IV.  Only valid when
259 			first_msdu is set.
260 
261 cce_super_rule
262 
263 			Indicates the super filter rule
264 
265 cce_classify_not_done_truncate
266 
267 			Classification failed due to truncated frame
268 
269 cce_classify_not_done_cce_dis
270 
271 			Classification failed due to CCE global disable
272 
273 ext_wapi_pn_63_48
274 
275 			Extension PN (packet number) which is only used by WAPI.
276 			This corresponds to WAPI PN bits [63:48] (pn6 and pn7).
277 			The WAPI PN bits [63:0] are in the pn field of the
278 			rx_mpdu_start descriptor.
279 
280 ext_wapi_pn_95_64
281 
282 			Extension PN (packet number) which is only used by WAPI.
283 			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
284 			and pn11).
285 
286 ext_wapi_pn_127_96
287 
288 			Extension PN (packet number) which is only used by WAPI.
289 			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
290 			pn14, pn15).
291 
292 reported_mpdu_length
293 
294 			MPDU length before decapsulation.  Only valid when
295 			first_msdu is set.  This field is taken directly from the
296 			length field of the A-MPDU delimiter or the preamble length
297 			field for non-A-MPDU frames.
298 
299 first_msdu
300 
301 			Indicates the first MSDU of A-MSDU.  If both first_msdu
302 			and last_msdu are set in the MSDU then this is a
303 			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
304 			A-MSDU shall have both first_mpdu and last_mpdu bits set to
305 			0.
306 
307 last_msdu
308 
309 			Indicates the last MSDU of the A-MSDU.  MPDU end status
310 			is only valid when last_msdu is set.
311 
312 sa_idx_timeout
313 
314 			Indicates an unsuccessful MAC source address search due
315 			to the expiring of the search timer.
316 
317 da_idx_timeout
318 
319 			Indicates an unsuccessful MAC destination address search
320 			due to the expiring of the search timer.
321 
322 msdu_limit_error
323 
324 			Indicates that the MSDU threshold was exceeded and thus
325 			all the rest of the MSDUs will not be scattered and will not
326 			be decapsulated but will be DMA'ed in RAW format as a single
327 			MSDU buffer
328 
329 flow_idx_timeout
330 
331 			Indicates an unsuccessful flow search due to the
332 			expiring of the search timer.
333 
334 			<legal all>
335 
336 flow_idx_invalid
337 
338 			flow id is not valid
339 
340 			<legal all>
341 
342 wifi_parser_error
343 
344 			TODO: add details to the description
345 
346 			<legal all>
347 
348 amsdu_parser_error
349 
350 			A-MSDU could not be properly de-agregated.
351 
352 			<legal all>
353 
354 sa_is_valid
355 
356 			Indicates that OLE found a valid SA entry
357 
358 da_is_valid
359 
360 			Indicates that OLE found a valid DA entry
361 
362 da_is_mcbc
363 
364 			Field Only valid if da_is_valid is set
365 
366 
367 
368 			Indicates the DA address was a Multicast of Broadcast
369 			address.
370 
371 l3_header_padding
372 
373 			Number of bytes padded  to make sure that the L3 header
374 			will always start of a Dword   boundary
375 
376 reserved_5a
377 
378 			<legal 0>
379 
380 ipv6_options_crc
381 
382 			32 bit CRC computed out of  IP v6 extension headers
383 
384 tcp_seq_number
385 
386 			TCP sequence number
387 
388 tcp_ack_number
389 
390 			TCP acknowledge number
391 
392 tcp_flag
393 
394 			TCP flags
395 
396 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
397 
398 lro_eligible
399 
400 			Computed out of TCP and IP fields to indicate that this
401 			MSDU is eligible for  LRO
402 
403 reserved_9a
404 
405 			NOTE: DO not assign a field... Internally used in
406 			RXOLE..
407 
408 			<legal 0>
409 
410 window_size
411 
412 			TCP receive window size
413 
414 da_offset
415 
416 			Offset into MSDU buffer for DA
417 
418 sa_offset
419 
420 			Offset into MSDU buffer for SA
421 
422 da_offset_valid
423 
424 			da_offset field is valid. This will be set to 0 in case
425 			of a dynamic A-MSDU when DA is compressed
426 
427 sa_offset_valid
428 
429 			sa_offset field is valid. This will be set to 0 in case
430 			of a dynamic A-MSDU when SA is compressed
431 
432 type_offset
433 
434 			Offset into MSDU buffer for Type
435 
436 reserved_10a
437 
438 			<legal 0>
439 
440 rule_indication_31_0
441 
442 			Bitmap indicating which of rules 31-0 have matched
443 
444 rule_indication_63_32
445 
446 			Bitmap indicating which of rules 63-32 have matched
447 
448 sa_idx
449 
450 			The offset in the address table which matches the MAC
451 			source address.
452 
453 da_idx
454 
455 			The offset in the address table which matches the MAC
456 			source address
457 
458 msdu_drop
459 
460 			When set, REO shall drop this MSDU and not forward it to
461 			any other ring...
462 
463 			<legal all>
464 
465 reo_destination_indication
466 
467 			The ID of the REO exit ring where the MSDU frame shall
468 			push after (MPDU level) reordering has finished.
469 
470 
471 
472 			<enum 0 reo_destination_tcl> Reo will push the frame
473 			into the REO2TCL ring
474 
475 			<enum 1 reo_destination_sw1> Reo will push the frame
476 			into the REO2SW1 ring
477 
478 			<enum 2 reo_destination_sw2> Reo will push the frame
479 			into the REO2SW1 ring
480 
481 			<enum 3 reo_destination_sw3> Reo will push the frame
482 			into the REO2SW1 ring
483 
484 			<enum 4 reo_destination_sw4> Reo will push the frame
485 			into the REO2SW1 ring
486 
487 			<enum 5 reo_destination_release> Reo will push the frame
488 			into the REO_release ring
489 
490 			<enum 6 reo_destination_fw> Reo will push the frame into
491 			the REO2FW ring
492 
493 			<enum 7 reo_destination_7> REO remaps this
494 
495 			<enum 8 reo_destination_8> REO remaps this <enum 9
496 			reo_destination_9> REO remaps this <enum 10
497 			reo_destination_10> REO remaps this
498 
499 			<enum 11 reo_destination_11> REO remaps this
500 
501 			<enum 12 reo_destination_12> REO remaps this <enum 13
502 			reo_destination_13> REO remaps this
503 
504 			<enum 14 reo_destination_14> REO remaps this
505 
506 			<enum 15 reo_destination_15> REO remaps this
507 
508 			<enum 16 reo_destination_16> REO remaps this
509 
510 			<enum 17 reo_destination_17> REO remaps this
511 
512 			<enum 18 reo_destination_18> REO remaps this
513 
514 			<enum 19 reo_destination_19> REO remaps this
515 
516 			<enum 20 reo_destination_20> REO remaps this
517 
518 			<enum 21 reo_destination_21> REO remaps this
519 
520 			<enum 22 reo_destination_22> REO remaps this
521 
522 			<enum 23 reo_destination_23> REO remaps this
523 
524 			<enum 24 reo_destination_24> REO remaps this
525 
526 			<enum 25 reo_destination_25> REO remaps this
527 
528 			<enum 26 reo_destination_26> REO remaps this
529 
530 			<enum 27 reo_destination_27> REO remaps this
531 
532 			<enum 28 reo_destination_28> REO remaps this
533 
534 			<enum 29 reo_destination_29> REO remaps this
535 
536 			<enum 30 reo_destination_30> REO remaps this
537 
538 			<enum 31 reo_destination_31> REO remaps this
539 
540 
541 
542 			<legal all>
543 
544 flow_idx
545 
546 			Flow table index
547 
548 			<legal all>
549 
550 reserved_14
551 
552 			<legal 0>
553 
554 fse_metadata
555 
556 			FSE related meta data:
557 
558 			<legal all>
559 
560 cce_metadata
561 
562 			CCE related meta data:
563 
564 			<legal all>
565 
566 sa_sw_peer_id
567 
568 			sw_peer_id from the address search entry corresponding
569 			to the source address of the MSDU
570 
571 			<legal 0>
572 */
573 
574 
575 /* Description		RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
576 
577 			Field indicates what the reason was that this MPDU frame
578 			was allowed to come into the receive path by RXPCU
579 
580 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
581 			frame filter programming of rxpcu
582 
583 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
584 			regular frame filter and would have been dropped, were it
585 			not for the frame fitting into the 'monitor_client'
586 			category.
587 
588 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
589 			regular frame filter and also did not pass the
590 			rxpcu_monitor_client filter. It would have been dropped
591 			accept that it did pass the 'monitor_other' category.
592 
593 			<legal 0-2>
594 */
595 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
596 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
597 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
598 
599 /* Description		RX_MSDU_END_0_SW_FRAME_GROUP_ID
600 
601 			SW processes frames based on certain classifications.
602 			This field indicates to what sw classification this MPDU is
603 			mapped.
604 
605 			The classification is given in priority order
606 
607 
608 
609 			<enum 0 sw_frame_group_NDP_frame>
610 
611 
612 
613 			<enum 1 sw_frame_group_Multicast_data>
614 
615 			<enum 2 sw_frame_group_Unicast_data>
616 
617 			<enum 3 sw_frame_group_Null_data > This includes mpdus
618 			of type Data Null as well as QoS Data Null
619 
620 
621 
622 			<enum 4 sw_frame_group_mgmt_0000 >
623 
624 			<enum 5 sw_frame_group_mgmt_0001 >
625 
626 			<enum 6 sw_frame_group_mgmt_0010 >
627 
628 			<enum 7 sw_frame_group_mgmt_0011 >
629 
630 			<enum 8 sw_frame_group_mgmt_0100 >
631 
632 			<enum 9 sw_frame_group_mgmt_0101 >
633 
634 			<enum 10 sw_frame_group_mgmt_0110 >
635 
636 			<enum 11 sw_frame_group_mgmt_0111 >
637 
638 			<enum 12 sw_frame_group_mgmt_1000 >
639 
640 			<enum 13 sw_frame_group_mgmt_1001 >
641 
642 			<enum 14 sw_frame_group_mgmt_1010 >
643 
644 			<enum 15 sw_frame_group_mgmt_1011 >
645 
646 			<enum 16 sw_frame_group_mgmt_1100 >
647 
648 			<enum 17 sw_frame_group_mgmt_1101 >
649 
650 			<enum 18 sw_frame_group_mgmt_1110 >
651 
652 			<enum 19 sw_frame_group_mgmt_1111 >
653 
654 
655 
656 			<enum 20 sw_frame_group_ctrl_0000 >
657 
658 			<enum 21 sw_frame_group_ctrl_0001 >
659 
660 			<enum 22 sw_frame_group_ctrl_0010 >
661 
662 			<enum 23 sw_frame_group_ctrl_0011 >
663 
664 			<enum 24 sw_frame_group_ctrl_0100 >
665 
666 			<enum 25 sw_frame_group_ctrl_0101 >
667 
668 			<enum 26 sw_frame_group_ctrl_0110 >
669 
670 			<enum 27 sw_frame_group_ctrl_0111 >
671 
672 			<enum 28 sw_frame_group_ctrl_1000 >
673 
674 			<enum 29 sw_frame_group_ctrl_1001 >
675 
676 			<enum 30 sw_frame_group_ctrl_1010 >
677 
678 			<enum 31 sw_frame_group_ctrl_1011 >
679 
680 			<enum 32 sw_frame_group_ctrl_1100 >
681 
682 			<enum 33 sw_frame_group_ctrl_1101 >
683 
684 			<enum 34 sw_frame_group_ctrl_1110 >
685 
686 			<enum 35 sw_frame_group_ctrl_1111 >
687 
688 
689 
690 			<enum 36 sw_frame_group_unsupported> This covers type 3
691 			and protocol version != 0
692 
693 
694 
695 
696 
697 
698 			<legal 0-37>
699 */
700 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
701 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
702 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
703 
704 /* Description		RX_MSDU_END_0_RESERVED_0
705 
706 			<legal 0>
707 */
708 #define RX_MSDU_END_0_RESERVED_0_OFFSET                              0x00000000
709 #define RX_MSDU_END_0_RESERVED_0_LSB                                 9
710 #define RX_MSDU_END_0_RESERVED_0_MASK                                0x0000fe00
711 
712 /* Description		RX_MSDU_END_0_PHY_PPDU_ID
713 
714 			A ppdu counter value that PHY increments for every PPDU
715 			received. The counter value wraps around
716 
717 			<legal all>
718 */
719 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
720 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB                                16
721 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
722 
723 /* Description		RX_MSDU_END_1_IP_HDR_CHKSUM
724 
725 			This can include the IP header checksum or the pseudo
726 			header checksum used by TCP/UDP checksum.
727 */
728 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET                           0x00000004
729 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB                              0
730 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK                             0x0000ffff
731 
732 /* Description		RX_MSDU_END_1_TCP_UDP_CHKSUM
733 
734 			The value of the computed TCP/UDP checksum.  A mode bit
735 			selects whether this checksum is the full checksum or the
736 			partial checksum which does not include the pseudo header.
737 */
738 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET                          0x00000004
739 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB                             16
740 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK                            0xffff0000
741 
742 /* Description		RX_MSDU_END_2_KEY_ID_OCTET
743 
744 			The key ID octet from the IV.  Only valid when
745 			first_msdu is set.
746 */
747 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET                            0x00000008
748 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB                               0
749 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK                              0x000000ff
750 
751 /* Description		RX_MSDU_END_2_CCE_SUPER_RULE
752 
753 			Indicates the super filter rule
754 */
755 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET                          0x00000008
756 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB                             8
757 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK                            0x00003f00
758 
759 /* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE
760 
761 			Classification failed due to truncated frame
762 */
763 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET          0x00000008
764 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB             14
765 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK            0x00004000
766 
767 /* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS
768 
769 			Classification failed due to CCE global disable
770 */
771 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET           0x00000008
772 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB              15
773 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK             0x00008000
774 
775 /* Description		RX_MSDU_END_2_EXT_WAPI_PN_63_48
776 
777 			Extension PN (packet number) which is only used by WAPI.
778 			This corresponds to WAPI PN bits [63:48] (pn6 and pn7).
779 			The WAPI PN bits [63:0] are in the pn field of the
780 			rx_mpdu_start descriptor.
781 */
782 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET                       0x00000008
783 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB                          16
784 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK                         0xffff0000
785 
786 /* Description		RX_MSDU_END_3_EXT_WAPI_PN_95_64
787 
788 			Extension PN (packet number) which is only used by WAPI.
789 			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
790 			and pn11).
791 */
792 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET                       0x0000000c
793 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB                          0
794 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK                         0xffffffff
795 
796 /* Description		RX_MSDU_END_4_EXT_WAPI_PN_127_96
797 
798 			Extension PN (packet number) which is only used by WAPI.
799 			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
800 			pn14, pn15).
801 */
802 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET                      0x00000010
803 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB                         0
804 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK                        0xffffffff
805 
806 /* Description		RX_MSDU_END_5_REPORTED_MPDU_LENGTH
807 
808 			MPDU length before decapsulation.  Only valid when
809 			first_msdu is set.  This field is taken directly from the
810 			length field of the A-MPDU delimiter or the preamble length
811 			field for non-A-MPDU frames.
812 */
813 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET                    0x00000014
814 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB                       0
815 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK                      0x00003fff
816 
817 /* Description		RX_MSDU_END_5_FIRST_MSDU
818 
819 			Indicates the first MSDU of A-MSDU.  If both first_msdu
820 			and last_msdu are set in the MSDU then this is a
821 			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
822 			A-MSDU shall have both first_mpdu and last_mpdu bits set to
823 			0.
824 */
825 #define RX_MSDU_END_5_FIRST_MSDU_OFFSET                              0x00000014
826 #define RX_MSDU_END_5_FIRST_MSDU_LSB                                 14
827 #define RX_MSDU_END_5_FIRST_MSDU_MASK                                0x00004000
828 
829 /* Description		RX_MSDU_END_5_LAST_MSDU
830 
831 			Indicates the last MSDU of the A-MSDU.  MPDU end status
832 			is only valid when last_msdu is set.
833 */
834 #define RX_MSDU_END_5_LAST_MSDU_OFFSET                               0x00000014
835 #define RX_MSDU_END_5_LAST_MSDU_LSB                                  15
836 #define RX_MSDU_END_5_LAST_MSDU_MASK                                 0x00008000
837 
838 /* Description		RX_MSDU_END_5_SA_IDX_TIMEOUT
839 
840 			Indicates an unsuccessful MAC source address search due
841 			to the expiring of the search timer.
842 */
843 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET                          0x00000014
844 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB                             16
845 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK                            0x00010000
846 
847 /* Description		RX_MSDU_END_5_DA_IDX_TIMEOUT
848 
849 			Indicates an unsuccessful MAC destination address search
850 			due to the expiring of the search timer.
851 */
852 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET                          0x00000014
853 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB                             17
854 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK                            0x00020000
855 
856 /* Description		RX_MSDU_END_5_MSDU_LIMIT_ERROR
857 
858 			Indicates that the MSDU threshold was exceeded and thus
859 			all the rest of the MSDUs will not be scattered and will not
860 			be decapsulated but will be DMA'ed in RAW format as a single
861 			MSDU buffer
862 */
863 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET                        0x00000014
864 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB                           18
865 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK                          0x00040000
866 
867 /* Description		RX_MSDU_END_5_FLOW_IDX_TIMEOUT
868 
869 			Indicates an unsuccessful flow search due to the
870 			expiring of the search timer.
871 
872 			<legal all>
873 */
874 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET                        0x00000014
875 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB                           19
876 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK                          0x00080000
877 
878 /* Description		RX_MSDU_END_5_FLOW_IDX_INVALID
879 
880 			flow id is not valid
881 
882 			<legal all>
883 */
884 #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET                        0x00000014
885 #define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB                           20
886 #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK                          0x00100000
887 
888 /* Description		RX_MSDU_END_5_WIFI_PARSER_ERROR
889 
890 			TODO: add details to the description
891 
892 			<legal all>
893 */
894 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET                       0x00000014
895 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB                          21
896 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK                         0x00200000
897 
898 /* Description		RX_MSDU_END_5_AMSDU_PARSER_ERROR
899 
900 			A-MSDU could not be properly de-agregated.
901 
902 			<legal all>
903 */
904 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET                      0x00000014
905 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB                         22
906 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK                        0x00400000
907 
908 /* Description		RX_MSDU_END_5_SA_IS_VALID
909 
910 			Indicates that OLE found a valid SA entry
911 */
912 #define RX_MSDU_END_5_SA_IS_VALID_OFFSET                             0x00000014
913 #define RX_MSDU_END_5_SA_IS_VALID_LSB                                23
914 #define RX_MSDU_END_5_SA_IS_VALID_MASK                               0x00800000
915 
916 /* Description		RX_MSDU_END_5_DA_IS_VALID
917 
918 			Indicates that OLE found a valid DA entry
919 */
920 #define RX_MSDU_END_5_DA_IS_VALID_OFFSET                             0x00000014
921 #define RX_MSDU_END_5_DA_IS_VALID_LSB                                24
922 #define RX_MSDU_END_5_DA_IS_VALID_MASK                               0x01000000
923 
924 /* Description		RX_MSDU_END_5_DA_IS_MCBC
925 
926 			Field Only valid if da_is_valid is set
927 
928 
929 
930 			Indicates the DA address was a Multicast of Broadcast
931 			address.
932 */
933 #define RX_MSDU_END_5_DA_IS_MCBC_OFFSET                              0x00000014
934 #define RX_MSDU_END_5_DA_IS_MCBC_LSB                                 25
935 #define RX_MSDU_END_5_DA_IS_MCBC_MASK                                0x02000000
936 
937 /* Description		RX_MSDU_END_5_L3_HEADER_PADDING
938 
939 			Number of bytes padded  to make sure that the L3 header
940 			will always start of a Dword   boundary
941 */
942 #define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET                       0x00000014
943 #define RX_MSDU_END_5_L3_HEADER_PADDING_LSB                          26
944 #define RX_MSDU_END_5_L3_HEADER_PADDING_MASK                         0x0c000000
945 
946 /* Description		RX_MSDU_END_5_RESERVED_5A
947 
948 			<legal 0>
949 */
950 #define RX_MSDU_END_5_RESERVED_5A_OFFSET                             0x00000014
951 #define RX_MSDU_END_5_RESERVED_5A_LSB                                28
952 #define RX_MSDU_END_5_RESERVED_5A_MASK                               0xf0000000
953 
954 /* Description		RX_MSDU_END_6_IPV6_OPTIONS_CRC
955 
956 			32 bit CRC computed out of  IP v6 extension headers
957 */
958 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET                        0x00000018
959 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB                           0
960 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK                          0xffffffff
961 
962 /* Description		RX_MSDU_END_7_TCP_SEQ_NUMBER
963 
964 			TCP sequence number
965 */
966 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET                          0x0000001c
967 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB                             0
968 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK                            0xffffffff
969 
970 /* Description		RX_MSDU_END_8_TCP_ACK_NUMBER
971 
972 			TCP acknowledge number
973 */
974 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET                          0x00000020
975 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB                             0
976 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK                            0xffffffff
977 
978 /* Description		RX_MSDU_END_9_TCP_FLAG
979 
980 			TCP flags
981 
982 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
983 */
984 #define RX_MSDU_END_9_TCP_FLAG_OFFSET                                0x00000024
985 #define RX_MSDU_END_9_TCP_FLAG_LSB                                   0
986 #define RX_MSDU_END_9_TCP_FLAG_MASK                                  0x000001ff
987 
988 /* Description		RX_MSDU_END_9_LRO_ELIGIBLE
989 
990 			Computed out of TCP and IP fields to indicate that this
991 			MSDU is eligible for  LRO
992 */
993 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET                            0x00000024
994 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB                               9
995 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK                              0x00000200
996 
997 /* Description		RX_MSDU_END_9_RESERVED_9A
998 
999 			NOTE: DO not assign a field... Internally used in
1000 			RXOLE..
1001 
1002 			<legal 0>
1003 */
1004 #define RX_MSDU_END_9_RESERVED_9A_OFFSET                             0x00000024
1005 #define RX_MSDU_END_9_RESERVED_9A_LSB                                10
1006 #define RX_MSDU_END_9_RESERVED_9A_MASK                               0x0000fc00
1007 
1008 /* Description		RX_MSDU_END_9_WINDOW_SIZE
1009 
1010 			TCP receive window size
1011 */
1012 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET                             0x00000024
1013 #define RX_MSDU_END_9_WINDOW_SIZE_LSB                                16
1014 #define RX_MSDU_END_9_WINDOW_SIZE_MASK                               0xffff0000
1015 
1016 /* Description		RX_MSDU_END_10_DA_OFFSET
1017 
1018 			Offset into MSDU buffer for DA
1019 */
1020 #define RX_MSDU_END_10_DA_OFFSET_OFFSET                              0x00000028
1021 #define RX_MSDU_END_10_DA_OFFSET_LSB                                 0
1022 #define RX_MSDU_END_10_DA_OFFSET_MASK                                0x0000003f
1023 
1024 /* Description		RX_MSDU_END_10_SA_OFFSET
1025 
1026 			Offset into MSDU buffer for SA
1027 */
1028 #define RX_MSDU_END_10_SA_OFFSET_OFFSET                              0x00000028
1029 #define RX_MSDU_END_10_SA_OFFSET_LSB                                 6
1030 #define RX_MSDU_END_10_SA_OFFSET_MASK                                0x00000fc0
1031 
1032 /* Description		RX_MSDU_END_10_DA_OFFSET_VALID
1033 
1034 			da_offset field is valid. This will be set to 0 in case
1035 			of a dynamic A-MSDU when DA is compressed
1036 */
1037 #define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET                        0x00000028
1038 #define RX_MSDU_END_10_DA_OFFSET_VALID_LSB                           12
1039 #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK                          0x00001000
1040 
1041 /* Description		RX_MSDU_END_10_SA_OFFSET_VALID
1042 
1043 			sa_offset field is valid. This will be set to 0 in case
1044 			of a dynamic A-MSDU when SA is compressed
1045 */
1046 #define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET                        0x00000028
1047 #define RX_MSDU_END_10_SA_OFFSET_VALID_LSB                           13
1048 #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK                          0x00002000
1049 
1050 /* Description		RX_MSDU_END_10_TYPE_OFFSET
1051 
1052 			Offset into MSDU buffer for Type
1053 */
1054 #define RX_MSDU_END_10_TYPE_OFFSET_OFFSET                            0x00000028
1055 #define RX_MSDU_END_10_TYPE_OFFSET_LSB                               14
1056 #define RX_MSDU_END_10_TYPE_OFFSET_MASK                              0x001fc000
1057 
1058 /* Description		RX_MSDU_END_10_RESERVED_10A
1059 
1060 			<legal 0>
1061 */
1062 #define RX_MSDU_END_10_RESERVED_10A_OFFSET                           0x00000028
1063 #define RX_MSDU_END_10_RESERVED_10A_LSB                              21
1064 #define RX_MSDU_END_10_RESERVED_10A_MASK                             0xffe00000
1065 
1066 /* Description		RX_MSDU_END_11_RULE_INDICATION_31_0
1067 
1068 			Bitmap indicating which of rules 31-0 have matched
1069 */
1070 #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET                   0x0000002c
1071 #define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB                      0
1072 #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK                     0xffffffff
1073 
1074 /* Description		RX_MSDU_END_12_RULE_INDICATION_63_32
1075 
1076 			Bitmap indicating which of rules 63-32 have matched
1077 */
1078 #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET                  0x00000030
1079 #define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB                     0
1080 #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK                    0xffffffff
1081 
1082 /* Description		RX_MSDU_END_13_SA_IDX
1083 
1084 			The offset in the address table which matches the MAC
1085 			source address.
1086 */
1087 #define RX_MSDU_END_13_SA_IDX_OFFSET                                 0x00000034
1088 #define RX_MSDU_END_13_SA_IDX_LSB                                    0
1089 #define RX_MSDU_END_13_SA_IDX_MASK                                   0x0000ffff
1090 
1091 /* Description		RX_MSDU_END_13_DA_IDX
1092 
1093 			The offset in the address table which matches the MAC
1094 			source address
1095 */
1096 #define RX_MSDU_END_13_DA_IDX_OFFSET                                 0x00000034
1097 #define RX_MSDU_END_13_DA_IDX_LSB                                    16
1098 #define RX_MSDU_END_13_DA_IDX_MASK                                   0xffff0000
1099 
1100 /* Description		RX_MSDU_END_14_MSDU_DROP
1101 
1102 			When set, REO shall drop this MSDU and not forward it to
1103 			any other ring...
1104 
1105 			<legal all>
1106 */
1107 #define RX_MSDU_END_14_MSDU_DROP_OFFSET                              0x00000038
1108 #define RX_MSDU_END_14_MSDU_DROP_LSB                                 0
1109 #define RX_MSDU_END_14_MSDU_DROP_MASK                                0x00000001
1110 
1111 /* Description		RX_MSDU_END_14_REO_DESTINATION_INDICATION
1112 
1113 			The ID of the REO exit ring where the MSDU frame shall
1114 			push after (MPDU level) reordering has finished.
1115 
1116 
1117 
1118 			<enum 0 reo_destination_tcl> Reo will push the frame
1119 			into the REO2TCL ring
1120 
1121 			<enum 1 reo_destination_sw1> Reo will push the frame
1122 			into the REO2SW1 ring
1123 
1124 			<enum 2 reo_destination_sw2> Reo will push the frame
1125 			into the REO2SW1 ring
1126 
1127 			<enum 3 reo_destination_sw3> Reo will push the frame
1128 			into the REO2SW1 ring
1129 
1130 			<enum 4 reo_destination_sw4> Reo will push the frame
1131 			into the REO2SW1 ring
1132 
1133 			<enum 5 reo_destination_release> Reo will push the frame
1134 			into the REO_release ring
1135 
1136 			<enum 6 reo_destination_fw> Reo will push the frame into
1137 			the REO2FW ring
1138 
1139 			<enum 7 reo_destination_7> REO remaps this
1140 
1141 			<enum 8 reo_destination_8> REO remaps this <enum 9
1142 			reo_destination_9> REO remaps this <enum 10
1143 			reo_destination_10> REO remaps this
1144 
1145 			<enum 11 reo_destination_11> REO remaps this
1146 
1147 			<enum 12 reo_destination_12> REO remaps this <enum 13
1148 			reo_destination_13> REO remaps this
1149 
1150 			<enum 14 reo_destination_14> REO remaps this
1151 
1152 			<enum 15 reo_destination_15> REO remaps this
1153 
1154 			<enum 16 reo_destination_16> REO remaps this
1155 
1156 			<enum 17 reo_destination_17> REO remaps this
1157 
1158 			<enum 18 reo_destination_18> REO remaps this
1159 
1160 			<enum 19 reo_destination_19> REO remaps this
1161 
1162 			<enum 20 reo_destination_20> REO remaps this
1163 
1164 			<enum 21 reo_destination_21> REO remaps this
1165 
1166 			<enum 22 reo_destination_22> REO remaps this
1167 
1168 			<enum 23 reo_destination_23> REO remaps this
1169 
1170 			<enum 24 reo_destination_24> REO remaps this
1171 
1172 			<enum 25 reo_destination_25> REO remaps this
1173 
1174 			<enum 26 reo_destination_26> REO remaps this
1175 
1176 			<enum 27 reo_destination_27> REO remaps this
1177 
1178 			<enum 28 reo_destination_28> REO remaps this
1179 
1180 			<enum 29 reo_destination_29> REO remaps this
1181 
1182 			<enum 30 reo_destination_30> REO remaps this
1183 
1184 			<enum 31 reo_destination_31> REO remaps this
1185 
1186 
1187 
1188 			<legal all>
1189 */
1190 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET             0x00000038
1191 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB                1
1192 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK               0x0000003e
1193 
1194 /* Description		RX_MSDU_END_14_FLOW_IDX
1195 
1196 			Flow table index
1197 
1198 			<legal all>
1199 */
1200 #define RX_MSDU_END_14_FLOW_IDX_OFFSET                               0x00000038
1201 #define RX_MSDU_END_14_FLOW_IDX_LSB                                  6
1202 #define RX_MSDU_END_14_FLOW_IDX_MASK                                 0x03ffffc0
1203 
1204 /* Description		RX_MSDU_END_14_RESERVED_14
1205 
1206 			<legal 0>
1207 */
1208 #define RX_MSDU_END_14_RESERVED_14_OFFSET                            0x00000038
1209 #define RX_MSDU_END_14_RESERVED_14_LSB                               26
1210 #define RX_MSDU_END_14_RESERVED_14_MASK                              0xfc000000
1211 
1212 /* Description		RX_MSDU_END_15_FSE_METADATA
1213 
1214 			FSE related meta data:
1215 
1216 			<legal all>
1217 */
1218 #define RX_MSDU_END_15_FSE_METADATA_OFFSET                           0x0000003c
1219 #define RX_MSDU_END_15_FSE_METADATA_LSB                              0
1220 #define RX_MSDU_END_15_FSE_METADATA_MASK                             0xffffffff
1221 
1222 /* Description		RX_MSDU_END_16_CCE_METADATA
1223 
1224 			CCE related meta data:
1225 
1226 			<legal all>
1227 */
1228 #define RX_MSDU_END_16_CCE_METADATA_OFFSET                           0x00000040
1229 #define RX_MSDU_END_16_CCE_METADATA_LSB                              0
1230 #define RX_MSDU_END_16_CCE_METADATA_MASK                             0x0000ffff
1231 
1232 /* Description		RX_MSDU_END_16_SA_SW_PEER_ID
1233 
1234 			sw_peer_id from the address search entry corresponding
1235 			to the source address of the MSDU
1236 
1237 			<legal 0>
1238 */
1239 #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET                          0x00000040
1240 #define RX_MSDU_END_16_SA_SW_PEER_ID_LSB                             16
1241 #define RX_MSDU_END_16_SA_SW_PEER_ID_MASK                            0xffff0000
1242 
1243 
1244 #endif // _RX_MSDU_END_H_
1245