1  /*
2   * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for
5   * any purpose with or without fee is hereby granted, provided that the
6   * above copyright notice and this permission notice appear in all
7   * copies.
8   *
9   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10   * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11   * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12   * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13   * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14   * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15   * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16   * PERFORMANCE OF THIS SOFTWARE.
17   */
18  
19  // $ATH_LICENSE_HW_HDR_C$
20  //
21  // DO NOT EDIT!  This file is automatically generated
22  //               These definitions are tied to a particular hardware layout
23  
24  
25  #ifndef _RX_ATTENTION_H_
26  #define _RX_ATTENTION_H_
27  #if !defined(__ASSEMBLER__)
28  #endif
29  
30  
31  // ################ START SUMMARY #################
32  //
33  //	Dword	Fields
34  //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
35  //	1	first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
36  //	2	flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
37  //
38  // ################ END SUMMARY #################
39  
40  #define NUM_OF_DWORDS_RX_ATTENTION 3
41  
42  struct rx_attention {
43               uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
44                        sw_frame_group_id               :  7, //[8:2]
45                        reserved_0                      :  7, //[15:9]
46                        phy_ppdu_id                     : 16; //[31:16]
47               uint32_t first_mpdu                      :  1, //[0]
48                        reserved_1a                     :  1, //[1]
49                        mcast_bcast                     :  1, //[2]
50                        ast_index_not_found             :  1, //[3]
51                        ast_index_timeout               :  1, //[4]
52                        power_mgmt                      :  1, //[5]
53                        non_qos                         :  1, //[6]
54                        null_data                       :  1, //[7]
55                        mgmt_type                       :  1, //[8]
56                        ctrl_type                       :  1, //[9]
57                        more_data                       :  1, //[10]
58                        eosp                            :  1, //[11]
59                        a_msdu_error                    :  1, //[12]
60                        fragment_flag                   :  1, //[13]
61                        order                           :  1, //[14]
62                        cce_match                       :  1, //[15]
63                        overflow_err                    :  1, //[16]
64                        msdu_length_err                 :  1, //[17]
65                        tcp_udp_chksum_fail             :  1, //[18]
66                        ip_chksum_fail                  :  1, //[19]
67                        sa_idx_invalid                  :  1, //[20]
68                        da_idx_invalid                  :  1, //[21]
69                        reserved_1b                     :  1, //[22]
70                        rx_in_tx_decrypt_byp            :  1, //[23]
71                        encrypt_required                :  1, //[24]
72                        directed                        :  1, //[25]
73                        buffer_fragment                 :  1, //[26]
74                        mpdu_length_err                 :  1, //[27]
75                        tkip_mic_err                    :  1, //[28]
76                        decrypt_err                     :  1, //[29]
77                        unencrypted_frame_err           :  1, //[30]
78                        fcs_err                         :  1; //[31]
79               uint32_t flow_idx_timeout                :  1, //[0]
80                        flow_idx_invalid                :  1, //[1]
81                        wifi_parser_error               :  1, //[2]
82                        amsdu_parser_error              :  1, //[3]
83                        sa_idx_timeout                  :  1, //[4]
84                        da_idx_timeout                  :  1, //[5]
85                        msdu_limit_error                :  1, //[6]
86                        da_is_valid                     :  1, //[7]
87                        da_is_mcbc                      :  1, //[8]
88                        sa_is_valid                     :  1, //[9]
89                        decrypt_status_code             :  3, //[12:10]
90                        rx_bitmap_not_updated           :  1, //[13]
91                        reserved_2                      : 17, //[30:14]
92                        msdu_done                       :  1; //[31]
93  };
94  
95  /*
96  
97  rxpcu_mpdu_filter_in_category
98  
99  			Field indicates what the reason was that this MPDU frame
100  			was allowed to come into the receive path by RXPCU
101  
102  			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
103  			frame filter programming of rxpcu
104  
105  			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
106  			regular frame filter and would have been dropped, were it
107  			not for the frame fitting into the 'monitor_client'
108  			category.
109  
110  			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
111  			regular frame filter and also did not pass the
112  			rxpcu_monitor_client filter. It would have been dropped
113  			accept that it did pass the 'monitor_other' category.
114  
115  			<legal 0-2>
116  
117  sw_frame_group_id
118  
119  			SW processes frames based on certain classifications.
120  			This field indicates to what sw classification this MPDU is
121  			mapped.
122  
123  			The classification is given in priority order
124  
125  
126  
127  			<enum 0 sw_frame_group_NDP_frame>
128  
129  
130  
131  			<enum 1 sw_frame_group_Multicast_data>
132  
133  			<enum 2 sw_frame_group_Unicast_data>
134  
135  			<enum 3 sw_frame_group_Null_data > This includes mpdus
136  			of type Data Null as well as QoS Data Null
137  
138  
139  
140  			<enum 4 sw_frame_group_mgmt_0000 >
141  
142  			<enum 5 sw_frame_group_mgmt_0001 >
143  
144  			<enum 6 sw_frame_group_mgmt_0010 >
145  
146  			<enum 7 sw_frame_group_mgmt_0011 >
147  
148  			<enum 8 sw_frame_group_mgmt_0100 >
149  
150  			<enum 9 sw_frame_group_mgmt_0101 >
151  
152  			<enum 10 sw_frame_group_mgmt_0110 >
153  
154  			<enum 11 sw_frame_group_mgmt_0111 >
155  
156  			<enum 12 sw_frame_group_mgmt_1000 >
157  
158  			<enum 13 sw_frame_group_mgmt_1001 >
159  
160  			<enum 14 sw_frame_group_mgmt_1010 >
161  
162  			<enum 15 sw_frame_group_mgmt_1011 >
163  
164  			<enum 16 sw_frame_group_mgmt_1100 >
165  
166  			<enum 17 sw_frame_group_mgmt_1101 >
167  
168  			<enum 18 sw_frame_group_mgmt_1110 >
169  
170  			<enum 19 sw_frame_group_mgmt_1111 >
171  
172  
173  
174  			<enum 20 sw_frame_group_ctrl_0000 >
175  
176  			<enum 21 sw_frame_group_ctrl_0001 >
177  
178  			<enum 22 sw_frame_group_ctrl_0010 >
179  
180  			<enum 23 sw_frame_group_ctrl_0011 >
181  
182  			<enum 24 sw_frame_group_ctrl_0100 >
183  
184  			<enum 25 sw_frame_group_ctrl_0101 >
185  
186  			<enum 26 sw_frame_group_ctrl_0110 >
187  
188  			<enum 27 sw_frame_group_ctrl_0111 >
189  
190  			<enum 28 sw_frame_group_ctrl_1000 >
191  
192  			<enum 29 sw_frame_group_ctrl_1001 >
193  
194  			<enum 30 sw_frame_group_ctrl_1010 >
195  
196  			<enum 31 sw_frame_group_ctrl_1011 >
197  
198  			<enum 32 sw_frame_group_ctrl_1100 >
199  
200  			<enum 33 sw_frame_group_ctrl_1101 >
201  
202  			<enum 34 sw_frame_group_ctrl_1110 >
203  
204  			<enum 35 sw_frame_group_ctrl_1111 >
205  
206  
207  
208  			<enum 36 sw_frame_group_unsupported> This covers type 3
209  			and protocol version != 0
210  
211  
212  
213  
214  
215  
216  			<legal 0-37>
217  
218  reserved_0
219  
220  			<legal 0>
221  
222  phy_ppdu_id
223  
224  			A ppdu counter value that PHY increments for every PPDU
225  			received. The counter value wraps around
226  
227  			<legal all>
228  
229  first_mpdu
230  
231  			Indicates the first MSDU of the PPDU.  If both
232  			first_mpdu and last_mpdu are set in the MSDU then this is a
233  			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
234  			in an A-MPDU shall have both first_mpdu and last_mpdu bits
235  			set to 0.  The PPDU start status will only be valid when
236  			this bit is set.
237  
238  reserved_1a
239  
240  			<legal 0>
241  
242  mcast_bcast
243  
244  			Multicast / broadcast indicator.  Only set when the MAC
245  			address 1 bit 0 is set indicating mcast/bcast and the BSSID
246  			matches one of the 4 BSSID registers. Only set when
247  			first_msdu is set.
248  
249  ast_index_not_found
250  
251  			Only valid when first_msdu is set.
252  
253  
254  
255  			Indicates no AST matching entries within the the max
256  			search count.
257  
258  ast_index_timeout
259  
260  			Only valid when first_msdu is set.
261  
262  
263  
264  			Indicates an unsuccessful search in the address seach
265  			table due to timeout.
266  
267  power_mgmt
268  
269  			Power management bit set in the 802.11 header.  Only set
270  			when first_msdu is set.
271  
272  non_qos
273  
274  			Set if packet is not a non-QoS data frame.  Only set
275  			when first_msdu is set.
276  
277  null_data
278  
279  			Set if frame type indicates either null data or QoS null
280  			data format.  Only set when first_msdu is set.
281  
282  mgmt_type
283  
284  			Set if packet is a management packet.  Only set when
285  			first_msdu is set.
286  
287  ctrl_type
288  
289  			Set if packet is a control packet.  Only set when
290  			first_msdu is set.
291  
292  more_data
293  
294  			Set if more bit in frame control is set.  Only set when
295  			first_msdu is set.
296  
297  eosp
298  
299  			Set if the EOSP (end of service period) bit in the QoS
300  			control field is set.  Only set when first_msdu is set.
301  
302  a_msdu_error
303  
304  			Set if number of MSDUs in A-MSDU is above a threshold or
305  			if the size of the MSDU is invalid.  This receive buffer
306  			will contain all of the remainder of the MSDUs in this MPDU
307  			without decapsulation.
308  
309  fragment_flag
310  
311  			Indicates that this is an 802.11 fragment frame.  This
312  			is set when either the more_frag bit is set in the frame
313  			control or the fragment number is not zero.  Only set when
314  			first_msdu is set.
315  
316  order
317  
318  			Set if the order bit in the frame control is set.  Only
319  			set when first_msdu is set.
320  
321  cce_match
322  
323  			Indicates that this status has a corresponding MSDU that
324  			requires FW processing.  The OLE will have classification
325  			ring mask registers which will indicate the ring(s) for
326  			packets and descriptors which need FW attention.
327  
328  overflow_err
329  
330  			RXPCU Receive FIFO ran out of space to receive the full
331  			MPDU. Therefor this MPDU is terminated early and is thus
332  			corrupted.
333  
334  
335  
336  			This MPDU will not be ACKed.
337  
338  			RXPCU might still be able to correctly receive the
339  			following MPDUs in the PPDU if enough fifo space became
340  			available in time
341  
342  msdu_length_err
343  
344  			Indicates that the MSDU length from the 802.3
345  			encapsulated length field extends beyond the MPDU boundary
346  			or if the length is less than 14 bytes.
347  
348  			Merged with original other_msdu_err: Indicates that the
349  			MSDU threshold was exceeded and thus all the rest of the
350  			MSDUs will not be scattered and will not be decasulated but
351  			will be DMA'ed in RAW format as a single MSDU buffer
352  
353  tcp_udp_chksum_fail
354  
355  			Indicates that the computed checksum (tcp_udp_chksum)
356  			did not match the checksum in the TCP/UDP header.
357  
358  ip_chksum_fail
359  
360  			Indicates that the computed checksum did not match the
361  			checksum in the IP header.
362  
363  sa_idx_invalid
364  
365  			Indicates no matching entry was found in the address
366  			search table for the source MAC address.
367  
368  da_idx_invalid
369  
370  			Indicates no matching entry was found in the address
371  			search table for the destination MAC address.
372  
373  reserved_1b
374  
375  
376  rx_in_tx_decrypt_byp
377  
378  			Indicates that RX packet is not decrypted as Crypto is
379  			busy with TX packet processing.
380  
381  encrypt_required
382  
383  			Indicates that this data type frame is not encrypted
384  			even if the policy for this MPDU requires encryption as
385  			indicated in the peer entry key type.
386  
387  directed
388  
389  			MPDU is a directed packet which means that the RA
390  			matched our STA addresses.  In proxySTA it means that the TA
391  			matched an entry in our address search table with the
392  			corresponding no_ack bit is the address search entry
393  			cleared.
394  
395  buffer_fragment
396  
397  			Indicates that at least one of the rx buffers has been
398  			fragmented.  If set the FW should look at the rx_frag_info
399  			descriptor described below.
400  
401  mpdu_length_err
402  
403  			Indicates that the MPDU was pre-maturely terminated
404  			resulting in a truncated MPDU.  Don't trust the MPDU length
405  			field.
406  
407  tkip_mic_err
408  
409  			Indicates that the MPDU Michael integrity check failed
410  
411  decrypt_err
412  
413  			Indicates that the MPDU decrypt integrity check failed
414  			or CRYPTO received an encrypted frame, but did not get a
415  			valid corresponding key id in the peer entry.
416  
417  unencrypted_frame_err
418  
419  			Copied here by RX OLE from the RX_MPDU_END TLV
420  
421  fcs_err
422  
423  			Indicates that the MPDU FCS check failed
424  
425  flow_idx_timeout
426  
427  			Indicates an unsuccessful flow search due to the
428  			expiring of the search timer.
429  
430  			<legal all>
431  
432  flow_idx_invalid
433  
434  			flow id is not valid
435  
436  			<legal all>
437  
438  wifi_parser_error
439  
440  			TODO: add details to the description
441  
442  			<legal all>
443  
444  amsdu_parser_error
445  
446  			A-MSDU could not be properly de-agregated.
447  
448  			<legal all>
449  
450  sa_idx_timeout
451  
452  			Indicates an unsuccessful MAC source address search due
453  			to the expiring of the search timer.
454  
455  da_idx_timeout
456  
457  			Indicates an unsuccessful MAC destination address search
458  			due to the expiring of the search timer.
459  
460  msdu_limit_error
461  
462  			Indicates that the MSDU threshold was exceeded and thus
463  			all the rest of the MSDUs will not be scattered and will not
464  			be decasulated but will be DMA'ed in RAW format as a single
465  			MSDU buffer
466  
467  da_is_valid
468  
469  			Indicates that OLE found a valid DA entry
470  
471  da_is_mcbc
472  
473  			Field Only valid if da_is_valid is set
474  
475  
476  
477  			Indicates the DA address was a Multicast of Broadcast
478  			address.
479  
480  sa_is_valid
481  
482  			Indicates that OLE found a valid SA entry
483  
484  decrypt_status_code
485  
486  			Field provides insight into the decryption performed
487  
488  
489  
490  			<enum 0 decrypt_ok> Frame had protection enabled and
491  			decrypted properly
492  
493  			<enum 1 decrypt_unprotected_frame > Frame is unprotected
494  			and hence bypassed
495  
496  			<enum 2 decrypt_data_err > Frame has protection enabled
497  			and could not be properly decrypted due to MIC/ICV mismatch
498  			etc.
499  
500  			<enum 3 decrypt_key_invalid > Frame has protection
501  			enabled but the key that was required to decrypt this frame
502  			was not valid
503  
504  			<enum 4 decrypt_peer_entry_invalid > Frame has
505  			protection enabled but the key that was required to decrypt
506  			this frame was not valid
507  
508  			<enum 5 decrypt_other > Reserved for other indications
509  
510  
511  
512  			<legal 0 - 5>
513  
514  rx_bitmap_not_updated
515  
516  			Frame is received, but RXPCU could not update the
517  			receive bitmap due to (temporary) fifo contraints.
518  
519  			<legal all>
520  
521  reserved_2
522  
523  			<legal 0>
524  
525  msdu_done
526  
527  			If set indicates that the RX packet data, RX header
528  			data, RX PPDU start descriptor, RX MPDU start/end
529  			descriptor, RX MSDU start/end descriptors and RX Attention
530  			descriptor are all valid.  This bit must be in the last
531  			octet of the descriptor.
532  */
533  
534  
535  /* Description		RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
536  
537  			Field indicates what the reason was that this MPDU frame
538  			was allowed to come into the receive path by RXPCU
539  
540  			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
541  			frame filter programming of rxpcu
542  
543  			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
544  			regular frame filter and would have been dropped, were it
545  			not for the frame fitting into the 'monitor_client'
546  			category.
547  
548  			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
549  			regular frame filter and also did not pass the
550  			rxpcu_monitor_client filter. It would have been dropped
551  			accept that it did pass the 'monitor_other' category.
552  
553  			<legal 0-2>
554  */
555  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
556  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
557  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
558  
559  /* Description		RX_ATTENTION_0_SW_FRAME_GROUP_ID
560  
561  			SW processes frames based on certain classifications.
562  			This field indicates to what sw classification this MPDU is
563  			mapped.
564  
565  			The classification is given in priority order
566  
567  
568  
569  			<enum 0 sw_frame_group_NDP_frame>
570  
571  
572  
573  			<enum 1 sw_frame_group_Multicast_data>
574  
575  			<enum 2 sw_frame_group_Unicast_data>
576  
577  			<enum 3 sw_frame_group_Null_data > This includes mpdus
578  			of type Data Null as well as QoS Data Null
579  
580  
581  
582  			<enum 4 sw_frame_group_mgmt_0000 >
583  
584  			<enum 5 sw_frame_group_mgmt_0001 >
585  
586  			<enum 6 sw_frame_group_mgmt_0010 >
587  
588  			<enum 7 sw_frame_group_mgmt_0011 >
589  
590  			<enum 8 sw_frame_group_mgmt_0100 >
591  
592  			<enum 9 sw_frame_group_mgmt_0101 >
593  
594  			<enum 10 sw_frame_group_mgmt_0110 >
595  
596  			<enum 11 sw_frame_group_mgmt_0111 >
597  
598  			<enum 12 sw_frame_group_mgmt_1000 >
599  
600  			<enum 13 sw_frame_group_mgmt_1001 >
601  
602  			<enum 14 sw_frame_group_mgmt_1010 >
603  
604  			<enum 15 sw_frame_group_mgmt_1011 >
605  
606  			<enum 16 sw_frame_group_mgmt_1100 >
607  
608  			<enum 17 sw_frame_group_mgmt_1101 >
609  
610  			<enum 18 sw_frame_group_mgmt_1110 >
611  
612  			<enum 19 sw_frame_group_mgmt_1111 >
613  
614  
615  
616  			<enum 20 sw_frame_group_ctrl_0000 >
617  
618  			<enum 21 sw_frame_group_ctrl_0001 >
619  
620  			<enum 22 sw_frame_group_ctrl_0010 >
621  
622  			<enum 23 sw_frame_group_ctrl_0011 >
623  
624  			<enum 24 sw_frame_group_ctrl_0100 >
625  
626  			<enum 25 sw_frame_group_ctrl_0101 >
627  
628  			<enum 26 sw_frame_group_ctrl_0110 >
629  
630  			<enum 27 sw_frame_group_ctrl_0111 >
631  
632  			<enum 28 sw_frame_group_ctrl_1000 >
633  
634  			<enum 29 sw_frame_group_ctrl_1001 >
635  
636  			<enum 30 sw_frame_group_ctrl_1010 >
637  
638  			<enum 31 sw_frame_group_ctrl_1011 >
639  
640  			<enum 32 sw_frame_group_ctrl_1100 >
641  
642  			<enum 33 sw_frame_group_ctrl_1101 >
643  
644  			<enum 34 sw_frame_group_ctrl_1110 >
645  
646  			<enum 35 sw_frame_group_ctrl_1111 >
647  
648  
649  
650  			<enum 36 sw_frame_group_unsupported> This covers type 3
651  			and protocol version != 0
652  
653  
654  
655  
656  
657  
658  			<legal 0-37>
659  */
660  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
661  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
662  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
663  
664  /* Description		RX_ATTENTION_0_RESERVED_0
665  
666  			<legal 0>
667  */
668  #define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
669  #define RX_ATTENTION_0_RESERVED_0_LSB                                9
670  #define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
671  
672  /* Description		RX_ATTENTION_0_PHY_PPDU_ID
673  
674  			A ppdu counter value that PHY increments for every PPDU
675  			received. The counter value wraps around
676  
677  			<legal all>
678  */
679  #define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
680  #define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
681  #define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
682  
683  /* Description		RX_ATTENTION_1_FIRST_MPDU
684  
685  			Indicates the first MSDU of the PPDU.  If both
686  			first_mpdu and last_mpdu are set in the MSDU then this is a
687  			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
688  			in an A-MPDU shall have both first_mpdu and last_mpdu bits
689  			set to 0.  The PPDU start status will only be valid when
690  			this bit is set.
691  */
692  #define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
693  #define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
694  #define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
695  
696  /* Description		RX_ATTENTION_1_RESERVED_1A
697  
698  			<legal 0>
699  */
700  #define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
701  #define RX_ATTENTION_1_RESERVED_1A_LSB                               1
702  #define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
703  
704  /* Description		RX_ATTENTION_1_MCAST_BCAST
705  
706  			Multicast / broadcast indicator.  Only set when the MAC
707  			address 1 bit 0 is set indicating mcast/bcast and the BSSID
708  			matches one of the 4 BSSID registers. Only set when
709  			first_msdu is set.
710  */
711  #define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
712  #define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
713  #define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
714  
715  /* Description		RX_ATTENTION_1_AST_INDEX_NOT_FOUND
716  
717  			Only valid when first_msdu is set.
718  
719  
720  
721  			Indicates no AST matching entries within the the max
722  			search count.
723  */
724  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
725  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
726  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
727  
728  /* Description		RX_ATTENTION_1_AST_INDEX_TIMEOUT
729  
730  			Only valid when first_msdu is set.
731  
732  
733  
734  			Indicates an unsuccessful search in the address seach
735  			table due to timeout.
736  */
737  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
738  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
739  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
740  
741  /* Description		RX_ATTENTION_1_POWER_MGMT
742  
743  			Power management bit set in the 802.11 header.  Only set
744  			when first_msdu is set.
745  */
746  #define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
747  #define RX_ATTENTION_1_POWER_MGMT_LSB                                5
748  #define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
749  
750  /* Description		RX_ATTENTION_1_NON_QOS
751  
752  			Set if packet is not a non-QoS data frame.  Only set
753  			when first_msdu is set.
754  */
755  #define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
756  #define RX_ATTENTION_1_NON_QOS_LSB                                   6
757  #define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
758  
759  /* Description		RX_ATTENTION_1_NULL_DATA
760  
761  			Set if frame type indicates either null data or QoS null
762  			data format.  Only set when first_msdu is set.
763  */
764  #define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
765  #define RX_ATTENTION_1_NULL_DATA_LSB                                 7
766  #define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
767  
768  /* Description		RX_ATTENTION_1_MGMT_TYPE
769  
770  			Set if packet is a management packet.  Only set when
771  			first_msdu is set.
772  */
773  #define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
774  #define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
775  #define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
776  
777  /* Description		RX_ATTENTION_1_CTRL_TYPE
778  
779  			Set if packet is a control packet.  Only set when
780  			first_msdu is set.
781  */
782  #define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
783  #define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
784  #define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
785  
786  /* Description		RX_ATTENTION_1_MORE_DATA
787  
788  			Set if more bit in frame control is set.  Only set when
789  			first_msdu is set.
790  */
791  #define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
792  #define RX_ATTENTION_1_MORE_DATA_LSB                                 10
793  #define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
794  
795  /* Description		RX_ATTENTION_1_EOSP
796  
797  			Set if the EOSP (end of service period) bit in the QoS
798  			control field is set.  Only set when first_msdu is set.
799  */
800  #define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
801  #define RX_ATTENTION_1_EOSP_LSB                                      11
802  #define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
803  
804  /* Description		RX_ATTENTION_1_A_MSDU_ERROR
805  
806  			Set if number of MSDUs in A-MSDU is above a threshold or
807  			if the size of the MSDU is invalid.  This receive buffer
808  			will contain all of the remainder of the MSDUs in this MPDU
809  			without decapsulation.
810  */
811  #define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
812  #define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
813  #define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
814  
815  /* Description		RX_ATTENTION_1_FRAGMENT_FLAG
816  
817  			Indicates that this is an 802.11 fragment frame.  This
818  			is set when either the more_frag bit is set in the frame
819  			control or the fragment number is not zero.  Only set when
820  			first_msdu is set.
821  */
822  #define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
823  #define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
824  #define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
825  
826  /* Description		RX_ATTENTION_1_ORDER
827  
828  			Set if the order bit in the frame control is set.  Only
829  			set when first_msdu is set.
830  */
831  #define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
832  #define RX_ATTENTION_1_ORDER_LSB                                     14
833  #define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
834  
835  /* Description		RX_ATTENTION_1_CCE_MATCH
836  
837  			Indicates that this status has a corresponding MSDU that
838  			requires FW processing.  The OLE will have classification
839  			ring mask registers which will indicate the ring(s) for
840  			packets and descriptors which need FW attention.
841  */
842  #define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
843  #define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
844  #define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
845  
846  /* Description		RX_ATTENTION_1_OVERFLOW_ERR
847  
848  			RXPCU Receive FIFO ran out of space to receive the full
849  			MPDU. Therefor this MPDU is terminated early and is thus
850  			corrupted.
851  
852  
853  
854  			This MPDU will not be ACKed.
855  
856  			RXPCU might still be able to correctly receive the
857  			following MPDUs in the PPDU if enough fifo space became
858  			available in time
859  */
860  #define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
861  #define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
862  #define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
863  
864  /* Description		RX_ATTENTION_1_MSDU_LENGTH_ERR
865  
866  			Indicates that the MSDU length from the 802.3
867  			encapsulated length field extends beyond the MPDU boundary
868  			or if the length is less than 14 bytes.
869  
870  			Merged with original other_msdu_err: Indicates that the
871  			MSDU threshold was exceeded and thus all the rest of the
872  			MSDUs will not be scattered and will not be decasulated but
873  			will be DMA'ed in RAW format as a single MSDU buffer
874  */
875  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
876  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
877  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
878  
879  /* Description		RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
880  
881  			Indicates that the computed checksum (tcp_udp_chksum)
882  			did not match the checksum in the TCP/UDP header.
883  */
884  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
885  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
886  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
887  
888  /* Description		RX_ATTENTION_1_IP_CHKSUM_FAIL
889  
890  			Indicates that the computed checksum did not match the
891  			checksum in the IP header.
892  */
893  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
894  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
895  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
896  
897  /* Description		RX_ATTENTION_1_SA_IDX_INVALID
898  
899  			Indicates no matching entry was found in the address
900  			search table for the source MAC address.
901  */
902  #define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
903  #define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
904  #define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
905  
906  /* Description		RX_ATTENTION_1_DA_IDX_INVALID
907  
908  			Indicates no matching entry was found in the address
909  			search table for the destination MAC address.
910  */
911  #define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
912  #define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
913  #define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
914  
915  /* Description		RX_ATTENTION_1_RESERVED_1B
916  
917  */
918  #define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
919  #define RX_ATTENTION_1_RESERVED_1B_LSB                               22
920  #define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
921  
922  /* Description		RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
923  
924  			Indicates that RX packet is not decrypted as Crypto is
925  			busy with TX packet processing.
926  */
927  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
928  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
929  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
930  
931  /* Description		RX_ATTENTION_1_ENCRYPT_REQUIRED
932  
933  			Indicates that this data type frame is not encrypted
934  			even if the policy for this MPDU requires encryption as
935  			indicated in the peer entry key type.
936  */
937  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
938  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
939  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
940  
941  /* Description		RX_ATTENTION_1_DIRECTED
942  
943  			MPDU is a directed packet which means that the RA
944  			matched our STA addresses.  In proxySTA it means that the TA
945  			matched an entry in our address search table with the
946  			corresponding no_ack bit is the address search entry
947  			cleared.
948  */
949  #define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
950  #define RX_ATTENTION_1_DIRECTED_LSB                                  25
951  #define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
952  
953  /* Description		RX_ATTENTION_1_BUFFER_FRAGMENT
954  
955  			Indicates that at least one of the rx buffers has been
956  			fragmented.  If set the FW should look at the rx_frag_info
957  			descriptor described below.
958  */
959  #define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
960  #define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
961  #define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
962  
963  /* Description		RX_ATTENTION_1_MPDU_LENGTH_ERR
964  
965  			Indicates that the MPDU was pre-maturely terminated
966  			resulting in a truncated MPDU.  Don't trust the MPDU length
967  			field.
968  */
969  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
970  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
971  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
972  
973  /* Description		RX_ATTENTION_1_TKIP_MIC_ERR
974  
975  			Indicates that the MPDU Michael integrity check failed
976  */
977  #define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
978  #define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
979  #define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
980  
981  /* Description		RX_ATTENTION_1_DECRYPT_ERR
982  
983  			Indicates that the MPDU decrypt integrity check failed
984  			or CRYPTO received an encrypted frame, but did not get a
985  			valid corresponding key id in the peer entry.
986  */
987  #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
988  #define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
989  #define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
990  
991  /* Description		RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
992  
993  			Copied here by RX OLE from the RX_MPDU_END TLV
994  */
995  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
996  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
997  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
998  
999  /* Description		RX_ATTENTION_1_FCS_ERR
1000  
1001  			Indicates that the MPDU FCS check failed
1002  */
1003  #define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
1004  #define RX_ATTENTION_1_FCS_ERR_LSB                                   31
1005  #define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
1006  
1007  /* Description		RX_ATTENTION_2_FLOW_IDX_TIMEOUT
1008  
1009  			Indicates an unsuccessful flow search due to the
1010  			expiring of the search timer.
1011  
1012  			<legal all>
1013  */
1014  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
1015  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
1016  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
1017  
1018  /* Description		RX_ATTENTION_2_FLOW_IDX_INVALID
1019  
1020  			flow id is not valid
1021  
1022  			<legal all>
1023  */
1024  #define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
1025  #define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
1026  #define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
1027  
1028  /* Description		RX_ATTENTION_2_WIFI_PARSER_ERROR
1029  
1030  			TODO: add details to the description
1031  
1032  			<legal all>
1033  */
1034  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
1035  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
1036  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
1037  
1038  /* Description		RX_ATTENTION_2_AMSDU_PARSER_ERROR
1039  
1040  			A-MSDU could not be properly de-agregated.
1041  
1042  			<legal all>
1043  */
1044  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
1045  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
1046  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
1047  
1048  /* Description		RX_ATTENTION_2_SA_IDX_TIMEOUT
1049  
1050  			Indicates an unsuccessful MAC source address search due
1051  			to the expiring of the search timer.
1052  */
1053  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
1054  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
1055  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
1056  
1057  /* Description		RX_ATTENTION_2_DA_IDX_TIMEOUT
1058  
1059  			Indicates an unsuccessful MAC destination address search
1060  			due to the expiring of the search timer.
1061  */
1062  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
1063  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
1064  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
1065  
1066  /* Description		RX_ATTENTION_2_MSDU_LIMIT_ERROR
1067  
1068  			Indicates that the MSDU threshold was exceeded and thus
1069  			all the rest of the MSDUs will not be scattered and will not
1070  			be decasulated but will be DMA'ed in RAW format as a single
1071  			MSDU buffer
1072  */
1073  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
1074  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
1075  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
1076  
1077  /* Description		RX_ATTENTION_2_DA_IS_VALID
1078  
1079  			Indicates that OLE found a valid DA entry
1080  */
1081  #define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
1082  #define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
1083  #define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
1084  
1085  /* Description		RX_ATTENTION_2_DA_IS_MCBC
1086  
1087  			Field Only valid if da_is_valid is set
1088  
1089  
1090  
1091  			Indicates the DA address was a Multicast of Broadcast
1092  			address.
1093  */
1094  #define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
1095  #define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
1096  #define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
1097  
1098  /* Description		RX_ATTENTION_2_SA_IS_VALID
1099  
1100  			Indicates that OLE found a valid SA entry
1101  */
1102  #define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
1103  #define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
1104  #define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
1105  
1106  /* Description		RX_ATTENTION_2_DECRYPT_STATUS_CODE
1107  
1108  			Field provides insight into the decryption performed
1109  
1110  
1111  
1112  			<enum 0 decrypt_ok> Frame had protection enabled and
1113  			decrypted properly
1114  
1115  			<enum 1 decrypt_unprotected_frame > Frame is unprotected
1116  			and hence bypassed
1117  
1118  			<enum 2 decrypt_data_err > Frame has protection enabled
1119  			and could not be properly decrypted due to MIC/ICV mismatch
1120  			etc.
1121  
1122  			<enum 3 decrypt_key_invalid > Frame has protection
1123  			enabled but the key that was required to decrypt this frame
1124  			was not valid
1125  
1126  			<enum 4 decrypt_peer_entry_invalid > Frame has
1127  			protection enabled but the key that was required to decrypt
1128  			this frame was not valid
1129  
1130  			<enum 5 decrypt_other > Reserved for other indications
1131  
1132  
1133  
1134  			<legal 0 - 5>
1135  */
1136  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
1137  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
1138  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
1139  
1140  /* Description		RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
1141  
1142  			Frame is received, but RXPCU could not update the
1143  			receive bitmap due to (temporary) fifo contraints.
1144  
1145  			<legal all>
1146  */
1147  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
1148  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
1149  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
1150  
1151  /* Description		RX_ATTENTION_2_RESERVED_2
1152  
1153  			<legal 0>
1154  */
1155  #define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
1156  #define RX_ATTENTION_2_RESERVED_2_LSB                                14
1157  #define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
1158  
1159  /* Description		RX_ATTENTION_2_MSDU_DONE
1160  
1161  			If set indicates that the RX packet data, RX header
1162  			data, RX PPDU start descriptor, RX MPDU start/end
1163  			descriptor, RX MSDU start/end descriptors and RX Attention
1164  			descriptor are all valid.  This bit must be in the last
1165  			octet of the descriptor.
1166  */
1167  #define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
1168  #define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
1169  #define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
1170  
1171  
1172  #endif // _RX_ATTENTION_H_
1173