1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 10/27/2016 22 // User Name:kanalas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __REO_REG_SEQ_REG_H__ 29 #define __REO_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "reo_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block REO_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register REO_R0_GENERAL_ENABLE //// 45 46 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 47 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 48 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0x1fffffff 49 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 50 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 51 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 52 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 53 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 54 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 55 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 56 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x10000000 64 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1c 65 66 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x0e000000 67 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x19 68 69 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK 0x01c00000 70 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT 0x16 71 72 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00200000 73 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x15 74 75 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00100000 76 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x14 77 78 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00080000 79 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x13 80 81 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00040000 82 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x12 83 84 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00020000 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x11 86 87 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00010000 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x10 89 90 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00008000 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0xf 92 93 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00004000 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xe 95 96 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00002000 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xd 98 99 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00001000 100 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xc 101 102 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000800 103 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xb 104 105 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000700 106 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x8 107 108 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000080 109 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x7 110 111 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 112 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 113 114 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 115 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 116 117 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 118 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 119 120 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 121 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 122 123 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 124 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 125 126 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 127 128 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 129 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 130 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffff00 131 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 8 132 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 133 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 134 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 135 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 136 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 137 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 138 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 139 do {\ 140 HWIO_INTLOCK(); \ 141 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 142 HWIO_INTFREE();\ 143 } while (0) 144 145 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 146 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d 147 148 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000 149 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x1a 150 151 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000 152 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x17 153 154 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x14 156 157 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0x11 159 160 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0xe 162 163 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0xb 165 166 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x8 168 169 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 170 171 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 172 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 173 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffff00 174 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 8 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 176 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 177 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 178 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 179 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 180 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 181 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 182 do {\ 183 HWIO_INTLOCK(); \ 184 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 185 HWIO_INTFREE();\ 186 } while (0) 187 188 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 189 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d 190 191 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000 192 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x1a 193 194 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000 195 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x17 196 197 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x14 199 200 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0x11 202 203 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0xe 205 206 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0xb 208 209 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700 210 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x8 211 212 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 213 214 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 215 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 216 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffff00 217 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 8 218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 219 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 220 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 221 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 222 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 223 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 224 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 225 do {\ 226 HWIO_INTLOCK(); \ 227 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 228 HWIO_INTFREE();\ 229 } while (0) 230 231 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 232 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d 233 234 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000 235 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x1a 236 237 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000 238 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x17 239 240 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x14 242 243 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0x11 245 246 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0xe 248 249 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0xb 251 252 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700 253 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x8 254 255 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 256 257 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 258 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 259 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffff00 260 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 8 261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 262 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 263 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 264 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 265 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 266 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 267 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 268 do {\ 269 HWIO_INTLOCK(); \ 270 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 271 HWIO_INTFREE();\ 272 } while (0) 273 274 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 275 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d 276 277 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000 278 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x1a 279 280 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000 281 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x17 282 283 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x14 285 286 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0x11 288 289 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0xe 291 292 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0xb 294 295 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700 296 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x8 297 298 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 299 300 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 301 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 302 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffff00 303 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 8 304 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 305 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 306 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 307 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 308 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 309 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 310 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 311 do {\ 312 HWIO_INTLOCK(); \ 313 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 314 HWIO_INTFREE();\ 315 } while (0) 316 317 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 318 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d 319 320 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000 321 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x1a 322 323 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000 324 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x17 325 326 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x14 328 329 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0x11 331 332 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0xe 334 335 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0xb 337 338 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700 339 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x8 340 341 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 342 343 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 344 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 345 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffff00 346 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 8 347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 348 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 349 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 350 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 351 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 352 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 353 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 354 do {\ 355 HWIO_INTLOCK(); \ 356 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 357 HWIO_INTFREE();\ 358 } while (0) 359 360 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 361 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d 362 363 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000 364 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x1a 365 366 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000 367 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x17 368 369 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x14 371 372 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0x11 374 375 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0xe 377 378 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0xb 380 381 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700 382 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x8 383 384 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 385 386 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 387 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 388 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffff00 389 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 8 390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 391 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 392 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 393 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 394 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 395 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 396 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 397 do {\ 398 HWIO_INTLOCK(); \ 399 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 400 HWIO_INTFREE();\ 401 } while (0) 402 403 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 404 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d 405 406 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000 407 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x1a 408 409 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000 410 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x17 411 412 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x14 414 415 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0x11 417 418 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0xe 420 421 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0xb 423 424 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700 425 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x8 426 427 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 428 429 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 430 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 431 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffff00 432 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 8 433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 434 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 435 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 436 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 437 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 438 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 439 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 440 do {\ 441 HWIO_INTLOCK(); \ 442 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 443 HWIO_INTFREE();\ 444 } while (0) 445 446 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 447 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d 448 449 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000 450 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x1a 451 452 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000 453 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x17 454 455 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x14 457 458 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0x11 460 461 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0xe 463 464 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0xb 466 467 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700 468 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x8 469 470 //// Register REO_R0_TIMESTAMP //// 471 472 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 473 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 474 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 475 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 476 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 477 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 478 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 479 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 480 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 481 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 482 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 483 do {\ 484 HWIO_INTLOCK(); \ 485 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 486 HWIO_INTFREE();\ 487 } while (0) 488 489 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 490 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 491 492 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 493 494 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 495 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 496 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x3fffffff 497 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 498 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 499 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 500 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 501 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 502 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 503 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 504 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 505 do {\ 506 HWIO_INTLOCK(); \ 507 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 508 HWIO_INTFREE();\ 509 } while (0) 510 511 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 512 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b 513 514 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000 515 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT 0x18 516 517 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000 518 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x15 519 520 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x12 522 523 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0xf 525 526 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0xc 528 529 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0x9 531 532 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0 533 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x6 534 535 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x3 537 538 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 540 541 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 542 543 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 544 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 545 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x0003ffff 546 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 547 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 548 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 549 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 550 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 551 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 552 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 553 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 554 do {\ 555 HWIO_INTLOCK(); \ 556 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 557 HWIO_INTFREE();\ 558 } while (0) 559 560 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 561 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf 562 563 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0xc 565 566 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x9 568 569 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x6 571 572 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0x3 574 575 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007 576 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x0 577 578 //// Register REO_R0_IDLE_REQ_CTRL //// 579 580 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 581 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 582 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 583 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 584 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 585 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 586 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 587 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 588 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 589 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 590 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 591 do {\ 592 HWIO_INTLOCK(); \ 593 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 594 HWIO_INTFREE();\ 595 } while (0) 596 597 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 598 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 599 600 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 601 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 602 603 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 604 605 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 606 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 607 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 608 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 609 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 610 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 611 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 612 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 613 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 614 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 615 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 616 do {\ 617 HWIO_INTLOCK(); \ 618 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 619 HWIO_INTFREE();\ 620 } while (0) 621 622 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 623 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 624 625 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 626 627 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 628 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 629 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 630 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 632 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 633 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 634 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 635 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 636 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 637 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 638 do {\ 639 HWIO_INTLOCK(); \ 640 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 641 HWIO_INTFREE();\ 642 } while (0) 643 644 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 645 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 646 647 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 648 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 649 650 //// Register REO_R0_RXDMA2REO0_RING_ID //// 651 652 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 653 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 654 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 655 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 656 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 657 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 658 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 659 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 660 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 661 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 662 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 663 do {\ 664 HWIO_INTLOCK(); \ 665 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 666 HWIO_INTFREE();\ 667 } while (0) 668 669 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 670 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 671 672 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 673 674 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 675 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 676 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 677 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 678 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 679 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 680 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 681 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 682 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 683 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 684 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 685 do {\ 686 HWIO_INTLOCK(); \ 687 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 688 HWIO_INTFREE();\ 689 } while (0) 690 691 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 692 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 693 694 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 695 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 696 697 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 698 699 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 700 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 701 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x0000003f 702 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 703 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 704 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 705 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 706 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 707 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 708 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 709 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 710 do {\ 711 HWIO_INTLOCK(); \ 712 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 713 HWIO_INTFREE();\ 714 } while (0) 715 716 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 717 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 718 719 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 720 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 721 722 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 723 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 724 725 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 727 728 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 730 731 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 733 734 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 735 736 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 737 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 738 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 739 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 740 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 741 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 742 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 743 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 744 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 745 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 746 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 747 do {\ 748 HWIO_INTLOCK(); \ 749 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 750 HWIO_INTFREE();\ 751 } while (0) 752 753 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 754 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 755 756 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 757 758 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 759 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 760 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 761 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 762 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 763 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 764 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 765 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 766 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 767 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 768 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 769 do {\ 770 HWIO_INTLOCK(); \ 771 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 772 HWIO_INTFREE();\ 773 } while (0) 774 775 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 776 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 777 778 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 779 780 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 781 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 782 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 783 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 784 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 785 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 786 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 787 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 788 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 789 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 790 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 791 do {\ 792 HWIO_INTLOCK(); \ 793 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 794 HWIO_INTFREE();\ 795 } while (0) 796 797 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 798 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 799 800 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 801 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 802 803 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 804 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 805 806 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 807 808 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 809 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 810 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 811 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 812 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 813 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 814 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 815 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 816 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 817 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 818 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 819 do {\ 820 HWIO_INTLOCK(); \ 821 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 822 HWIO_INTFREE();\ 823 } while (0) 824 825 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 826 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 827 828 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 829 830 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 831 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 832 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 833 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 834 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 835 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 836 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 837 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 838 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 839 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 840 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 841 do {\ 842 HWIO_INTLOCK(); \ 843 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 844 HWIO_INTFREE();\ 845 } while (0) 846 847 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 848 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 849 850 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 851 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 852 853 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 854 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 855 856 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 857 858 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 859 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 860 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 861 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 862 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 863 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 864 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 865 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 866 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 867 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 868 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 869 do {\ 870 HWIO_INTLOCK(); \ 871 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 872 HWIO_INTFREE();\ 873 } while (0) 874 875 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 876 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 877 878 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 879 880 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 881 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 882 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 883 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 884 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 885 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 886 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 887 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 888 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 889 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 890 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 891 do {\ 892 HWIO_INTLOCK(); \ 893 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 894 HWIO_INTFREE();\ 895 } while (0) 896 897 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 898 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 899 900 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 901 902 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 903 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 904 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 905 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 906 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 907 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 908 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 909 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 910 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 911 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 912 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 913 do {\ 914 HWIO_INTLOCK(); \ 915 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 916 HWIO_INTFREE();\ 917 } while (0) 918 919 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 920 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 921 922 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 923 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 924 925 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 926 927 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 928 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 929 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 930 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 931 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 932 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 933 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 934 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 935 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 936 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 937 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 938 do {\ 939 HWIO_INTLOCK(); \ 940 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 941 HWIO_INTFREE();\ 942 } while (0) 943 944 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 945 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 946 947 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 948 949 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 950 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 951 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 952 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 953 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 954 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 955 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 956 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 957 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 958 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 959 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 960 do {\ 961 HWIO_INTLOCK(); \ 962 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 963 HWIO_INTFREE();\ 964 } while (0) 965 966 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 967 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 968 969 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 970 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 971 972 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 973 974 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 975 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 976 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 977 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 978 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 979 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 980 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 981 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 982 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 983 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 984 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 985 do {\ 986 HWIO_INTLOCK(); \ 987 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 988 HWIO_INTFREE();\ 989 } while (0) 990 991 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 992 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 993 994 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 995 996 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 997 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 998 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 999 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1000 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1001 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1002 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1003 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1004 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1005 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1006 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1007 do {\ 1008 HWIO_INTLOCK(); \ 1009 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1010 HWIO_INTFREE();\ 1011 } while (0) 1012 1013 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1014 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1015 1016 //// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// 1017 1018 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1019 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1020 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK 0xffffffff 1021 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT 0 1022 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ 1023 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) 1024 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ 1025 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) 1026 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ 1027 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) 1028 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 1029 do {\ 1030 HWIO_INTLOCK(); \ 1031 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ 1032 HWIO_INTFREE();\ 1033 } while (0) 1034 1035 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1036 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1037 1038 //// Register REO_R0_RXDMA2REO1_RING_BASE_MSB //// 1039 1040 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1041 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1042 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK 0x00ffffff 1043 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT 0 1044 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ 1045 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) 1046 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ 1047 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) 1048 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ 1049 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) 1050 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 1051 do {\ 1052 HWIO_INTLOCK(); \ 1053 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ 1054 HWIO_INTFREE();\ 1055 } while (0) 1056 1057 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1058 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1059 1060 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1061 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1062 1063 //// Register REO_R0_RXDMA2REO1_RING_ID //// 1064 1065 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) 1066 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) 1067 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x000000ff 1068 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 1069 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ 1070 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) 1071 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ 1072 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) 1073 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ 1074 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) 1075 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ 1076 do {\ 1077 HWIO_INTLOCK(); \ 1078 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ 1079 HWIO_INTFREE();\ 1080 } while (0) 1081 1082 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1083 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 1084 1085 //// Register REO_R0_RXDMA2REO1_RING_STATUS //// 1086 1087 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x) (x+0x00000098) 1088 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x) (x+0x00000098) 1089 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK 0xffffffff 1090 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT 0 1091 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ 1092 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) 1093 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ 1094 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) 1095 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ 1096 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) 1097 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ 1098 do {\ 1099 HWIO_INTLOCK(); \ 1100 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ 1101 HWIO_INTFREE();\ 1102 } while (0) 1103 1104 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1105 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1106 1107 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1108 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1109 1110 //// Register REO_R0_RXDMA2REO1_RING_MISC //// 1111 1112 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x) (x+0x0000009c) 1113 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x) (x+0x0000009c) 1114 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK 0x0000003f 1115 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT 0 1116 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ 1117 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) 1118 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ 1119 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) 1120 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ 1121 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) 1122 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ 1123 do {\ 1124 HWIO_INTLOCK(); \ 1125 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ 1126 HWIO_INTFREE();\ 1127 } while (0) 1128 1129 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1130 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1131 1132 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1133 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1134 1135 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1136 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1137 1138 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1139 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 1140 1141 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1142 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1143 1144 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1145 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1146 1147 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB //// 1148 1149 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1150 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1151 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1152 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT 0 1153 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ 1154 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) 1155 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 1156 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 1157 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 1158 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 1159 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1160 do {\ 1161 HWIO_INTLOCK(); \ 1162 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ 1163 HWIO_INTFREE();\ 1164 } while (0) 1165 1166 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1167 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1168 1169 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB //// 1170 1171 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1172 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1173 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1174 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT 0 1175 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ 1176 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) 1177 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 1178 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 1179 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 1180 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 1181 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1182 do {\ 1183 HWIO_INTLOCK(); \ 1184 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ 1185 HWIO_INTFREE();\ 1186 } while (0) 1187 1188 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1189 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1190 1191 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 1192 1193 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1194 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1195 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1196 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1197 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1198 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1199 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1200 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1201 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1202 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1203 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1204 do {\ 1205 HWIO_INTLOCK(); \ 1206 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1207 HWIO_INTFREE();\ 1208 } while (0) 1209 1210 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1211 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1212 1213 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1214 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1215 1216 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1217 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1218 1219 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 1220 1221 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1222 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1223 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1224 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1225 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1226 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1227 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1228 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1229 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1230 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1231 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1232 do {\ 1233 HWIO_INTLOCK(); \ 1234 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1235 HWIO_INTFREE();\ 1236 } while (0) 1237 1238 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1239 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1240 1241 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS //// 1242 1243 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1244 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1245 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1246 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 1247 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 1248 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) 1249 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1250 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1251 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1252 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1253 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1254 do {\ 1255 HWIO_INTLOCK(); \ 1256 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1257 HWIO_INTFREE();\ 1258 } while (0) 1259 1260 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1261 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1262 1263 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1264 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1265 1266 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1267 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1268 1269 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER //// 1270 1271 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1272 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1273 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1274 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1275 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1276 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1277 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1278 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1279 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1280 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1281 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1282 do {\ 1283 HWIO_INTLOCK(); \ 1284 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1285 HWIO_INTFREE();\ 1286 } while (0) 1287 1288 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1289 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1290 1291 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// 1292 1293 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1294 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1295 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1296 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1297 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1298 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1299 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1300 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1301 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1302 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1303 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1304 do {\ 1305 HWIO_INTLOCK(); \ 1306 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1307 HWIO_INTFREE();\ 1308 } while (0) 1309 1310 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1311 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1312 1313 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS //// 1314 1315 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1316 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1317 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1318 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1319 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1320 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1321 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1322 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1323 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1324 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1325 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1326 do {\ 1327 HWIO_INTLOCK(); \ 1328 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1329 HWIO_INTFREE();\ 1330 } while (0) 1331 1332 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1333 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1334 1335 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1336 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1337 1338 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB //// 1339 1340 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1341 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1342 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1343 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT 0 1344 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ 1345 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) 1346 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1347 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1348 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1349 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 1350 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1351 do {\ 1352 HWIO_INTLOCK(); \ 1353 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 1354 HWIO_INTFREE();\ 1355 } while (0) 1356 1357 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1358 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1359 1360 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB //// 1361 1362 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1363 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1364 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1365 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT 0 1366 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ 1367 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) 1368 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1369 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1370 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1371 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 1372 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1373 do {\ 1374 HWIO_INTLOCK(); \ 1375 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 1376 HWIO_INTFREE();\ 1377 } while (0) 1378 1379 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1380 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1381 1382 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1383 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1384 1385 //// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA //// 1386 1387 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1388 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1389 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK 0xffffffff 1390 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT 0 1391 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ 1392 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) 1393 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ 1394 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) 1395 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ 1396 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) 1397 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1398 do {\ 1399 HWIO_INTLOCK(); \ 1400 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ 1401 HWIO_INTFREE();\ 1402 } while (0) 1403 1404 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1405 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 1406 1407 //// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET //// 1408 1409 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1410 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1411 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1412 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 1413 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 1414 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) 1415 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1416 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1417 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1418 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1419 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1420 do {\ 1421 HWIO_INTLOCK(); \ 1422 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1423 HWIO_INTFREE();\ 1424 } while (0) 1425 1426 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1427 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1428 1429 //// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// 1430 1431 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1432 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1433 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK 0xffffffff 1434 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT 0 1435 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ 1436 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) 1437 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ 1438 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) 1439 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ 1440 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) 1441 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ 1442 do {\ 1443 HWIO_INTLOCK(); \ 1444 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ 1445 HWIO_INTFREE();\ 1446 } while (0) 1447 1448 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1449 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1450 1451 //// Register REO_R0_RXDMA2REO2_RING_BASE_MSB //// 1452 1453 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1454 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1455 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK 0x00ffffff 1456 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT 0 1457 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ 1458 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) 1459 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ 1460 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) 1461 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ 1462 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) 1463 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ 1464 do {\ 1465 HWIO_INTLOCK(); \ 1466 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ 1467 HWIO_INTFREE();\ 1468 } while (0) 1469 1470 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1471 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1472 1473 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1474 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1475 1476 //// Register REO_R0_RXDMA2REO2_RING_ID //// 1477 1478 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) 1479 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) 1480 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x000000ff 1481 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 1482 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ 1483 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) 1484 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ 1485 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) 1486 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ 1487 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) 1488 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ 1489 do {\ 1490 HWIO_INTLOCK(); \ 1491 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ 1492 HWIO_INTFREE();\ 1493 } while (0) 1494 1495 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1496 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 1497 1498 //// Register REO_R0_RXDMA2REO2_RING_STATUS //// 1499 1500 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x) (x+0x000000f0) 1501 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x) (x+0x000000f0) 1502 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK 0xffffffff 1503 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT 0 1504 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ 1505 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) 1506 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ 1507 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) 1508 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ 1509 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) 1510 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ 1511 do {\ 1512 HWIO_INTLOCK(); \ 1513 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ 1514 HWIO_INTFREE();\ 1515 } while (0) 1516 1517 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1518 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1519 1520 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1521 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1522 1523 //// Register REO_R0_RXDMA2REO2_RING_MISC //// 1524 1525 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x) (x+0x000000f4) 1526 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x) (x+0x000000f4) 1527 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK 0x0000003f 1528 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT 0 1529 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ 1530 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) 1531 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ 1532 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) 1533 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ 1534 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) 1535 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ 1536 do {\ 1537 HWIO_INTLOCK(); \ 1538 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ 1539 HWIO_INTFREE();\ 1540 } while (0) 1541 1542 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1543 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1544 1545 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1546 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1547 1548 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1549 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1550 1551 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1552 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT 0x2 1553 1554 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1555 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1556 1557 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1558 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1559 1560 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB //// 1561 1562 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1563 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1564 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1565 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT 0 1566 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ 1567 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) 1568 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ 1569 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) 1570 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ 1571 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) 1572 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1573 do {\ 1574 HWIO_INTLOCK(); \ 1575 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ 1576 HWIO_INTFREE();\ 1577 } while (0) 1578 1579 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1580 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1581 1582 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB //// 1583 1584 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1585 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1586 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1587 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT 0 1588 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ 1589 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) 1590 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ 1591 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) 1592 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ 1593 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) 1594 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1595 do {\ 1596 HWIO_INTLOCK(); \ 1597 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ 1598 HWIO_INTFREE();\ 1599 } while (0) 1600 1601 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1602 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1603 1604 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 //// 1605 1606 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1607 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1608 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1609 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1610 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1611 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1612 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1613 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1614 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1615 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1616 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1617 do {\ 1618 HWIO_INTLOCK(); \ 1619 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1620 HWIO_INTFREE();\ 1621 } while (0) 1622 1623 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1624 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1625 1626 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1627 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1628 1629 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1630 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1631 1632 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 //// 1633 1634 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1635 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1636 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1637 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1638 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1639 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1640 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1641 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1642 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1643 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1644 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1645 do {\ 1646 HWIO_INTLOCK(); \ 1647 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1648 HWIO_INTFREE();\ 1649 } while (0) 1650 1651 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1652 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1653 1654 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS //// 1655 1656 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1657 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1658 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1659 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT 0 1660 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ 1661 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) 1662 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1663 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1664 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1665 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1666 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1667 do {\ 1668 HWIO_INTLOCK(); \ 1669 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1670 HWIO_INTFREE();\ 1671 } while (0) 1672 1673 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1674 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1675 1676 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1677 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1678 1679 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1680 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1681 1682 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER //// 1683 1684 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1685 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1686 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1687 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1688 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1689 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1690 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1691 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1692 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1693 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1694 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1695 do {\ 1696 HWIO_INTLOCK(); \ 1697 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1698 HWIO_INTFREE();\ 1699 } while (0) 1700 1701 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1702 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1703 1704 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// 1705 1706 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1707 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1708 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1709 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1710 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1711 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1712 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1713 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1714 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1715 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1716 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1717 do {\ 1718 HWIO_INTLOCK(); \ 1719 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1720 HWIO_INTFREE();\ 1721 } while (0) 1722 1723 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1724 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1725 1726 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS //// 1727 1728 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1729 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1730 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1731 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1732 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1733 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1734 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1735 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1736 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1737 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1738 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1739 do {\ 1740 HWIO_INTLOCK(); \ 1741 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1742 HWIO_INTFREE();\ 1743 } while (0) 1744 1745 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1746 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1747 1748 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1749 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1750 1751 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB //// 1752 1753 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1754 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1755 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1756 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT 0 1757 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ 1758 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) 1759 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1760 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1761 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1762 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) 1763 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1764 do {\ 1765 HWIO_INTLOCK(); \ 1766 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ 1767 HWIO_INTFREE();\ 1768 } while (0) 1769 1770 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1771 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1772 1773 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB //// 1774 1775 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1776 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1777 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1778 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT 0 1779 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ 1780 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) 1781 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1782 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1783 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1784 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) 1785 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1786 do {\ 1787 HWIO_INTLOCK(); \ 1788 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ 1789 HWIO_INTFREE();\ 1790 } while (0) 1791 1792 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1793 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1794 1795 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1796 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1797 1798 //// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA //// 1799 1800 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1801 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1802 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK 0xffffffff 1803 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT 0 1804 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ 1805 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) 1806 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ 1807 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) 1808 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ 1809 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) 1810 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1811 do {\ 1812 HWIO_INTLOCK(); \ 1813 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ 1814 HWIO_INTFREE();\ 1815 } while (0) 1816 1817 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1818 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 1819 1820 //// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET //// 1821 1822 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1823 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1824 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1825 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 1826 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ 1827 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) 1828 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1829 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1830 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1831 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1832 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1833 do {\ 1834 HWIO_INTLOCK(); \ 1835 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1836 HWIO_INTFREE();\ 1837 } while (0) 1838 1839 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1840 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1841 1842 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1843 1844 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1845 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1846 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1847 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1848 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1849 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1850 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1851 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1852 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1853 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1854 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1855 do {\ 1856 HWIO_INTLOCK(); \ 1857 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1858 HWIO_INTFREE();\ 1859 } while (0) 1860 1861 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1862 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1863 1864 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1865 1866 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1867 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1868 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1869 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1870 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1871 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1872 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1873 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1874 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1875 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1876 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1877 do {\ 1878 HWIO_INTLOCK(); \ 1879 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1880 HWIO_INTFREE();\ 1881 } while (0) 1882 1883 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1884 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1885 1886 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1887 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1888 1889 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1890 1891 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) 1892 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) 1893 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1894 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1895 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1896 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1897 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1898 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1899 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1900 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1901 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1902 do {\ 1903 HWIO_INTLOCK(); \ 1904 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1905 HWIO_INTFREE();\ 1906 } while (0) 1907 1908 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1909 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1910 1911 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1912 1913 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000148) 1914 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000148) 1915 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1916 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1917 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1918 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1919 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1920 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1921 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1922 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1923 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1924 do {\ 1925 HWIO_INTLOCK(); \ 1926 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1927 HWIO_INTFREE();\ 1928 } while (0) 1929 1930 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1931 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1932 1933 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1934 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1935 1936 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1937 1938 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000014c) 1939 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000014c) 1940 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x0000003f 1941 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1942 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1943 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1944 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1945 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1946 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1947 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1948 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1949 do {\ 1950 HWIO_INTLOCK(); \ 1951 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 1952 HWIO_INTFREE();\ 1953 } while (0) 1954 1955 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1956 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1957 1958 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1959 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1960 1961 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1962 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1963 1964 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1965 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 1966 1967 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1968 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1969 1970 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1971 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1972 1973 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 1974 1975 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 1976 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 1977 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 1978 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 1979 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 1980 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 1981 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 1982 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 1983 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 1984 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 1985 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1986 do {\ 1987 HWIO_INTLOCK(); \ 1988 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 1989 HWIO_INTFREE();\ 1990 } while (0) 1991 1992 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1993 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1994 1995 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 1996 1997 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 1998 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 1999 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 2000 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 2001 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 2002 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 2003 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 2004 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 2005 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 2006 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 2007 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2008 do {\ 2009 HWIO_INTLOCK(); \ 2010 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 2011 HWIO_INTFREE();\ 2012 } while (0) 2013 2014 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2015 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2016 2017 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 2018 2019 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2020 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2021 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2022 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2023 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2024 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2025 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2026 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2027 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2028 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2029 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2030 do {\ 2031 HWIO_INTLOCK(); \ 2032 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2033 HWIO_INTFREE();\ 2034 } while (0) 2035 2036 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2037 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2038 2039 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2040 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2041 2042 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2043 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2044 2045 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 2046 2047 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2048 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2049 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2050 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2051 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2052 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2053 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2054 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2055 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2056 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2057 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2058 do {\ 2059 HWIO_INTLOCK(); \ 2060 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2061 HWIO_INTFREE();\ 2062 } while (0) 2063 2064 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2065 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2066 2067 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 2068 2069 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2070 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2071 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2072 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 2073 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 2074 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 2075 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2076 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2077 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2078 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2079 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2080 do {\ 2081 HWIO_INTLOCK(); \ 2082 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 2083 HWIO_INTFREE();\ 2084 } while (0) 2085 2086 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2087 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2088 2089 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2090 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2091 2092 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2093 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2094 2095 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 2096 2097 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2098 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2099 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2100 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2101 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2102 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2103 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2104 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2105 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2106 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2107 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2108 do {\ 2109 HWIO_INTLOCK(); \ 2110 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2111 HWIO_INTFREE();\ 2112 } while (0) 2113 2114 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2115 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2116 2117 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 2118 2119 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2120 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2121 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2122 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2123 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2124 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2125 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2126 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2127 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2128 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2129 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2130 do {\ 2131 HWIO_INTLOCK(); \ 2132 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2133 HWIO_INTFREE();\ 2134 } while (0) 2135 2136 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2137 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2138 2139 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 2140 2141 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2142 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2143 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2144 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2145 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2146 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2147 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2148 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2149 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2150 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2151 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2152 do {\ 2153 HWIO_INTLOCK(); \ 2154 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2155 HWIO_INTFREE();\ 2156 } while (0) 2157 2158 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2159 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2160 2161 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2162 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2163 2164 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 2165 2166 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2167 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2168 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2169 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 2170 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 2171 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 2172 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2173 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2174 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2175 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2176 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2177 do {\ 2178 HWIO_INTLOCK(); \ 2179 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 2180 HWIO_INTFREE();\ 2181 } while (0) 2182 2183 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2184 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2185 2186 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 2187 2188 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2189 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2190 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 2191 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 2192 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 2193 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 2194 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 2195 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 2196 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 2197 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 2198 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2199 do {\ 2200 HWIO_INTLOCK(); \ 2201 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 2202 HWIO_INTFREE();\ 2203 } while (0) 2204 2205 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2206 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2207 2208 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 2209 2210 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2211 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2212 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 2213 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 2214 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 2215 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 2216 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 2217 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 2218 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 2219 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 2220 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2221 do {\ 2222 HWIO_INTLOCK(); \ 2223 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 2224 HWIO_INTFREE();\ 2225 } while (0) 2226 2227 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2228 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2229 2230 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2231 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2232 2233 //// Register REO_R0_REO_CMD_RING_ID //// 2234 2235 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) 2236 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) 2237 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 2238 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 2239 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 2240 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 2241 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 2242 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 2243 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 2244 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 2245 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 2246 do {\ 2247 HWIO_INTLOCK(); \ 2248 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 2249 HWIO_INTFREE();\ 2250 } while (0) 2251 2252 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2253 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2254 2255 //// Register REO_R0_REO_CMD_RING_STATUS //// 2256 2257 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000001a0) 2258 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000001a0) 2259 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 2260 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 2261 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 2262 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 2263 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 2264 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 2265 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 2266 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 2267 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 2268 do {\ 2269 HWIO_INTLOCK(); \ 2270 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 2271 HWIO_INTFREE();\ 2272 } while (0) 2273 2274 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2275 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2276 2277 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2278 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2279 2280 //// Register REO_R0_REO_CMD_RING_MISC //// 2281 2282 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000001a4) 2283 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000001a4) 2284 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x0000003f 2285 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 2286 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 2287 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 2288 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 2289 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 2290 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 2291 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 2292 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 2293 do {\ 2294 HWIO_INTLOCK(); \ 2295 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 2296 HWIO_INTFREE();\ 2297 } while (0) 2298 2299 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2300 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2301 2302 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2303 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2304 2305 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2306 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2307 2308 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2309 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2310 2311 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2312 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2313 2314 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2315 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2316 2317 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 2318 2319 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2320 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2321 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2322 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 2323 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 2324 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 2325 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2326 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2327 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2328 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2329 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2330 do {\ 2331 HWIO_INTLOCK(); \ 2332 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2333 HWIO_INTFREE();\ 2334 } while (0) 2335 2336 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2337 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2338 2339 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 2340 2341 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2342 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2343 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2344 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 2345 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 2346 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 2347 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2348 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2349 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2350 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2351 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2352 do {\ 2353 HWIO_INTLOCK(); \ 2354 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2355 HWIO_INTFREE();\ 2356 } while (0) 2357 2358 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2359 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2360 2361 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2362 2363 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2364 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2365 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2366 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2367 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2368 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2369 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2370 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2371 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2372 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2373 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2374 do {\ 2375 HWIO_INTLOCK(); \ 2376 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2377 HWIO_INTFREE();\ 2378 } while (0) 2379 2380 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2381 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2382 2383 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2384 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2385 2386 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2387 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2388 2389 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2390 2391 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2392 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2393 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2394 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2395 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2396 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2397 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2398 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2399 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2400 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2401 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2402 do {\ 2403 HWIO_INTLOCK(); \ 2404 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2405 HWIO_INTFREE();\ 2406 } while (0) 2407 2408 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2409 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2410 2411 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 2412 2413 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2414 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2415 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2416 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2417 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2418 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2419 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2420 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2421 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2422 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2423 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2424 do {\ 2425 HWIO_INTLOCK(); \ 2426 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2427 HWIO_INTFREE();\ 2428 } while (0) 2429 2430 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2431 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2432 2433 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2434 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2435 2436 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2437 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2438 2439 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2440 2441 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2442 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2443 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2444 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2445 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2446 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2447 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2448 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2449 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2450 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2451 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2452 do {\ 2453 HWIO_INTLOCK(); \ 2454 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2455 HWIO_INTFREE();\ 2456 } while (0) 2457 2458 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2459 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2460 2461 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2462 2463 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2464 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2465 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2466 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2467 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2468 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2469 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2470 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2471 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2472 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2473 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2474 do {\ 2475 HWIO_INTLOCK(); \ 2476 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2477 HWIO_INTFREE();\ 2478 } while (0) 2479 2480 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2481 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2482 2483 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2484 2485 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2486 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2487 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2488 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2489 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2490 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2491 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2492 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2493 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2494 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2495 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2496 do {\ 2497 HWIO_INTLOCK(); \ 2498 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2499 HWIO_INTFREE();\ 2500 } while (0) 2501 2502 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2503 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2504 2505 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2506 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2507 2508 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 2509 2510 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2511 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2512 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2513 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 2514 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2515 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 2516 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2517 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2518 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2519 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2520 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2521 do {\ 2522 HWIO_INTLOCK(); \ 2523 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2524 HWIO_INTFREE();\ 2525 } while (0) 2526 2527 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2528 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2529 2530 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 2531 2532 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2533 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2534 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2535 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 2536 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2537 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 2538 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2539 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2540 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2541 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2542 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2543 do {\ 2544 HWIO_INTLOCK(); \ 2545 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2546 HWIO_INTFREE();\ 2547 } while (0) 2548 2549 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2550 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2551 2552 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2553 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2554 2555 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 2556 2557 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2558 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2559 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2560 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 2561 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 2562 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 2563 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 2564 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 2565 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 2566 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 2567 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2568 do {\ 2569 HWIO_INTLOCK(); \ 2570 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 2571 HWIO_INTFREE();\ 2572 } while (0) 2573 2574 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2575 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2576 2577 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 2578 2579 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2580 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2581 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2582 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2583 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2584 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2585 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2586 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2587 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2588 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2589 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2590 do {\ 2591 HWIO_INTLOCK(); \ 2592 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2593 HWIO_INTFREE();\ 2594 } while (0) 2595 2596 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2597 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2598 2599 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 2600 2601 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2602 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2603 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 2604 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 2605 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 2606 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 2607 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 2608 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 2609 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 2610 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 2611 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 2612 do {\ 2613 HWIO_INTLOCK(); \ 2614 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 2615 HWIO_INTFREE();\ 2616 } while (0) 2617 2618 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2619 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2620 2621 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 2622 2623 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2624 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2625 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 2626 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 2627 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 2628 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 2629 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 2630 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 2631 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 2632 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 2633 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 2634 do {\ 2635 HWIO_INTLOCK(); \ 2636 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 2637 HWIO_INTFREE();\ 2638 } while (0) 2639 2640 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2641 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2642 2643 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2644 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2645 2646 //// Register REO_R0_SW2REO_RING_ID //// 2647 2648 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) 2649 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) 2650 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 2651 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 2652 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 2653 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 2654 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 2655 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 2656 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 2657 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 2658 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 2659 do {\ 2660 HWIO_INTLOCK(); \ 2661 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 2662 HWIO_INTFREE();\ 2663 } while (0) 2664 2665 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2666 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 2667 2668 //// Register REO_R0_SW2REO_RING_STATUS //// 2669 2670 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x000001f8) 2671 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x000001f8) 2672 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 2673 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 2674 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 2675 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 2676 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 2677 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 2678 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 2679 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 2680 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 2681 do {\ 2682 HWIO_INTLOCK(); \ 2683 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 2684 HWIO_INTFREE();\ 2685 } while (0) 2686 2687 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2688 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2689 2690 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2691 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2692 2693 //// Register REO_R0_SW2REO_RING_MISC //// 2694 2695 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x000001fc) 2696 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x000001fc) 2697 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x0000003f 2698 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 2699 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 2700 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 2701 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 2702 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 2703 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 2704 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 2705 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 2706 do {\ 2707 HWIO_INTLOCK(); \ 2708 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 2709 HWIO_INTFREE();\ 2710 } while (0) 2711 2712 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2713 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2714 2715 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2716 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2717 2718 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2719 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2720 2721 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2722 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2723 2724 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2725 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2726 2727 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2728 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2729 2730 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2731 2732 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) 2733 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) 2734 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2735 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2736 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2737 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2738 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2739 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2740 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2741 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2742 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2743 do {\ 2744 HWIO_INTLOCK(); \ 2745 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2746 HWIO_INTFREE();\ 2747 } while (0) 2748 2749 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2750 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2751 2752 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2753 2754 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) 2755 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) 2756 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2757 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2758 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2759 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2760 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2761 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2762 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2763 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2764 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2765 do {\ 2766 HWIO_INTLOCK(); \ 2767 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2768 HWIO_INTFREE();\ 2769 } while (0) 2770 2771 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2772 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2773 2774 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2775 2776 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) 2777 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) 2778 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2779 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2780 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2781 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2782 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2783 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2784 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2785 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2786 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2787 do {\ 2788 HWIO_INTLOCK(); \ 2789 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2790 HWIO_INTFREE();\ 2791 } while (0) 2792 2793 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2794 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2795 2796 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2797 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2798 2799 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2800 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2801 2802 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2803 2804 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) 2805 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) 2806 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2807 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2808 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2809 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2810 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2811 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2812 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2813 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2814 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2815 do {\ 2816 HWIO_INTLOCK(); \ 2817 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2818 HWIO_INTFREE();\ 2819 } while (0) 2820 2821 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2822 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2823 2824 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2825 2826 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) 2827 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) 2828 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2829 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2830 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2831 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2832 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2833 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2834 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2835 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2836 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2837 do {\ 2838 HWIO_INTLOCK(); \ 2839 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2840 HWIO_INTFREE();\ 2841 } while (0) 2842 2843 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2844 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2845 2846 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2847 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2848 2849 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2850 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2851 2852 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2853 2854 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) 2855 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) 2856 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2857 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2858 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2859 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2860 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2861 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2862 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2863 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2864 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2865 do {\ 2866 HWIO_INTLOCK(); \ 2867 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2868 HWIO_INTFREE();\ 2869 } while (0) 2870 2871 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2872 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2873 2874 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2875 2876 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) 2877 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) 2878 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2879 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2880 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2881 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2882 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2883 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2884 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2885 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2886 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2887 do {\ 2888 HWIO_INTLOCK(); \ 2889 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2890 HWIO_INTFREE();\ 2891 } while (0) 2892 2893 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2894 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2895 2896 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2897 2898 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) 2899 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) 2900 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2901 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2902 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2903 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2904 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2905 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2906 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2907 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2908 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2909 do {\ 2910 HWIO_INTLOCK(); \ 2911 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2912 HWIO_INTFREE();\ 2913 } while (0) 2914 2915 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2916 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2917 2918 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2919 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2920 2921 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 2922 2923 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 2924 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 2925 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2926 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 2927 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 2928 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 2929 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 2930 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 2931 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 2932 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 2933 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2934 do {\ 2935 HWIO_INTLOCK(); \ 2936 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 2937 HWIO_INTFREE();\ 2938 } while (0) 2939 2940 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2941 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2942 2943 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 2944 2945 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 2946 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 2947 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2948 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 2949 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 2950 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 2951 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 2952 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 2953 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 2954 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 2955 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2956 do {\ 2957 HWIO_INTLOCK(); \ 2958 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 2959 HWIO_INTFREE();\ 2960 } while (0) 2961 2962 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2963 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2964 2965 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2966 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2967 2968 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 2969 2970 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 2971 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 2972 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 2973 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 2974 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 2975 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 2976 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 2977 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 2978 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 2979 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 2980 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 2981 do {\ 2982 HWIO_INTLOCK(); \ 2983 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 2984 HWIO_INTFREE();\ 2985 } while (0) 2986 2987 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2988 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 2989 2990 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 2991 2992 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 2993 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 2994 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2995 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 2996 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 2997 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 2998 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2999 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3000 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3001 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3002 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3003 do {\ 3004 HWIO_INTLOCK(); \ 3005 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 3006 HWIO_INTFREE();\ 3007 } while (0) 3008 3009 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3010 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3011 3012 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 3013 3014 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3015 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3016 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 3017 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 3018 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 3019 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 3020 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 3021 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 3022 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 3023 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 3024 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 3025 do {\ 3026 HWIO_INTLOCK(); \ 3027 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 3028 HWIO_INTFREE();\ 3029 } while (0) 3030 3031 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3032 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3033 3034 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 3035 3036 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3037 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3038 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x00ffffff 3039 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 3040 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 3041 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 3042 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 3043 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 3044 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 3045 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 3046 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 3047 do {\ 3048 HWIO_INTLOCK(); \ 3049 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 3050 HWIO_INTFREE();\ 3051 } while (0) 3052 3053 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3054 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3055 3056 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3057 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3058 3059 //// Register REO_R0_REO2SW1_RING_ID //// 3060 3061 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x0000024c) 3062 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x0000024c) 3063 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 3064 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 3065 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 3066 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 3067 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 3068 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 3069 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 3070 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 3071 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 3072 do {\ 3073 HWIO_INTLOCK(); \ 3074 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 3075 HWIO_INTFREE();\ 3076 } while (0) 3077 3078 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 3079 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 3080 3081 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3082 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 3083 3084 //// Register REO_R0_REO2SW1_RING_STATUS //// 3085 3086 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x00000250) 3087 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x00000250) 3088 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 3089 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 3090 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 3091 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 3092 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 3093 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 3094 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 3095 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 3096 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 3097 do {\ 3098 HWIO_INTLOCK(); \ 3099 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 3100 HWIO_INTFREE();\ 3101 } while (0) 3102 3103 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3104 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3105 3106 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3107 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3108 3109 //// Register REO_R0_REO2SW1_RING_MISC //// 3110 3111 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x00000254) 3112 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x00000254) 3113 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x0000003f 3114 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 3115 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 3116 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 3117 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 3118 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 3119 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 3120 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 3121 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 3122 do {\ 3123 HWIO_INTLOCK(); \ 3124 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 3125 HWIO_INTFREE();\ 3126 } while (0) 3127 3128 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3129 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3130 3131 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3132 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3133 3134 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3135 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3136 3137 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3138 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 3139 3140 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3141 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3142 3143 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3144 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3145 3146 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 3147 3148 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) 3149 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) 3150 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3151 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 3152 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 3153 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 3154 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 3155 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 3156 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 3157 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 3158 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3159 do {\ 3160 HWIO_INTLOCK(); \ 3161 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 3162 HWIO_INTFREE();\ 3163 } while (0) 3164 3165 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3166 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3167 3168 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 3169 3170 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) 3171 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) 3172 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3173 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 3174 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 3175 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 3176 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 3177 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 3178 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 3179 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 3180 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3181 do {\ 3182 HWIO_INTLOCK(); \ 3183 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 3184 HWIO_INTFREE();\ 3185 } while (0) 3186 3187 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3188 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3189 3190 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 3191 3192 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) 3193 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) 3194 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3195 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 3196 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 3197 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 3198 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3199 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3200 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3201 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3202 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3203 do {\ 3204 HWIO_INTLOCK(); \ 3205 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3206 HWIO_INTFREE();\ 3207 } while (0) 3208 3209 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3210 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3211 3212 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3213 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3214 3215 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3216 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3217 3218 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 3219 3220 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) 3221 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) 3222 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3223 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 3224 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 3225 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 3226 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3227 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3228 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3229 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3230 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3231 do {\ 3232 HWIO_INTLOCK(); \ 3233 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3234 HWIO_INTFREE();\ 3235 } while (0) 3236 3237 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3238 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3239 3240 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3241 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3242 3243 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3244 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3245 3246 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 3247 3248 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) 3249 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) 3250 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3251 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3252 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3253 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3254 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3255 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3256 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3257 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3258 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3259 do {\ 3260 HWIO_INTLOCK(); \ 3261 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3262 HWIO_INTFREE();\ 3263 } while (0) 3264 3265 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3266 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3267 3268 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3269 3270 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3271 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3272 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3273 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3274 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3275 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3276 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3277 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3278 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3279 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3280 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3281 do {\ 3282 HWIO_INTLOCK(); \ 3283 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3284 HWIO_INTFREE();\ 3285 } while (0) 3286 3287 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3288 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3289 3290 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3291 3292 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3293 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3294 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3295 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3296 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3297 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3298 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3299 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3300 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3301 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3302 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3303 do {\ 3304 HWIO_INTLOCK(); \ 3305 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3306 HWIO_INTFREE();\ 3307 } while (0) 3308 3309 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3310 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3311 3312 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3313 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3314 3315 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3316 3317 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3318 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3319 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3320 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3321 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3322 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3323 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3324 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3325 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3326 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3327 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3328 do {\ 3329 HWIO_INTLOCK(); \ 3330 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3331 HWIO_INTFREE();\ 3332 } while (0) 3333 3334 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3335 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3336 3337 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3338 3339 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3340 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3341 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3342 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3343 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3344 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3345 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3346 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3347 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3348 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3349 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3350 do {\ 3351 HWIO_INTLOCK(); \ 3352 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3353 HWIO_INTFREE();\ 3354 } while (0) 3355 3356 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3357 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3358 3359 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3360 3361 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3362 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3363 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3364 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3365 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3366 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3367 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3368 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3369 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3370 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3371 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3372 do {\ 3373 HWIO_INTLOCK(); \ 3374 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3375 HWIO_INTFREE();\ 3376 } while (0) 3377 3378 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3379 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3380 3381 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3382 3383 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3384 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3385 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x00ffffff 3386 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3387 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3388 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3389 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3390 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3391 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3392 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3393 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3394 do {\ 3395 HWIO_INTLOCK(); \ 3396 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3397 HWIO_INTFREE();\ 3398 } while (0) 3399 3400 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3401 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3402 3403 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3404 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3405 3406 //// Register REO_R0_REO2SW2_RING_ID //// 3407 3408 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x000002a4) 3409 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x000002a4) 3410 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3411 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3412 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3413 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3414 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3415 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3416 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3417 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3418 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3419 do {\ 3420 HWIO_INTLOCK(); \ 3421 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3422 HWIO_INTFREE();\ 3423 } while (0) 3424 3425 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3426 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3427 3428 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3429 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3430 3431 //// Register REO_R0_REO2SW2_RING_STATUS //// 3432 3433 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x000002a8) 3434 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x000002a8) 3435 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3436 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3437 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3438 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3439 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3440 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3441 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3442 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3443 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3444 do {\ 3445 HWIO_INTLOCK(); \ 3446 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3447 HWIO_INTFREE();\ 3448 } while (0) 3449 3450 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3451 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3452 3453 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3454 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3455 3456 //// Register REO_R0_REO2SW2_RING_MISC //// 3457 3458 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x000002ac) 3459 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x000002ac) 3460 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x0000003f 3461 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 3462 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 3463 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 3464 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 3465 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 3466 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 3467 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 3468 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 3469 do {\ 3470 HWIO_INTLOCK(); \ 3471 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 3472 HWIO_INTFREE();\ 3473 } while (0) 3474 3475 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3476 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3477 3478 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3479 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3480 3481 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3482 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3483 3484 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3485 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 3486 3487 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3488 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3489 3490 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3491 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3492 3493 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 3494 3495 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3496 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3497 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3498 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 3499 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 3500 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 3501 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 3502 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 3503 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 3504 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 3505 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3506 do {\ 3507 HWIO_INTLOCK(); \ 3508 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 3509 HWIO_INTFREE();\ 3510 } while (0) 3511 3512 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3513 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3514 3515 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 3516 3517 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3518 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3519 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3520 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 3521 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 3522 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 3523 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 3524 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 3525 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 3526 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 3527 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3528 do {\ 3529 HWIO_INTLOCK(); \ 3530 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 3531 HWIO_INTFREE();\ 3532 } while (0) 3533 3534 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3535 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3536 3537 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 3538 3539 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3540 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3541 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3542 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 3543 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 3544 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 3545 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3546 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3547 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3548 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3549 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3550 do {\ 3551 HWIO_INTLOCK(); \ 3552 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3553 HWIO_INTFREE();\ 3554 } while (0) 3555 3556 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3557 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3558 3559 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3560 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3561 3562 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3563 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3564 3565 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 3566 3567 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3568 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3569 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3570 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 3571 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 3572 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 3573 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3574 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3575 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3576 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3577 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3578 do {\ 3579 HWIO_INTLOCK(); \ 3580 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3581 HWIO_INTFREE();\ 3582 } while (0) 3583 3584 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3585 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3586 3587 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3588 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3589 3590 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3591 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3592 3593 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 3594 3595 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3596 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3597 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3598 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 3599 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3600 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 3601 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3602 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3603 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3604 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3605 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3606 do {\ 3607 HWIO_INTLOCK(); \ 3608 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3609 HWIO_INTFREE();\ 3610 } while (0) 3611 3612 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3613 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3614 3615 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 3616 3617 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3618 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3619 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3620 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 3621 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 3622 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 3623 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 3624 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 3625 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 3626 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 3627 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3628 do {\ 3629 HWIO_INTLOCK(); \ 3630 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 3631 HWIO_INTFREE();\ 3632 } while (0) 3633 3634 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3635 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3636 3637 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 3638 3639 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3640 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3641 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3642 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 3643 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 3644 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 3645 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 3646 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 3647 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 3648 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 3649 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3650 do {\ 3651 HWIO_INTLOCK(); \ 3652 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 3653 HWIO_INTFREE();\ 3654 } while (0) 3655 3656 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3657 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3658 3659 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3660 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3661 3662 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 3663 3664 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3665 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3666 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 3667 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 3668 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 3669 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 3670 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 3671 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 3672 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 3673 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 3674 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 3675 do {\ 3676 HWIO_INTLOCK(); \ 3677 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 3678 HWIO_INTFREE();\ 3679 } while (0) 3680 3681 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3682 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 3683 3684 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 3685 3686 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3687 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3688 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3689 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 3690 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 3691 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 3692 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3693 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3694 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3695 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3696 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3697 do {\ 3698 HWIO_INTLOCK(); \ 3699 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 3700 HWIO_INTFREE();\ 3701 } while (0) 3702 3703 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3704 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3705 3706 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 3707 3708 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3709 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3710 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 3711 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 3712 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 3713 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 3714 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 3715 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 3716 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 3717 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 3718 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 3719 do {\ 3720 HWIO_INTLOCK(); \ 3721 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 3722 HWIO_INTFREE();\ 3723 } while (0) 3724 3725 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3726 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3727 3728 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 3729 3730 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3731 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3732 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x00ffffff 3733 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 3734 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 3735 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 3736 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 3737 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 3738 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 3739 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 3740 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 3741 do {\ 3742 HWIO_INTLOCK(); \ 3743 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 3744 HWIO_INTFREE();\ 3745 } while (0) 3746 3747 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3748 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3749 3750 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3751 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3752 3753 //// Register REO_R0_REO2SW3_RING_ID //// 3754 3755 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002fc) 3756 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002fc) 3757 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 3758 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 3759 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 3760 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 3761 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 3762 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 3763 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 3764 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 3765 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 3766 do {\ 3767 HWIO_INTLOCK(); \ 3768 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 3769 HWIO_INTFREE();\ 3770 } while (0) 3771 3772 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 3773 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 3774 3775 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3776 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 3777 3778 //// Register REO_R0_REO2SW3_RING_STATUS //// 3779 3780 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x00000300) 3781 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x00000300) 3782 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 3783 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 3784 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 3785 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 3786 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 3787 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 3788 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 3789 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 3790 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 3791 do {\ 3792 HWIO_INTLOCK(); \ 3793 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 3794 HWIO_INTFREE();\ 3795 } while (0) 3796 3797 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3798 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3799 3800 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3801 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3802 3803 //// Register REO_R0_REO2SW3_RING_MISC //// 3804 3805 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x00000304) 3806 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x00000304) 3807 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x0000003f 3808 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 3809 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 3810 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 3811 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 3812 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 3813 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 3814 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 3815 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 3816 do {\ 3817 HWIO_INTLOCK(); \ 3818 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 3819 HWIO_INTFREE();\ 3820 } while (0) 3821 3822 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3823 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3824 3825 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3826 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3827 3828 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3829 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3830 3831 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3832 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 3833 3834 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3835 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3836 3837 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3838 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3839 3840 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 3841 3842 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 3843 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 3844 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 3845 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 3846 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 3847 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 3848 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 3849 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 3850 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 3851 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 3852 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3853 do {\ 3854 HWIO_INTLOCK(); \ 3855 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 3856 HWIO_INTFREE();\ 3857 } while (0) 3858 3859 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3860 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3861 3862 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 3863 3864 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 3865 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 3866 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 3867 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 3868 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 3869 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 3870 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 3871 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 3872 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 3873 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 3874 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3875 do {\ 3876 HWIO_INTLOCK(); \ 3877 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 3878 HWIO_INTFREE();\ 3879 } while (0) 3880 3881 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3882 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3883 3884 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 3885 3886 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 3887 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 3888 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3889 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 3890 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 3891 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 3892 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3893 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3894 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3895 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3896 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3897 do {\ 3898 HWIO_INTLOCK(); \ 3899 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 3900 HWIO_INTFREE();\ 3901 } while (0) 3902 3903 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3904 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3905 3906 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3907 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3908 3909 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3910 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3911 3912 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 3913 3914 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 3915 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 3916 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3917 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 3918 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 3919 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 3920 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3921 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3922 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3923 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3924 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3925 do {\ 3926 HWIO_INTLOCK(); \ 3927 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 3928 HWIO_INTFREE();\ 3929 } while (0) 3930 3931 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3932 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3933 3934 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3935 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3936 3937 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3938 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3939 3940 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 3941 3942 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 3943 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 3944 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3945 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 3946 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3947 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 3948 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3949 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3950 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3951 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3952 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3953 do {\ 3954 HWIO_INTLOCK(); \ 3955 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3956 HWIO_INTFREE();\ 3957 } while (0) 3958 3959 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3960 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3961 3962 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 3963 3964 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 3965 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 3966 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3967 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 3968 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 3969 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 3970 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 3971 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 3972 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 3973 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 3974 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3975 do {\ 3976 HWIO_INTLOCK(); \ 3977 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 3978 HWIO_INTFREE();\ 3979 } while (0) 3980 3981 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3982 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3983 3984 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 3985 3986 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 3987 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 3988 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3989 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 3990 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 3991 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 3992 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 3993 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 3994 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 3995 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 3996 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3997 do {\ 3998 HWIO_INTLOCK(); \ 3999 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 4000 HWIO_INTFREE();\ 4001 } while (0) 4002 4003 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4004 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4005 4006 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4007 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4008 4009 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 4010 4011 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4012 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4013 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 4014 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 4015 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 4016 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 4017 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 4018 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 4019 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 4020 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 4021 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 4022 do {\ 4023 HWIO_INTLOCK(); \ 4024 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 4025 HWIO_INTFREE();\ 4026 } while (0) 4027 4028 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4029 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 4030 4031 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 4032 4033 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4034 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4035 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4036 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 4037 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 4038 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 4039 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4040 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4041 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4042 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4043 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4044 do {\ 4045 HWIO_INTLOCK(); \ 4046 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 4047 HWIO_INTFREE();\ 4048 } while (0) 4049 4050 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4051 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4052 4053 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 4054 4055 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x0000034c) 4056 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x0000034c) 4057 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 4058 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 4059 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 4060 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 4061 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 4062 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 4063 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 4064 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 4065 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 4066 do {\ 4067 HWIO_INTLOCK(); \ 4068 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 4069 HWIO_INTFREE();\ 4070 } while (0) 4071 4072 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4073 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4074 4075 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 4076 4077 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x00000350) 4078 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x00000350) 4079 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x00ffffff 4080 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 4081 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 4082 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 4083 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 4084 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 4085 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 4086 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 4087 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 4088 do {\ 4089 HWIO_INTLOCK(); \ 4090 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 4091 HWIO_INTFREE();\ 4092 } while (0) 4093 4094 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4095 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4096 4097 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4098 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4099 4100 //// Register REO_R0_REO2SW4_RING_ID //// 4101 4102 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x00000354) 4103 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x00000354) 4104 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 4105 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 4106 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 4107 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 4108 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 4109 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 4110 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 4111 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 4112 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 4113 do {\ 4114 HWIO_INTLOCK(); \ 4115 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 4116 HWIO_INTFREE();\ 4117 } while (0) 4118 4119 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 4120 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 4121 4122 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4123 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 4124 4125 //// Register REO_R0_REO2SW4_RING_STATUS //// 4126 4127 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000358) 4128 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000358) 4129 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 4130 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 4131 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 4132 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 4133 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 4134 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 4135 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 4136 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 4137 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 4138 do {\ 4139 HWIO_INTLOCK(); \ 4140 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 4141 HWIO_INTFREE();\ 4142 } while (0) 4143 4144 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4145 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4146 4147 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4148 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4149 4150 //// Register REO_R0_REO2SW4_RING_MISC //// 4151 4152 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x0000035c) 4153 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x0000035c) 4154 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x0000003f 4155 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 4156 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 4157 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 4158 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 4159 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 4160 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 4161 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 4162 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 4163 do {\ 4164 HWIO_INTLOCK(); \ 4165 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 4166 HWIO_INTFREE();\ 4167 } while (0) 4168 4169 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4170 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4171 4172 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4173 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4174 4175 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4176 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4177 4178 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4179 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 4180 4181 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4182 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4183 4184 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4185 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4186 4187 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 4188 4189 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) 4190 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) 4191 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 4192 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 4193 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 4194 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 4195 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 4196 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 4197 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 4198 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4199 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4200 do {\ 4201 HWIO_INTLOCK(); \ 4202 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4203 HWIO_INTFREE();\ 4204 } while (0) 4205 4206 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4207 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4208 4209 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4210 4211 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) 4212 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) 4213 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4214 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4215 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4216 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4217 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4218 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4219 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4220 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4221 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4222 do {\ 4223 HWIO_INTLOCK(); \ 4224 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4225 HWIO_INTFREE();\ 4226 } while (0) 4227 4228 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4229 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4230 4231 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4232 4233 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) 4234 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) 4235 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4236 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4237 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4238 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4239 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4240 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4241 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4242 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4243 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4244 do {\ 4245 HWIO_INTLOCK(); \ 4246 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4247 HWIO_INTFREE();\ 4248 } while (0) 4249 4250 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4251 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4252 4253 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4254 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4255 4256 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4257 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4258 4259 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4260 4261 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) 4262 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) 4263 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4264 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4265 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4266 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4267 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4268 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4269 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4270 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4271 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4272 do {\ 4273 HWIO_INTLOCK(); \ 4274 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4275 HWIO_INTFREE();\ 4276 } while (0) 4277 4278 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4279 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4280 4281 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4282 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4283 4284 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4285 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4286 4287 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4288 4289 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) 4290 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) 4291 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4292 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4293 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4294 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4295 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4296 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4297 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4298 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4299 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4300 do {\ 4301 HWIO_INTLOCK(); \ 4302 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4303 HWIO_INTFREE();\ 4304 } while (0) 4305 4306 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4307 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4308 4309 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4310 4311 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) 4312 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) 4313 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4314 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4315 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4316 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4317 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4318 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4319 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4320 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4321 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4322 do {\ 4323 HWIO_INTLOCK(); \ 4324 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4325 HWIO_INTFREE();\ 4326 } while (0) 4327 4328 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4329 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4330 4331 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4332 4333 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) 4334 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) 4335 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4336 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4337 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4338 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4339 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4340 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4341 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4342 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4343 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4344 do {\ 4345 HWIO_INTLOCK(); \ 4346 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4347 HWIO_INTFREE();\ 4348 } while (0) 4349 4350 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4351 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4352 4353 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4354 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4355 4356 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4357 4358 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) 4359 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) 4360 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4361 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4362 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4363 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4364 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4365 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4366 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4367 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4368 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4369 do {\ 4370 HWIO_INTLOCK(); \ 4371 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4372 HWIO_INTFREE();\ 4373 } while (0) 4374 4375 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4376 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4377 4378 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4379 4380 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) 4381 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) 4382 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4383 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4384 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4385 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4386 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4387 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4388 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4389 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4390 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4391 do {\ 4392 HWIO_INTLOCK(); \ 4393 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4394 HWIO_INTFREE();\ 4395 } while (0) 4396 4397 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4398 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4399 4400 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4401 4402 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003a4) 4403 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003a4) 4404 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4405 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4406 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 4407 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 4408 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 4409 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 4410 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 4411 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 4412 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 4413 do {\ 4414 HWIO_INTLOCK(); \ 4415 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 4416 HWIO_INTFREE();\ 4417 } while (0) 4418 4419 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4420 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4421 4422 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 4423 4424 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x000003a8) 4425 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x000003a8) 4426 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x00ffffff 4427 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 4428 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 4429 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 4430 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 4431 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 4432 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 4433 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 4434 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 4435 do {\ 4436 HWIO_INTLOCK(); \ 4437 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 4438 HWIO_INTFREE();\ 4439 } while (0) 4440 4441 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4442 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4443 4444 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4445 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4446 4447 //// Register REO_R0_REO2TCL_RING_ID //// 4448 4449 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x000003ac) 4450 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x000003ac) 4451 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 4452 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 4453 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 4454 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 4455 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 4456 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 4457 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 4458 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 4459 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 4460 do {\ 4461 HWIO_INTLOCK(); \ 4462 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 4463 HWIO_INTFREE();\ 4464 } while (0) 4465 4466 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 4467 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 4468 4469 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4470 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 4471 4472 //// Register REO_R0_REO2TCL_RING_STATUS //// 4473 4474 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x000003b0) 4475 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x000003b0) 4476 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 4477 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 4478 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 4479 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 4480 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 4481 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 4482 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 4483 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 4484 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 4485 do {\ 4486 HWIO_INTLOCK(); \ 4487 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 4488 HWIO_INTFREE();\ 4489 } while (0) 4490 4491 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4492 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4493 4494 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4495 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4496 4497 //// Register REO_R0_REO2TCL_RING_MISC //// 4498 4499 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x000003b4) 4500 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x000003b4) 4501 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x0000003f 4502 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 4503 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 4504 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 4505 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 4506 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 4507 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 4508 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 4509 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 4510 do {\ 4511 HWIO_INTLOCK(); \ 4512 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 4513 HWIO_INTFREE();\ 4514 } while (0) 4515 4516 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4517 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4518 4519 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4520 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4521 4522 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4523 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4524 4525 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4526 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 4527 4528 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4529 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4530 4531 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4532 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4533 4534 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 4535 4536 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) 4537 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) 4538 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 4539 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 4540 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 4541 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 4542 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 4543 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 4544 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 4545 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 4546 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4547 do {\ 4548 HWIO_INTLOCK(); \ 4549 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 4550 HWIO_INTFREE();\ 4551 } while (0) 4552 4553 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4554 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4555 4556 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 4557 4558 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) 4559 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) 4560 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 4561 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 4562 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 4563 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 4564 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 4565 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 4566 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 4567 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 4568 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4569 do {\ 4570 HWIO_INTLOCK(); \ 4571 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 4572 HWIO_INTFREE();\ 4573 } while (0) 4574 4575 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4576 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4577 4578 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 4579 4580 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) 4581 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) 4582 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4583 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 4584 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 4585 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 4586 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4587 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4588 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4589 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4590 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4591 do {\ 4592 HWIO_INTLOCK(); \ 4593 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 4594 HWIO_INTFREE();\ 4595 } while (0) 4596 4597 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4598 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4599 4600 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4601 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4602 4603 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4604 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4605 4606 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 4607 4608 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) 4609 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) 4610 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4611 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 4612 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 4613 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 4614 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4615 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4616 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4617 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4618 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4619 do {\ 4620 HWIO_INTLOCK(); \ 4621 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 4622 HWIO_INTFREE();\ 4623 } while (0) 4624 4625 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4626 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4627 4628 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4629 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4630 4631 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4632 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4633 4634 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 4635 4636 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) 4637 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) 4638 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4639 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 4640 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4641 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 4642 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4643 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4644 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4645 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4646 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4647 do {\ 4648 HWIO_INTLOCK(); \ 4649 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4650 HWIO_INTFREE();\ 4651 } while (0) 4652 4653 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4654 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4655 4656 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 4657 4658 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) 4659 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) 4660 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4661 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 4662 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 4663 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 4664 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 4665 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 4666 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 4667 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 4668 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4669 do {\ 4670 HWIO_INTLOCK(); \ 4671 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 4672 HWIO_INTFREE();\ 4673 } while (0) 4674 4675 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4676 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4677 4678 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 4679 4680 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) 4681 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) 4682 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4683 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 4684 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 4685 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 4686 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 4687 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 4688 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 4689 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 4690 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4691 do {\ 4692 HWIO_INTLOCK(); \ 4693 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 4694 HWIO_INTFREE();\ 4695 } while (0) 4696 4697 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4698 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4699 4700 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4701 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4702 4703 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 4704 4705 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) 4706 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) 4707 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 4708 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 4709 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 4710 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 4711 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 4712 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 4713 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 4714 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 4715 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 4716 do {\ 4717 HWIO_INTLOCK(); \ 4718 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 4719 HWIO_INTFREE();\ 4720 } while (0) 4721 4722 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4723 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 4724 4725 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 4726 4727 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) 4728 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) 4729 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4730 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 4731 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 4732 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 4733 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4734 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4735 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4736 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4737 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4738 do {\ 4739 HWIO_INTLOCK(); \ 4740 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 4741 HWIO_INTFREE();\ 4742 } while (0) 4743 4744 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4745 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4746 4747 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 4748 4749 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4750 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4751 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 4752 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 4753 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 4754 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 4755 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 4756 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 4757 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 4758 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 4759 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4760 do {\ 4761 HWIO_INTLOCK(); \ 4762 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 4763 HWIO_INTFREE();\ 4764 } while (0) 4765 4766 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4767 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4768 4769 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 4770 4771 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000400) 4772 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000400) 4773 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x00ffffff 4774 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 4775 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 4776 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 4777 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 4778 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 4779 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 4780 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 4781 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4782 do {\ 4783 HWIO_INTLOCK(); \ 4784 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 4785 HWIO_INTFREE();\ 4786 } while (0) 4787 4788 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4789 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4790 4791 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4792 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4793 4794 //// Register REO_R0_REO2FW_RING_ID //// 4795 4796 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x00000404) 4797 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x00000404) 4798 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 4799 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 4800 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 4801 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 4802 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 4803 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 4804 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 4805 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 4806 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 4807 do {\ 4808 HWIO_INTLOCK(); \ 4809 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 4810 HWIO_INTFREE();\ 4811 } while (0) 4812 4813 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4814 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 4815 4816 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4817 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4818 4819 //// Register REO_R0_REO2FW_RING_STATUS //// 4820 4821 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000408) 4822 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000408) 4823 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 4824 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 4825 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 4826 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 4827 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 4828 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 4829 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 4830 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 4831 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 4832 do {\ 4833 HWIO_INTLOCK(); \ 4834 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 4835 HWIO_INTFREE();\ 4836 } while (0) 4837 4838 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4839 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4840 4841 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4842 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4843 4844 //// Register REO_R0_REO2FW_RING_MISC //// 4845 4846 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x0000040c) 4847 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x0000040c) 4848 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x0000003f 4849 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 4850 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 4851 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 4852 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 4853 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 4854 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 4855 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 4856 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 4857 do {\ 4858 HWIO_INTLOCK(); \ 4859 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 4860 HWIO_INTFREE();\ 4861 } while (0) 4862 4863 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4864 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4865 4866 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4867 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4868 4869 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4870 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4871 4872 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4873 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4874 4875 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4876 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4877 4878 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4879 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4880 4881 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 4882 4883 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 4884 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 4885 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4886 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 4887 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 4888 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 4889 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4890 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4891 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4892 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4893 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4894 do {\ 4895 HWIO_INTLOCK(); \ 4896 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 4897 HWIO_INTFREE();\ 4898 } while (0) 4899 4900 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4901 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4902 4903 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 4904 4905 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 4906 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 4907 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4908 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 4909 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 4910 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 4911 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4912 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4913 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4914 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4915 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4916 do {\ 4917 HWIO_INTLOCK(); \ 4918 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 4919 HWIO_INTFREE();\ 4920 } while (0) 4921 4922 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4923 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4924 4925 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 4926 4927 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 4928 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 4929 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4930 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4931 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4932 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 4933 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4934 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4935 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4936 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4937 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4938 do {\ 4939 HWIO_INTLOCK(); \ 4940 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4941 HWIO_INTFREE();\ 4942 } while (0) 4943 4944 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4945 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4946 4947 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4948 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4949 4950 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4951 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4952 4953 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 4954 4955 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 4956 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 4957 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4958 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4959 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4960 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 4961 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4962 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4963 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4964 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4965 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4966 do {\ 4967 HWIO_INTLOCK(); \ 4968 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4969 HWIO_INTFREE();\ 4970 } while (0) 4971 4972 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4973 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4974 4975 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4976 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4977 4978 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4979 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4980 4981 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 4982 4983 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 4984 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 4985 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4986 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4987 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4988 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4989 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4990 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4991 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4992 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4993 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4994 do {\ 4995 HWIO_INTLOCK(); \ 4996 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4997 HWIO_INTFREE();\ 4998 } while (0) 4999 5000 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5001 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5002 5003 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 5004 5005 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 5006 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 5007 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5008 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 5009 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 5010 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 5011 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 5012 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 5013 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 5014 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 5015 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5016 do {\ 5017 HWIO_INTLOCK(); \ 5018 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 5019 HWIO_INTFREE();\ 5020 } while (0) 5021 5022 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5023 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5024 5025 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 5026 5027 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 5028 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 5029 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5030 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 5031 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 5032 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 5033 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 5034 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 5035 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 5036 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 5037 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5038 do {\ 5039 HWIO_INTLOCK(); \ 5040 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 5041 HWIO_INTFREE();\ 5042 } while (0) 5043 5044 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5045 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5046 5047 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5048 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5049 5050 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 5051 5052 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 5053 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 5054 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 5055 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 5056 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 5057 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 5058 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 5059 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 5060 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 5061 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 5062 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 5063 do {\ 5064 HWIO_INTLOCK(); \ 5065 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 5066 HWIO_INTFREE();\ 5067 } while (0) 5068 5069 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5070 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 5071 5072 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 5073 5074 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 5075 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 5076 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5077 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 5078 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 5079 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 5080 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5081 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5082 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5083 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5084 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5085 do {\ 5086 HWIO_INTLOCK(); \ 5087 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 5088 HWIO_INTFREE();\ 5089 } while (0) 5090 5091 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5092 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5093 5094 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 5095 5096 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000454) 5097 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000454) 5098 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 5099 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 5100 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 5101 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 5102 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 5103 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 5104 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 5105 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 5106 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 5107 do {\ 5108 HWIO_INTLOCK(); \ 5109 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 5110 HWIO_INTFREE();\ 5111 } while (0) 5112 5113 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5114 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5115 5116 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 5117 5118 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000458) 5119 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000458) 5120 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 5121 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 5122 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 5123 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 5124 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 5125 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 5126 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 5127 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 5128 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 5129 do {\ 5130 HWIO_INTLOCK(); \ 5131 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 5132 HWIO_INTFREE();\ 5133 } while (0) 5134 5135 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5136 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5137 5138 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5139 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5140 5141 //// Register REO_R0_REO_RELEASE_RING_ID //// 5142 5143 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000045c) 5144 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000045c) 5145 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 5146 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 5147 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 5148 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 5149 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 5150 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 5151 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 5152 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 5153 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 5154 do {\ 5155 HWIO_INTLOCK(); \ 5156 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 5157 HWIO_INTFREE();\ 5158 } while (0) 5159 5160 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 5161 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 5162 5163 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5164 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5165 5166 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5167 5168 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000460) 5169 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000460) 5170 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5171 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5172 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5173 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5174 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5175 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5176 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5177 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5178 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5179 do {\ 5180 HWIO_INTLOCK(); \ 5181 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5182 HWIO_INTFREE();\ 5183 } while (0) 5184 5185 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5186 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5187 5188 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5189 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5190 5191 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5192 5193 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000464) 5194 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000464) 5195 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x0000003f 5196 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5197 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5198 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5199 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5200 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5201 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5202 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5203 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5204 do {\ 5205 HWIO_INTLOCK(); \ 5206 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5207 HWIO_INTFREE();\ 5208 } while (0) 5209 5210 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5211 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5212 5213 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5214 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5215 5216 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5217 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5218 5219 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5220 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5221 5222 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5223 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5224 5225 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5226 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5227 5228 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5229 5230 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 5231 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 5232 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5233 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5234 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5235 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5236 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5237 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5238 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5239 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5240 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5241 do {\ 5242 HWIO_INTLOCK(); \ 5243 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5244 HWIO_INTFREE();\ 5245 } while (0) 5246 5247 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5248 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5249 5250 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5251 5252 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 5253 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 5254 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5255 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5256 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5257 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5258 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5259 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5260 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5261 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5262 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5263 do {\ 5264 HWIO_INTLOCK(); \ 5265 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5266 HWIO_INTFREE();\ 5267 } while (0) 5268 5269 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5270 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5271 5272 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5273 5274 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 5275 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 5276 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5277 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5278 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5279 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5280 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5281 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5282 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5283 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5284 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5285 do {\ 5286 HWIO_INTLOCK(); \ 5287 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5288 HWIO_INTFREE();\ 5289 } while (0) 5290 5291 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5292 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5293 5294 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5295 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5296 5297 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5298 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5299 5300 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5301 5302 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 5303 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 5304 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5305 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5306 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5307 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5308 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5309 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5310 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5311 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5312 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5313 do {\ 5314 HWIO_INTLOCK(); \ 5315 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5316 HWIO_INTFREE();\ 5317 } while (0) 5318 5319 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5320 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5321 5322 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5323 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5324 5325 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5326 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5327 5328 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5329 5330 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 5331 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 5332 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5333 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5334 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5335 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5336 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5337 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5338 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5339 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5340 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5341 do {\ 5342 HWIO_INTLOCK(); \ 5343 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5344 HWIO_INTFREE();\ 5345 } while (0) 5346 5347 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5348 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5349 5350 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 5351 5352 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 5353 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 5354 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5355 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 5356 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 5357 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 5358 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5359 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5360 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5361 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5362 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5363 do {\ 5364 HWIO_INTLOCK(); \ 5365 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 5366 HWIO_INTFREE();\ 5367 } while (0) 5368 5369 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5370 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5371 5372 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 5373 5374 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 5375 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 5376 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 5377 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 5378 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 5379 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 5380 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 5381 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 5382 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 5383 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 5384 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 5385 do {\ 5386 HWIO_INTLOCK(); \ 5387 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 5388 HWIO_INTFREE();\ 5389 } while (0) 5390 5391 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5392 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5393 5394 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 5395 5396 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 5397 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 5398 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 5399 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 5400 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 5401 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 5402 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 5403 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 5404 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 5405 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 5406 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 5407 do {\ 5408 HWIO_INTLOCK(); \ 5409 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 5410 HWIO_INTFREE();\ 5411 } while (0) 5412 5413 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5414 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5415 5416 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5417 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5418 5419 //// Register REO_R0_REO_STATUS_RING_ID //// 5420 5421 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x000004b4) 5422 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x000004b4) 5423 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 5424 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 5425 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 5426 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 5427 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 5428 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 5429 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 5430 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 5431 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 5432 do {\ 5433 HWIO_INTLOCK(); \ 5434 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 5435 HWIO_INTFREE();\ 5436 } while (0) 5437 5438 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 5439 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 5440 5441 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5442 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 5443 5444 //// Register REO_R0_REO_STATUS_RING_STATUS //// 5445 5446 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x000004b8) 5447 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x000004b8) 5448 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 5449 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 5450 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 5451 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 5452 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 5453 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 5454 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 5455 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 5456 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 5457 do {\ 5458 HWIO_INTLOCK(); \ 5459 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 5460 HWIO_INTFREE();\ 5461 } while (0) 5462 5463 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5464 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5465 5466 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5467 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5468 5469 //// Register REO_R0_REO_STATUS_RING_MISC //// 5470 5471 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x000004bc) 5472 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x000004bc) 5473 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x0000003f 5474 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 5475 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 5476 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 5477 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 5478 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 5479 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 5480 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 5481 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 5482 do {\ 5483 HWIO_INTLOCK(); \ 5484 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 5485 HWIO_INTFREE();\ 5486 } while (0) 5487 5488 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5489 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5490 5491 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5492 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5493 5494 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5495 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5496 5497 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5498 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 5499 5500 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5501 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5502 5503 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5504 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5505 5506 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 5507 5508 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5509 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5510 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 5511 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 5512 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 5513 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 5514 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 5515 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 5516 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 5517 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 5518 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5519 do {\ 5520 HWIO_INTLOCK(); \ 5521 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 5522 HWIO_INTFREE();\ 5523 } while (0) 5524 5525 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5526 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5527 5528 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 5529 5530 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5531 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5532 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 5533 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 5534 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 5535 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 5536 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 5537 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 5538 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 5539 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 5540 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5541 do {\ 5542 HWIO_INTLOCK(); \ 5543 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 5544 HWIO_INTFREE();\ 5545 } while (0) 5546 5547 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5548 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5549 5550 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 5551 5552 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5553 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5554 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5555 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 5556 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 5557 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 5558 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5559 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5560 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5561 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5562 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5563 do {\ 5564 HWIO_INTLOCK(); \ 5565 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 5566 HWIO_INTFREE();\ 5567 } while (0) 5568 5569 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5570 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5571 5572 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5573 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5574 5575 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5576 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5577 5578 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 5579 5580 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5581 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5582 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5583 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 5584 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 5585 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 5586 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5587 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5588 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5589 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5590 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5591 do {\ 5592 HWIO_INTLOCK(); \ 5593 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 5594 HWIO_INTFREE();\ 5595 } while (0) 5596 5597 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5598 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5599 5600 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5601 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5602 5603 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5604 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5605 5606 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 5607 5608 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5609 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5610 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5611 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 5612 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5613 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 5614 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5615 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5616 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5617 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5618 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5619 do {\ 5620 HWIO_INTLOCK(); \ 5621 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5622 HWIO_INTFREE();\ 5623 } while (0) 5624 5625 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5626 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5627 5628 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 5629 5630 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) 5631 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) 5632 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5633 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 5634 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 5635 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 5636 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 5637 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 5638 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 5639 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 5640 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5641 do {\ 5642 HWIO_INTLOCK(); \ 5643 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 5644 HWIO_INTFREE();\ 5645 } while (0) 5646 5647 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5648 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5649 5650 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 5651 5652 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) 5653 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) 5654 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5655 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 5656 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 5657 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 5658 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 5659 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 5660 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 5661 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 5662 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5663 do {\ 5664 HWIO_INTLOCK(); \ 5665 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 5666 HWIO_INTFREE();\ 5667 } while (0) 5668 5669 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5670 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5671 5672 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5673 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5674 5675 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 5676 5677 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) 5678 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) 5679 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 5680 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 5681 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 5682 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 5683 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 5684 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 5685 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 5686 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 5687 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 5688 do {\ 5689 HWIO_INTLOCK(); \ 5690 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 5691 HWIO_INTFREE();\ 5692 } while (0) 5693 5694 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5695 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 5696 5697 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 5698 5699 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 5700 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 5701 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5702 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 5703 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 5704 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 5705 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5706 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5707 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5708 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5709 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5710 do {\ 5711 HWIO_INTLOCK(); \ 5712 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 5713 HWIO_INTFREE();\ 5714 } while (0) 5715 5716 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5717 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5718 5719 //// Register REO_R0_WATCHDOG_TIMEOUT //// 5720 5721 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) 5722 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) 5723 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff 5724 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 5725 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 5726 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 5727 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 5728 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 5729 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 5730 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 5731 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 5732 do {\ 5733 HWIO_INTLOCK(); \ 5734 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 5735 HWIO_INTFREE();\ 5736 } while (0) 5737 5738 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 5739 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 5740 5741 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 5742 5743 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000508) 5744 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000508) 5745 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 5746 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 5747 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 5748 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 5749 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 5750 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 5751 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 5752 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 5753 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 5754 do {\ 5755 HWIO_INTLOCK(); \ 5756 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 5757 HWIO_INTFREE();\ 5758 } while (0) 5759 5760 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 5761 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 5762 5763 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 5764 5765 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x0000050c) 5766 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x0000050c) 5767 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 5768 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 5769 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 5770 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 5771 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 5772 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 5773 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 5774 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 5775 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 5776 do {\ 5777 HWIO_INTLOCK(); \ 5778 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 5779 HWIO_INTFREE();\ 5780 } while (0) 5781 5782 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 5783 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 5784 5785 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 5786 5787 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000510) 5788 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000510) 5789 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 5790 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 5791 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 5792 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 5793 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 5794 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 5795 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 5796 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 5797 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 5798 do {\ 5799 HWIO_INTLOCK(); \ 5800 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 5801 HWIO_INTFREE();\ 5802 } while (0) 5803 5804 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 5805 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 5806 5807 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 5808 5809 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x00000514) 5810 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x00000514) 5811 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 5812 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 5813 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 5814 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 5815 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 5816 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 5817 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 5818 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 5819 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 5820 do {\ 5821 HWIO_INTLOCK(); \ 5822 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 5823 HWIO_INTFREE();\ 5824 } while (0) 5825 5826 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 5827 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 5828 5829 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 5830 5831 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000518) 5832 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000518) 5833 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 5834 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 5835 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 5836 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 5837 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 5838 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 5839 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 5840 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 5841 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 5842 do {\ 5843 HWIO_INTLOCK(); \ 5844 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 5845 HWIO_INTFREE();\ 5846 } while (0) 5847 5848 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 5849 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 5850 5851 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 5852 5853 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x0000051c) 5854 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x0000051c) 5855 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 5856 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 5857 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 5858 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 5859 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 5860 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 5861 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 5862 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 5863 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 5864 do {\ 5865 HWIO_INTLOCK(); \ 5866 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 5867 HWIO_INTFREE();\ 5868 } while (0) 5869 5870 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5871 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 5872 5873 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 5874 5875 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000520) 5876 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000520) 5877 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 5878 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 5879 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 5880 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 5881 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 5882 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 5883 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 5884 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 5885 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 5886 do {\ 5887 HWIO_INTLOCK(); \ 5888 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 5889 HWIO_INTFREE();\ 5890 } while (0) 5891 5892 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5893 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 5894 5895 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 5896 5897 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x00000524) 5898 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x00000524) 5899 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 5900 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 5901 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 5902 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 5903 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 5904 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 5905 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 5906 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 5907 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 5908 do {\ 5909 HWIO_INTLOCK(); \ 5910 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 5911 HWIO_INTFREE();\ 5912 } while (0) 5913 5914 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 5915 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 5916 5917 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 5918 5919 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000528) 5920 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000528) 5921 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 5922 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 5923 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 5924 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 5925 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 5926 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 5927 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 5928 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 5929 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 5930 do {\ 5931 HWIO_INTLOCK(); \ 5932 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 5933 HWIO_INTFREE();\ 5934 } while (0) 5935 5936 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 5937 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 5938 5939 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 5940 5941 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x0000052c) 5942 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x0000052c) 5943 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 5944 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 5945 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 5946 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 5947 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 5948 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 5949 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 5950 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 5951 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 5952 do {\ 5953 HWIO_INTLOCK(); \ 5954 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 5955 HWIO_INTFREE();\ 5956 } while (0) 5957 5958 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 5959 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 5960 5961 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 5962 5963 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000530) 5964 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000530) 5965 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 5966 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 5967 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 5968 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 5969 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 5970 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 5971 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 5972 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 5973 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 5974 do {\ 5975 HWIO_INTLOCK(); \ 5976 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 5977 HWIO_INTFREE();\ 5978 } while (0) 5979 5980 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 5981 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 5982 5983 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 5984 5985 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x00000534) 5986 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x00000534) 5987 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 5988 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 5989 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 5990 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 5991 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 5992 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 5993 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 5994 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 5995 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 5996 do {\ 5997 HWIO_INTLOCK(); \ 5998 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 5999 HWIO_INTFREE();\ 6000 } while (0) 6001 6002 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6003 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 6004 6005 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 6006 6007 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000538) 6008 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000538) 6009 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 6010 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 6011 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 6012 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 6013 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 6014 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 6015 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 6016 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 6017 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 6018 do {\ 6019 HWIO_INTLOCK(); \ 6020 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 6021 HWIO_INTFREE();\ 6022 } while (0) 6023 6024 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6025 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 6026 6027 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 6028 6029 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x0000053c) 6030 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x0000053c) 6031 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 6032 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 6033 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 6034 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 6035 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 6036 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 6037 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 6038 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 6039 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 6040 do {\ 6041 HWIO_INTLOCK(); \ 6042 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 6043 HWIO_INTFREE();\ 6044 } while (0) 6045 6046 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6047 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 6048 6049 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 6050 6051 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000540) 6052 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000540) 6053 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 6054 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6055 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6056 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6057 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6058 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6059 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6060 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6061 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6062 do {\ 6063 HWIO_INTLOCK(); \ 6064 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6065 HWIO_INTFREE();\ 6066 } while (0) 6067 6068 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6069 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6070 6071 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6072 6073 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x00000544) 6074 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x00000544) 6075 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6076 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6077 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6078 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6079 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6080 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6081 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6082 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6083 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6084 do {\ 6085 HWIO_INTLOCK(); \ 6086 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6087 HWIO_INTFREE();\ 6088 } while (0) 6089 6090 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6091 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6092 6093 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6094 6095 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x00000548) 6096 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x00000548) 6097 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6098 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6099 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6100 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6101 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6102 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6103 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6104 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6105 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6106 do {\ 6107 HWIO_INTLOCK(); \ 6108 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6109 HWIO_INTFREE();\ 6110 } while (0) 6111 6112 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6113 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6114 6115 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6116 6117 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x0000054c) 6118 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x0000054c) 6119 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6120 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6121 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6122 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6123 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6124 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6125 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6126 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6127 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6128 do {\ 6129 HWIO_INTLOCK(); \ 6130 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6131 HWIO_INTFREE();\ 6132 } while (0) 6133 6134 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6135 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6136 6137 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6138 6139 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x00000550) 6140 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x00000550) 6141 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6142 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6143 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6144 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6145 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6146 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6147 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6148 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6149 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6150 do {\ 6151 HWIO_INTLOCK(); \ 6152 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6153 HWIO_INTFREE();\ 6154 } while (0) 6155 6156 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6157 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6158 6159 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6160 6161 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x00000554) 6162 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x00000554) 6163 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6164 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6165 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6166 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6167 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6168 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6169 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6170 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6171 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6172 do {\ 6173 HWIO_INTLOCK(); \ 6174 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6175 HWIO_INTFREE();\ 6176 } while (0) 6177 6178 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6179 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6180 6181 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6182 6183 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x00000558) 6184 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x00000558) 6185 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6186 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6187 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6188 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6189 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6190 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6191 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6192 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6193 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6194 do {\ 6195 HWIO_INTLOCK(); \ 6196 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6197 HWIO_INTFREE();\ 6198 } while (0) 6199 6200 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6201 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6202 6203 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6204 6205 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x0000055c) 6206 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x0000055c) 6207 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6208 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6209 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6210 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6211 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6212 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6213 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6214 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6215 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6216 do {\ 6217 HWIO_INTLOCK(); \ 6218 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6219 HWIO_INTFREE();\ 6220 } while (0) 6221 6222 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6223 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6224 6225 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6226 6227 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x00000560) 6228 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x00000560) 6229 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6230 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6231 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6232 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6233 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6234 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6235 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6236 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6237 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6238 do {\ 6239 HWIO_INTLOCK(); \ 6240 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6241 HWIO_INTFREE();\ 6242 } while (0) 6243 6244 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6245 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6246 6247 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6248 6249 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x00000564) 6250 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x00000564) 6251 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6252 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6253 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6254 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6255 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6256 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6257 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6258 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6259 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6260 do {\ 6261 HWIO_INTLOCK(); \ 6262 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6263 HWIO_INTFREE();\ 6264 } while (0) 6265 6266 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6267 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6268 6269 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6270 6271 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x00000568) 6272 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x00000568) 6273 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6274 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6275 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6276 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6277 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6278 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6279 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6280 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6281 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6282 do {\ 6283 HWIO_INTLOCK(); \ 6284 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6285 HWIO_INTFREE();\ 6286 } while (0) 6287 6288 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6289 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6290 6291 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6292 6293 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x0000056c) 6294 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x0000056c) 6295 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6296 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6297 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6298 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6299 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6300 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6301 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6302 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6303 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6304 do {\ 6305 HWIO_INTLOCK(); \ 6306 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6307 HWIO_INTFREE();\ 6308 } while (0) 6309 6310 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6311 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6312 6313 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 6314 6315 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x00000570) 6316 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x00000570) 6317 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 6318 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 6319 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 6320 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 6321 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 6322 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 6323 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 6324 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 6325 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 6326 do {\ 6327 HWIO_INTLOCK(); \ 6328 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 6329 HWIO_INTFREE();\ 6330 } while (0) 6331 6332 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 6333 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 6334 6335 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 6336 6337 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x00000574) 6338 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x00000574) 6339 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 6340 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 6341 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 6342 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 6343 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 6344 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 6345 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 6346 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 6347 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 6348 do {\ 6349 HWIO_INTLOCK(); \ 6350 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 6351 HWIO_INTFREE();\ 6352 } while (0) 6353 6354 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 6355 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 6356 6357 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 6358 6359 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x00000578) 6360 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x00000578) 6361 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 6362 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 6363 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 6364 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 6365 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 6366 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 6367 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 6368 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 6369 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 6370 do {\ 6371 HWIO_INTLOCK(); \ 6372 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 6373 HWIO_INTFREE();\ 6374 } while (0) 6375 6376 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 6377 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 6378 6379 //// Register REO_R0_AGING_CONTROL //// 6380 6381 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x0000057c) 6382 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x0000057c) 6383 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 6384 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 6385 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 6386 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 6387 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 6388 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 6389 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 6390 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 6391 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 6392 do {\ 6393 HWIO_INTLOCK(); \ 6394 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 6395 HWIO_INTFREE();\ 6396 } while (0) 6397 6398 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 6399 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 6400 6401 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 6402 6403 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x00000580) 6404 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x00000580) 6405 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 6406 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 6407 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 6408 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 6409 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 6410 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 6411 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 6412 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 6413 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 6414 do {\ 6415 HWIO_INTLOCK(); \ 6416 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 6417 HWIO_INTFREE();\ 6418 } while (0) 6419 6420 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 6421 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 6422 6423 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 6424 6425 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x00000584) 6426 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x00000584) 6427 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 6428 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 6429 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 6430 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 6431 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 6432 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 6433 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 6434 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 6435 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 6436 do {\ 6437 HWIO_INTLOCK(); \ 6438 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 6439 HWIO_INTFREE();\ 6440 } while (0) 6441 6442 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 6443 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 6444 6445 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 6446 6447 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x00000588) 6448 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x00000588) 6449 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 6450 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 6451 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 6452 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 6453 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 6454 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 6455 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 6456 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 6457 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 6458 do {\ 6459 HWIO_INTLOCK(); \ 6460 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 6461 HWIO_INTFREE();\ 6462 } while (0) 6463 6464 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 6465 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 6466 6467 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 6468 6469 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x0000058c) 6470 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x0000058c) 6471 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 6472 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 6473 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 6474 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 6475 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 6476 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 6477 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 6478 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 6479 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 6480 do {\ 6481 HWIO_INTLOCK(); \ 6482 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 6483 HWIO_INTFREE();\ 6484 } while (0) 6485 6486 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 6487 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 6488 6489 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 6490 6491 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x00000590) 6492 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x00000590) 6493 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 6494 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 6495 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 6496 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 6497 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 6498 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 6499 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 6500 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 6501 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 6502 do {\ 6503 HWIO_INTLOCK(); \ 6504 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 6505 HWIO_INTFREE();\ 6506 } while (0) 6507 6508 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 6509 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 6510 6511 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 6512 6513 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x00000594) 6514 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x00000594) 6515 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 6516 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 6517 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 6518 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 6519 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 6520 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 6521 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 6522 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 6523 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 6524 do {\ 6525 HWIO_INTLOCK(); \ 6526 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 6527 HWIO_INTFREE();\ 6528 } while (0) 6529 6530 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 6531 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 6532 6533 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 6534 6535 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x00000598) 6536 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x00000598) 6537 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 6538 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 6539 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 6540 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 6541 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 6542 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 6543 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 6544 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 6545 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 6546 do {\ 6547 HWIO_INTLOCK(); \ 6548 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 6549 HWIO_INTFREE();\ 6550 } while (0) 6551 6552 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 6553 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 6554 6555 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 6556 6557 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x0000059c) 6558 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x0000059c) 6559 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 6560 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 6561 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 6562 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 6563 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 6564 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 6565 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 6566 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 6567 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 6568 do {\ 6569 HWIO_INTLOCK(); \ 6570 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 6571 HWIO_INTFREE();\ 6572 } while (0) 6573 6574 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 6575 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 6576 6577 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 6578 6579 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005a0) 6580 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005a0) 6581 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 6582 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 6583 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 6584 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 6585 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 6586 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 6587 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 6588 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 6589 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 6590 do {\ 6591 HWIO_INTLOCK(); \ 6592 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 6593 HWIO_INTFREE();\ 6594 } while (0) 6595 6596 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 6597 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 6598 6599 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 6600 6601 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x000005a4) 6602 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x000005a4) 6603 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 6604 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 6605 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 6606 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 6607 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 6608 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 6609 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 6610 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 6611 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 6612 do {\ 6613 HWIO_INTLOCK(); \ 6614 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 6615 HWIO_INTFREE();\ 6616 } while (0) 6617 6618 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 6619 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 6620 6621 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 6622 6623 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x000005a8) 6624 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x000005a8) 6625 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 6626 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 6627 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 6628 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 6629 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 6630 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 6631 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 6632 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 6633 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 6634 do {\ 6635 HWIO_INTLOCK(); \ 6636 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 6637 HWIO_INTFREE();\ 6638 } while (0) 6639 6640 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 6641 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 6642 6643 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 6644 6645 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x000005ac) 6646 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x000005ac) 6647 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 6648 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 6649 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 6650 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 6651 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 6652 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 6653 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 6654 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 6655 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 6656 do {\ 6657 HWIO_INTLOCK(); \ 6658 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 6659 HWIO_INTFREE();\ 6660 } while (0) 6661 6662 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 6663 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 6664 6665 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 6666 6667 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x000005b0) 6668 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x000005b0) 6669 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 6670 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 6671 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 6672 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 6673 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 6674 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 6675 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 6676 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 6677 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 6678 do {\ 6679 HWIO_INTLOCK(); \ 6680 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 6681 HWIO_INTFREE();\ 6682 } while (0) 6683 6684 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 6685 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 6686 6687 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 6688 6689 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x000005b4) 6690 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x000005b4) 6691 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 6692 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 6693 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 6694 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 6695 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 6696 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 6697 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 6698 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 6699 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 6700 do {\ 6701 HWIO_INTLOCK(); \ 6702 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 6703 HWIO_INTFREE();\ 6704 } while (0) 6705 6706 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 6707 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 6708 6709 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 6710 6711 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x000005b8) 6712 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x000005b8) 6713 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 6714 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 6715 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 6716 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 6717 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 6718 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 6719 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 6720 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 6721 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 6722 do {\ 6723 HWIO_INTLOCK(); \ 6724 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 6725 HWIO_INTFREE();\ 6726 } while (0) 6727 6728 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 6729 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 6730 6731 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 6732 6733 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x000005bc) 6734 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x000005bc) 6735 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 6736 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 6737 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 6738 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 6739 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 6740 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 6741 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 6742 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 6743 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 6744 do {\ 6745 HWIO_INTLOCK(); \ 6746 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 6747 HWIO_INTFREE();\ 6748 } while (0) 6749 6750 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 6751 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 6752 6753 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 6754 6755 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x000005c0) 6756 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x000005c0) 6757 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 6758 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 6759 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 6760 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 6761 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 6762 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 6763 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 6764 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 6765 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 6766 do {\ 6767 HWIO_INTLOCK(); \ 6768 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 6769 HWIO_INTFREE();\ 6770 } while (0) 6771 6772 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 6773 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 6774 6775 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 6776 6777 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x000005c4) 6778 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x000005c4) 6779 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 6780 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 6781 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 6782 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 6783 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 6784 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 6785 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 6786 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 6787 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 6788 do {\ 6789 HWIO_INTLOCK(); \ 6790 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 6791 HWIO_INTFREE();\ 6792 } while (0) 6793 6794 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 6795 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 6796 6797 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 6798 6799 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x000005c8) 6800 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x000005c8) 6801 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 6802 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 6803 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 6804 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 6805 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 6806 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 6807 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 6808 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 6809 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 6810 do {\ 6811 HWIO_INTLOCK(); \ 6812 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 6813 HWIO_INTFREE();\ 6814 } while (0) 6815 6816 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 6817 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 6818 6819 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 6820 6821 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x000005cc) 6822 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x000005cc) 6823 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 6824 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 6825 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 6826 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 6827 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 6828 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 6829 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 6830 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 6831 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 6832 do {\ 6833 HWIO_INTLOCK(); \ 6834 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 6835 HWIO_INTFREE();\ 6836 } while (0) 6837 6838 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 6839 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 6840 6841 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 6842 6843 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x000005d0) 6844 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x000005d0) 6845 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 6846 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 6847 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 6848 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 6849 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 6850 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 6851 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 6852 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 6853 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 6854 do {\ 6855 HWIO_INTLOCK(); \ 6856 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 6857 HWIO_INTFREE();\ 6858 } while (0) 6859 6860 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 6861 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 6862 6863 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 6864 6865 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x000005d4) 6866 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x000005d4) 6867 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 6868 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 6869 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 6870 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 6871 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 6872 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 6873 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 6874 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 6875 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 6876 do {\ 6877 HWIO_INTLOCK(); \ 6878 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 6879 HWIO_INTFREE();\ 6880 } while (0) 6881 6882 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 6883 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 6884 6885 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 6886 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 6887 6888 //// Register REO_R0_GXI_TESTBUS_LOWER //// 6889 6890 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000005d8) 6891 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000005d8) 6892 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 6893 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 6894 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 6895 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 6896 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 6897 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 6898 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 6899 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 6900 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 6901 do {\ 6902 HWIO_INTLOCK(); \ 6903 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 6904 HWIO_INTFREE();\ 6905 } while (0) 6906 6907 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 6908 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 6909 6910 //// Register REO_R0_GXI_TESTBUS_UPPER //// 6911 6912 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000005dc) 6913 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000005dc) 6914 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 6915 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 6916 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 6917 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 6918 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 6919 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 6920 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 6921 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 6922 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 6923 do {\ 6924 HWIO_INTLOCK(); \ 6925 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 6926 HWIO_INTFREE();\ 6927 } while (0) 6928 6929 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 6930 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 6931 6932 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 6933 6934 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000005e0) 6935 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000005e0) 6936 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 6937 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 6938 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 6939 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 6940 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 6941 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 6942 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 6943 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 6944 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 6945 do {\ 6946 HWIO_INTLOCK(); \ 6947 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 6948 HWIO_INTFREE();\ 6949 } while (0) 6950 6951 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 6952 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 6953 6954 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 6955 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 6956 6957 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 6958 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 6959 6960 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 6961 6962 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000005e4) 6963 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000005e4) 6964 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 6965 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 6966 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 6967 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 6968 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 6969 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 6970 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 6971 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 6972 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6973 do {\ 6974 HWIO_INTLOCK(); \ 6975 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 6976 HWIO_INTFREE();\ 6977 } while (0) 6978 6979 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6980 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6981 6982 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 6983 6984 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000005e8) 6985 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000005e8) 6986 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 6987 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 6988 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 6989 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 6990 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 6991 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 6992 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 6993 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 6994 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 6995 do {\ 6996 HWIO_INTLOCK(); \ 6997 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 6998 HWIO_INTFREE();\ 6999 } while (0) 7000 7001 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 7002 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 7003 7004 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff 7005 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT 0x0 7006 7007 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7008 7009 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000005ec) 7010 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000005ec) 7011 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7012 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7013 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7014 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7015 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7016 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7017 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7018 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7019 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7020 do {\ 7021 HWIO_INTLOCK(); \ 7022 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7023 HWIO_INTFREE();\ 7024 } while (0) 7025 7026 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7027 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7028 7029 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7030 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7031 7032 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7033 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7034 7035 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7036 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7037 7038 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7039 7040 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000005f0) 7041 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000005f0) 7042 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7043 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7044 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7045 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7046 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7047 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7048 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7049 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 7050 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 7051 do {\ 7052 HWIO_INTLOCK(); \ 7053 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 7054 HWIO_INTFREE();\ 7055 } while (0) 7056 7057 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 7058 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 7059 7060 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 7061 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 7062 7063 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 7064 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 7065 7066 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 7067 7068 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000005f4) 7069 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000005f4) 7070 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 7071 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 7072 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 7073 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 7074 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 7075 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 7076 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 7077 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 7078 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 7079 do {\ 7080 HWIO_INTLOCK(); \ 7081 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 7082 HWIO_INTFREE();\ 7083 } while (0) 7084 7085 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 7086 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 7087 7088 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7089 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 7090 7091 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 7092 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 7093 7094 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 7095 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 7096 7097 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 7098 7099 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000005f8) 7100 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000005f8) 7101 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 7102 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 7103 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 7104 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 7105 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 7106 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 7107 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 7108 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 7109 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 7110 do {\ 7111 HWIO_INTLOCK(); \ 7112 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 7113 HWIO_INTFREE();\ 7114 } while (0) 7115 7116 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 7117 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 7118 7119 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7120 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 7121 7122 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 7123 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 7124 7125 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 7126 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 7127 7128 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 7129 7130 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000005fc) 7131 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000005fc) 7132 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff 7133 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 7134 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 7135 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 7136 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 7137 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 7138 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 7139 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 7140 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 7141 do {\ 7142 HWIO_INTLOCK(); \ 7143 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 7144 HWIO_INTFREE();\ 7145 } while (0) 7146 7147 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 7148 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 7149 7150 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 7151 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 7152 7153 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 7154 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 7155 7156 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 7157 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 7158 7159 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 7160 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 7161 7162 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 7163 7164 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000600) 7165 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000600) 7166 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 7167 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 7168 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 7169 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 7170 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 7171 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 7172 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 7173 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 7174 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 7175 do {\ 7176 HWIO_INTLOCK(); \ 7177 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 7178 HWIO_INTFREE();\ 7179 } while (0) 7180 7181 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 7182 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 7183 7184 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 7185 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 7186 7187 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 7188 7189 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000604) 7190 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000604) 7191 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 7192 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 7193 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 7194 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 7195 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 7196 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 7197 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 7198 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 7199 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 7200 do {\ 7201 HWIO_INTLOCK(); \ 7202 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 7203 HWIO_INTFREE();\ 7204 } while (0) 7205 7206 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 7207 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 7208 7209 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 7210 7211 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000608) 7212 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000608) 7213 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 7214 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 7215 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 7216 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 7217 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 7218 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 7219 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 7220 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 7221 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 7222 do {\ 7223 HWIO_INTLOCK(); \ 7224 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 7225 HWIO_INTFREE();\ 7226 } while (0) 7227 7228 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 7229 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 7230 7231 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 7232 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 7233 7234 //// Register REO_R0_CACHE_CTL_CONFIG //// 7235 7236 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x0000060c) 7237 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x0000060c) 7238 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0x003f7fff 7239 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 7240 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 7241 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 7242 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 7243 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 7244 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 7245 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 7246 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 7247 do {\ 7248 HWIO_INTLOCK(); \ 7249 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 7250 HWIO_INTFREE();\ 7251 } while (0) 7252 7253 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00200000 7254 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x15 7255 7256 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00100000 7257 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x14 7258 7259 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00080000 7260 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x13 7261 7262 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00040000 7263 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x12 7264 7265 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00020000 7266 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x11 7267 7268 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00010000 7269 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x10 7270 7271 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x00007f00 7272 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x8 7273 7274 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000000ff 7275 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 7276 7277 //// Register REO_R0_CACHE_CTL_CONTROL //// 7278 7279 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x00000610) 7280 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x00000610) 7281 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000001 7282 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 7283 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 7284 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 7285 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 7286 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 7287 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 7288 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 7289 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 7290 do {\ 7291 HWIO_INTLOCK(); \ 7292 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 7293 HWIO_INTFREE();\ 7294 } while (0) 7295 7296 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 7297 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 7298 7299 //// Register REO_R0_CLK_GATE_CTRL //// 7300 7301 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000614) 7302 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000614) 7303 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 7304 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 7305 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 7306 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 7307 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 7308 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 7309 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 7310 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 7311 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 7312 do {\ 7313 HWIO_INTLOCK(); \ 7314 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 7315 HWIO_INTFREE();\ 7316 } while (0) 7317 7318 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 7319 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 7320 7321 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 7322 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 7323 7324 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 7325 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 7326 7327 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 7328 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 7329 7330 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 7331 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 7332 7333 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 7334 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 7335 7336 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK 0x00001000 7337 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT 0xc 7338 7339 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK 0x00000800 7340 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT 0xb 7341 7342 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 7343 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 7344 7345 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 7346 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 7347 7348 //// Register REO_R0_EVENTMASK_IX_0 //// 7349 7350 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x00000618) 7351 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x00000618) 7352 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 7353 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 7354 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 7355 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 7356 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 7357 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 7358 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 7359 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 7360 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 7361 do {\ 7362 HWIO_INTLOCK(); \ 7363 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 7364 HWIO_INTFREE();\ 7365 } while (0) 7366 7367 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 7368 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 7369 7370 //// Register REO_R0_EVENTMASK_IX_1 //// 7371 7372 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x0000061c) 7373 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x0000061c) 7374 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 7375 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 7376 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 7377 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 7378 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 7379 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 7380 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 7381 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 7382 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 7383 do {\ 7384 HWIO_INTLOCK(); \ 7385 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 7386 HWIO_INTFREE();\ 7387 } while (0) 7388 7389 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 7390 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 7391 7392 //// Register REO_R0_EVENTMASK_IX_2 //// 7393 7394 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x00000620) 7395 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x00000620) 7396 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 7397 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 7398 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 7399 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 7400 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 7401 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 7402 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 7403 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 7404 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 7405 do {\ 7406 HWIO_INTLOCK(); \ 7407 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 7408 HWIO_INTFREE();\ 7409 } while (0) 7410 7411 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 7412 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 7413 7414 //// Register REO_R0_EVENTMASK_IX_3 //// 7415 7416 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x00000624) 7417 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x00000624) 7418 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 7419 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 7420 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 7421 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 7422 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 7423 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 7424 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 7425 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 7426 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 7427 do {\ 7428 HWIO_INTLOCK(); \ 7429 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 7430 HWIO_INTFREE();\ 7431 } while (0) 7432 7433 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 7434 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 7435 7436 //// Register REO_R1_MISC_DEBUG_CTRL //// 7437 7438 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 7439 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 7440 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0x3fffffff 7441 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 7442 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 7443 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 7444 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 7445 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 7446 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 7447 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 7448 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 7449 do {\ 7450 HWIO_INTLOCK(); \ 7451 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 7452 HWIO_INTFREE();\ 7453 } while (0) 7454 7455 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 7456 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 7457 7458 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 7459 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 7460 7461 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 7462 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 7463 7464 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 7465 7466 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 7467 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 7468 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 7469 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 7470 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 7471 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 7472 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 7473 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 7474 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 7475 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 7476 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 7477 do {\ 7478 HWIO_INTLOCK(); \ 7479 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 7480 HWIO_INTFREE();\ 7481 } while (0) 7482 7483 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 7484 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 7485 7486 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 7487 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 7488 7489 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 7490 7491 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 7492 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 7493 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x000003ff 7494 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 7495 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 7496 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 7497 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 7498 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 7499 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 7500 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 7501 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 7502 do {\ 7503 HWIO_INTLOCK(); \ 7504 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 7505 HWIO_INTFREE();\ 7506 } while (0) 7507 7508 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000200 7509 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0x9 7510 7511 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000100 7512 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0x8 7513 7514 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000080 7515 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x7 7516 7517 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x0000007f 7518 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 7519 7520 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 7521 7522 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 7523 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 7524 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 7525 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 7526 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 7527 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 7528 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 7529 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 7530 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 7531 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 7532 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 7533 do {\ 7534 HWIO_INTLOCK(); \ 7535 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 7536 HWIO_INTFREE();\ 7537 } while (0) 7538 7539 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 7540 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 7541 7542 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 7543 7544 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 7545 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 7546 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 7547 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 7548 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 7549 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 7550 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 7551 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 7552 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 7553 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 7554 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 7555 do {\ 7556 HWIO_INTLOCK(); \ 7557 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 7558 HWIO_INTFREE();\ 7559 } while (0) 7560 7561 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 7562 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 7563 7564 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 7565 7566 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 7567 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 7568 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 7569 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 7570 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 7571 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 7572 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 7573 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 7574 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 7575 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 7576 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 7577 do {\ 7578 HWIO_INTLOCK(); \ 7579 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 7580 HWIO_INTFREE();\ 7581 } while (0) 7582 7583 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 7584 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 7585 7586 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 7587 7588 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 7589 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 7590 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0x03ffffff 7591 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 7592 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 7593 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 7594 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 7595 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 7596 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 7597 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 7598 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 7599 do {\ 7600 HWIO_INTLOCK(); \ 7601 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 7602 HWIO_INTFREE();\ 7603 } while (0) 7604 7605 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0x03ffffff 7606 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 7607 7608 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 7609 7610 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 7611 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 7612 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 7613 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 7614 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 7615 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 7616 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 7617 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 7618 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 7619 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 7620 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 7621 do {\ 7622 HWIO_INTLOCK(); \ 7623 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 7624 HWIO_INTFREE();\ 7625 } while (0) 7626 7627 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 7628 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 7629 7630 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 7631 7632 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 7633 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 7634 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0xffffffff 7635 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 7636 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 7637 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 7638 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 7639 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 7640 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 7641 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 7642 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 7643 do {\ 7644 HWIO_INTLOCK(); \ 7645 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 7646 HWIO_INTFREE();\ 7647 } while (0) 7648 7649 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK 0xff000000 7650 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT 0x18 7651 7652 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_BMSK 0x00ff0000 7653 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_SHFT 0x10 7654 7655 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0000ff00 7656 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0x8 7657 7658 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000000ff 7659 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 7660 7661 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 7662 7663 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x00002024) 7664 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x00002024) 7665 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 7666 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 7667 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 7668 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 7669 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 7670 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 7671 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 7672 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 7673 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7674 do {\ 7675 HWIO_INTLOCK(); \ 7676 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 7677 HWIO_INTFREE();\ 7678 } while (0) 7679 7680 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7681 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7682 7683 //// Register REO_R1_END_OF_TEST_CHECK //// 7684 7685 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002028) 7686 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002028) 7687 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 7688 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 7689 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 7690 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 7691 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 7692 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 7693 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 7694 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 7695 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7696 do {\ 7697 HWIO_INTLOCK(); \ 7698 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 7699 HWIO_INTFREE();\ 7700 } while (0) 7701 7702 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7703 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7704 7705 //// Register REO_R1_SM_ALL_IDLE //// 7706 7707 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x0000202c) 7708 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x0000202c) 7709 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 7710 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 7711 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 7712 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 7713 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 7714 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 7715 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 7716 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 7717 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 7718 do {\ 7719 HWIO_INTLOCK(); \ 7720 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 7721 HWIO_INTFREE();\ 7722 } while (0) 7723 7724 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 7725 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 7726 7727 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 7728 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 7729 7730 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 7731 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 7732 7733 //// Register REO_R1_TESTBUS_CTRL //// 7734 7735 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002030) 7736 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002030) 7737 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 7738 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 7739 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 7740 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 7741 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 7742 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 7743 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 7744 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 7745 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 7746 do {\ 7747 HWIO_INTLOCK(); \ 7748 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 7749 HWIO_INTFREE();\ 7750 } while (0) 7751 7752 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 7753 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 7754 7755 //// Register REO_R1_TESTBUS_LOWER //// 7756 7757 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002034) 7758 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002034) 7759 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 7760 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 7761 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 7762 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 7763 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 7764 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 7765 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 7766 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 7767 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 7768 do {\ 7769 HWIO_INTLOCK(); \ 7770 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 7771 HWIO_INTFREE();\ 7772 } while (0) 7773 7774 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 7775 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 7776 7777 //// Register REO_R1_TESTBUS_HIGHER //// 7778 7779 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002038) 7780 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002038) 7781 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 7782 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 7783 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 7784 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 7785 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 7786 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 7787 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 7788 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 7789 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 7790 do {\ 7791 HWIO_INTLOCK(); \ 7792 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 7793 HWIO_INTFREE();\ 7794 } while (0) 7795 7796 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 7797 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 7798 7799 //// Register REO_R1_SM_STATES_IX_0 //// 7800 7801 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x0000203c) 7802 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x0000203c) 7803 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 7804 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 7805 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 7806 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 7807 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 7808 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 7809 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 7810 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 7811 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 7812 do {\ 7813 HWIO_INTLOCK(); \ 7814 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 7815 HWIO_INTFREE();\ 7816 } while (0) 7817 7818 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 7819 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 7820 7821 //// Register REO_R1_SM_STATES_IX_1 //// 7822 7823 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002040) 7824 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002040) 7825 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 7826 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 7827 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 7828 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 7829 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 7830 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 7831 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 7832 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 7833 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 7834 do {\ 7835 HWIO_INTLOCK(); \ 7836 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 7837 HWIO_INTFREE();\ 7838 } while (0) 7839 7840 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 7841 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 7842 7843 //// Register REO_R1_SM_STATES_IX_2 //// 7844 7845 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x00002044) 7846 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x00002044) 7847 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 7848 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 7849 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 7850 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 7851 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 7852 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 7853 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 7854 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 7855 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 7856 do {\ 7857 HWIO_INTLOCK(); \ 7858 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 7859 HWIO_INTFREE();\ 7860 } while (0) 7861 7862 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 7863 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 7864 7865 //// Register REO_R1_SM_STATES_IX_3 //// 7866 7867 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002048) 7868 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002048) 7869 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 7870 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 7871 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 7872 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 7873 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 7874 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 7875 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 7876 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 7877 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 7878 do {\ 7879 HWIO_INTLOCK(); \ 7880 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 7881 HWIO_INTFREE();\ 7882 } while (0) 7883 7884 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 7885 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 7886 7887 //// Register REO_R1_SM_STATES_IX_4 //// 7888 7889 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x0000204c) 7890 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x0000204c) 7891 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 7892 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 7893 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 7894 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 7895 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 7896 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 7897 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 7898 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 7899 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 7900 do {\ 7901 HWIO_INTLOCK(); \ 7902 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 7903 HWIO_INTFREE();\ 7904 } while (0) 7905 7906 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 7907 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 7908 7909 //// Register REO_R1_SM_STATES_IX_5 //// 7910 7911 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002050) 7912 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002050) 7913 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 7914 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 7915 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 7916 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 7917 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 7918 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 7919 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 7920 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 7921 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 7922 do {\ 7923 HWIO_INTLOCK(); \ 7924 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 7925 HWIO_INTFREE();\ 7926 } while (0) 7927 7928 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 7929 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 7930 7931 //// Register REO_R1_SM_STATES_IX_6 //// 7932 7933 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x00002054) 7934 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x00002054) 7935 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 7936 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 7937 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 7938 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 7939 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 7940 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 7941 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 7942 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 7943 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 7944 do {\ 7945 HWIO_INTLOCK(); \ 7946 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 7947 HWIO_INTFREE();\ 7948 } while (0) 7949 7950 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 7951 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 7952 7953 //// Register REO_R1_IDLE_STATES_IX_0 //// 7954 7955 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002058) 7956 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002058) 7957 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 7958 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 7959 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 7960 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 7961 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 7962 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 7963 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 7964 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 7965 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 7966 do {\ 7967 HWIO_INTLOCK(); \ 7968 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 7969 HWIO_INTFREE();\ 7970 } while (0) 7971 7972 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 7973 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 7974 7975 //// Register REO_R1_INVALID_APB_ACCESS //// 7976 7977 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x0000205c) 7978 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x0000205c) 7979 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 7980 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 7981 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 7982 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 7983 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 7984 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 7985 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 7986 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 7987 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 7988 do {\ 7989 HWIO_INTLOCK(); \ 7990 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 7991 HWIO_INTFREE();\ 7992 } while (0) 7993 7994 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 7995 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 7996 7997 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 7998 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 7999 8000 //// Register REO_R2_RXDMA2REO0_RING_HP //// 8001 8002 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 8003 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 8004 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 8005 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 8006 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 8007 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 8008 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 8009 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 8010 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 8011 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 8012 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 8013 do {\ 8014 HWIO_INTLOCK(); \ 8015 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 8016 HWIO_INTFREE();\ 8017 } while (0) 8018 8019 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8020 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 8021 8022 //// Register REO_R2_RXDMA2REO0_RING_TP //// 8023 8024 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 8025 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 8026 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 8027 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 8028 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 8029 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 8030 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 8031 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 8032 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 8033 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 8034 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 8035 do {\ 8036 HWIO_INTLOCK(); \ 8037 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 8038 HWIO_INTFREE();\ 8039 } while (0) 8040 8041 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8042 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 8043 8044 //// Register REO_R2_RXDMA2REO1_RING_HP //// 8045 8046 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x) (x+0x00003008) 8047 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x) (x+0x00003008) 8048 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK 0x0000ffff 8049 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT 0 8050 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ 8051 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) 8052 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ 8053 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) 8054 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ 8055 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) 8056 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ 8057 do {\ 8058 HWIO_INTLOCK(); \ 8059 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ 8060 HWIO_INTFREE();\ 8061 } while (0) 8062 8063 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8064 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 8065 8066 //// Register REO_R2_RXDMA2REO1_RING_TP //// 8067 8068 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x) (x+0x0000300c) 8069 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x) (x+0x0000300c) 8070 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK 0x0000ffff 8071 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT 0 8072 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ 8073 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) 8074 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ 8075 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) 8076 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ 8077 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) 8078 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ 8079 do {\ 8080 HWIO_INTLOCK(); \ 8081 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ 8082 HWIO_INTFREE();\ 8083 } while (0) 8084 8085 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8086 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 8087 8088 //// Register REO_R2_RXDMA2REO2_RING_HP //// 8089 8090 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x) (x+0x00003010) 8091 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x) (x+0x00003010) 8092 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK 0x0000ffff 8093 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT 0 8094 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ 8095 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) 8096 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ 8097 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) 8098 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ 8099 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) 8100 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ 8101 do {\ 8102 HWIO_INTLOCK(); \ 8103 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ 8104 HWIO_INTFREE();\ 8105 } while (0) 8106 8107 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8108 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 8109 8110 //// Register REO_R2_RXDMA2REO2_RING_TP //// 8111 8112 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x) (x+0x00003014) 8113 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x) (x+0x00003014) 8114 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK 0x0000ffff 8115 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT 0 8116 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ 8117 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) 8118 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ 8119 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) 8120 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ 8121 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) 8122 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ 8123 do {\ 8124 HWIO_INTLOCK(); \ 8125 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ 8126 HWIO_INTFREE();\ 8127 } while (0) 8128 8129 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8130 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 8131 8132 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 8133 8134 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003018) 8135 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003018) 8136 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 8137 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 8138 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 8139 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 8140 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 8141 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 8142 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 8143 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 8144 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 8145 do {\ 8146 HWIO_INTLOCK(); \ 8147 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 8148 HWIO_INTFREE();\ 8149 } while (0) 8150 8151 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8152 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 8153 8154 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 8155 8156 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000301c) 8157 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000301c) 8158 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 8159 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 8160 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 8161 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 8162 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 8163 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 8164 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 8165 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 8166 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 8167 do {\ 8168 HWIO_INTLOCK(); \ 8169 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 8170 HWIO_INTFREE();\ 8171 } while (0) 8172 8173 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8174 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 8175 8176 //// Register REO_R2_REO_CMD_RING_HP //// 8177 8178 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003020) 8179 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003020) 8180 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 8181 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 8182 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 8183 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 8184 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 8185 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 8186 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 8187 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 8188 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 8189 do {\ 8190 HWIO_INTLOCK(); \ 8191 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 8192 HWIO_INTFREE();\ 8193 } while (0) 8194 8195 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8196 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 8197 8198 //// Register REO_R2_REO_CMD_RING_TP //// 8199 8200 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003024) 8201 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003024) 8202 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 8203 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 8204 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 8205 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 8206 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 8207 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 8208 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 8209 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 8210 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 8211 do {\ 8212 HWIO_INTLOCK(); \ 8213 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 8214 HWIO_INTFREE();\ 8215 } while (0) 8216 8217 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8218 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 8219 8220 //// Register REO_R2_SW2REO_RING_HP //// 8221 8222 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003028) 8223 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003028) 8224 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 8225 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 8226 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 8227 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 8228 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 8229 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 8230 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 8231 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 8232 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 8233 do {\ 8234 HWIO_INTLOCK(); \ 8235 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 8236 HWIO_INTFREE();\ 8237 } while (0) 8238 8239 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8240 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 8241 8242 //// Register REO_R2_SW2REO_RING_TP //// 8243 8244 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000302c) 8245 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000302c) 8246 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 8247 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 8248 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 8249 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 8250 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 8251 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 8252 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 8253 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 8254 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 8255 do {\ 8256 HWIO_INTLOCK(); \ 8257 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 8258 HWIO_INTFREE();\ 8259 } while (0) 8260 8261 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8262 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 8263 8264 //// Register REO_R2_REO2SW1_RING_HP //// 8265 8266 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003030) 8267 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003030) 8268 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x0000ffff 8269 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 8270 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 8271 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 8272 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 8273 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 8274 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 8275 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 8276 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 8277 do {\ 8278 HWIO_INTLOCK(); \ 8279 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 8280 HWIO_INTFREE();\ 8281 } while (0) 8282 8283 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8284 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 8285 8286 //// Register REO_R2_REO2SW1_RING_TP //// 8287 8288 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x00003034) 8289 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x00003034) 8290 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x0000ffff 8291 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 8292 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 8293 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 8294 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 8295 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 8296 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 8297 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 8298 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 8299 do {\ 8300 HWIO_INTLOCK(); \ 8301 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 8302 HWIO_INTFREE();\ 8303 } while (0) 8304 8305 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8306 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 8307 8308 //// Register REO_R2_REO2SW2_RING_HP //// 8309 8310 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003038) 8311 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003038) 8312 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x0000ffff 8313 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 8314 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 8315 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 8316 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 8317 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 8318 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 8319 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 8320 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 8321 do {\ 8322 HWIO_INTLOCK(); \ 8323 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 8324 HWIO_INTFREE();\ 8325 } while (0) 8326 8327 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8328 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 8329 8330 //// Register REO_R2_REO2SW2_RING_TP //// 8331 8332 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x0000303c) 8333 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x0000303c) 8334 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x0000ffff 8335 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 8336 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 8337 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 8338 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 8339 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 8340 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 8341 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 8342 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 8343 do {\ 8344 HWIO_INTLOCK(); \ 8345 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 8346 HWIO_INTFREE();\ 8347 } while (0) 8348 8349 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8350 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 8351 8352 //// Register REO_R2_REO2SW3_RING_HP //// 8353 8354 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003040) 8355 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003040) 8356 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x0000ffff 8357 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 8358 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 8359 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 8360 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 8361 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 8362 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 8363 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 8364 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 8365 do {\ 8366 HWIO_INTLOCK(); \ 8367 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 8368 HWIO_INTFREE();\ 8369 } while (0) 8370 8371 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8372 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 8373 8374 //// Register REO_R2_REO2SW3_RING_TP //// 8375 8376 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x00003044) 8377 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x00003044) 8378 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x0000ffff 8379 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 8380 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 8381 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 8382 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 8383 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 8384 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 8385 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 8386 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 8387 do {\ 8388 HWIO_INTLOCK(); \ 8389 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 8390 HWIO_INTFREE();\ 8391 } while (0) 8392 8393 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8394 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 8395 8396 //// Register REO_R2_REO2SW4_RING_HP //// 8397 8398 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003048) 8399 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003048) 8400 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x0000ffff 8401 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 8402 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 8403 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 8404 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 8405 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 8406 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 8407 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 8408 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 8409 do {\ 8410 HWIO_INTLOCK(); \ 8411 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 8412 HWIO_INTFREE();\ 8413 } while (0) 8414 8415 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8416 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 8417 8418 //// Register REO_R2_REO2SW4_RING_TP //// 8419 8420 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x0000304c) 8421 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x0000304c) 8422 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x0000ffff 8423 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 8424 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 8425 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 8426 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 8427 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 8428 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 8429 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 8430 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 8431 do {\ 8432 HWIO_INTLOCK(); \ 8433 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 8434 HWIO_INTFREE();\ 8435 } while (0) 8436 8437 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8438 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 8439 8440 //// Register REO_R2_REO2TCL_RING_HP //// 8441 8442 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003050) 8443 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003050) 8444 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x0000ffff 8445 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 8446 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 8447 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 8448 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 8449 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 8450 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 8451 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 8452 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 8453 do {\ 8454 HWIO_INTLOCK(); \ 8455 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 8456 HWIO_INTFREE();\ 8457 } while (0) 8458 8459 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8460 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 8461 8462 //// Register REO_R2_REO2TCL_RING_TP //// 8463 8464 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x00003054) 8465 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x00003054) 8466 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x0000ffff 8467 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 8468 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 8469 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 8470 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 8471 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 8472 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 8473 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 8474 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 8475 do {\ 8476 HWIO_INTLOCK(); \ 8477 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 8478 HWIO_INTFREE();\ 8479 } while (0) 8480 8481 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8482 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 8483 8484 //// Register REO_R2_REO2FW_RING_HP //// 8485 8486 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003058) 8487 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003058) 8488 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x0000ffff 8489 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 8490 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 8491 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 8492 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 8493 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 8494 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 8495 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 8496 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 8497 do {\ 8498 HWIO_INTLOCK(); \ 8499 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 8500 HWIO_INTFREE();\ 8501 } while (0) 8502 8503 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8504 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 8505 8506 //// Register REO_R2_REO2FW_RING_TP //// 8507 8508 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x0000305c) 8509 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x0000305c) 8510 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x0000ffff 8511 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 8512 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 8513 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 8514 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 8515 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 8516 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 8517 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 8518 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 8519 do {\ 8520 HWIO_INTLOCK(); \ 8521 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 8522 HWIO_INTFREE();\ 8523 } while (0) 8524 8525 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8526 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 8527 8528 //// Register REO_R2_REO_RELEASE_RING_HP //// 8529 8530 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003060) 8531 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003060) 8532 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 8533 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 8534 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 8535 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 8536 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 8537 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 8538 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 8539 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 8540 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 8541 do {\ 8542 HWIO_INTLOCK(); \ 8543 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 8544 HWIO_INTFREE();\ 8545 } while (0) 8546 8547 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8548 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 8549 8550 //// Register REO_R2_REO_RELEASE_RING_TP //// 8551 8552 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003064) 8553 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003064) 8554 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 8555 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 8556 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 8557 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 8558 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 8559 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 8560 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 8561 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 8562 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 8563 do {\ 8564 HWIO_INTLOCK(); \ 8565 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 8566 HWIO_INTFREE();\ 8567 } while (0) 8568 8569 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8570 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 8571 8572 //// Register REO_R2_REO_STATUS_RING_HP //// 8573 8574 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003068) 8575 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003068) 8576 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 8577 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 8578 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 8579 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 8580 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 8581 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 8582 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 8583 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 8584 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 8585 do {\ 8586 HWIO_INTLOCK(); \ 8587 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 8588 HWIO_INTFREE();\ 8589 } while (0) 8590 8591 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8592 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 8593 8594 //// Register REO_R2_REO_STATUS_RING_TP //// 8595 8596 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x0000306c) 8597 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x0000306c) 8598 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 8599 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 8600 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 8601 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 8602 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 8603 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 8604 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 8605 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 8606 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 8607 do {\ 8608 HWIO_INTLOCK(); \ 8609 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 8610 HWIO_INTFREE();\ 8611 } while (0) 8612 8613 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8614 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 8615 8616 8617 #endif 8618 8619