1 /*
2  * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 // $ATH_LICENSE_HW_HDR_C$
20 //
21 // DO NOT EDIT!  This file is automatically generated
22 //               These definitions are tied to a particular hardware layout
23 
24 
25 #ifndef _REO_ENTRANCE_RING_H_
26 #define _REO_ENTRANCE_RING_H_
27 #if !defined(__ASSEMBLER__)
28 #endif
29 
30 #include "rx_mpdu_details.h"
31 
32 // ################ START SUMMARY #################
33 //
34 //	Dword	Fields
35 //	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
36 //	4	rx_reo_queue_desc_addr_31_0[31:0]
37 //	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
38 //	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7]
39 //	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
40 //
41 // ################ END SUMMARY #################
42 
43 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
44 
45 struct reo_entrance_ring {
46     struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
47              uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
48              uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
49                       rounded_mpdu_byte_count         : 14, //[21:8]
50                       reo_destination_indication      :  5, //[26:22]
51                       frameless_bar                   :  1, //[27]
52                       reserved_5a                     :  4; //[31:28]
53              uint32_t rxdma_push_reason               :  2, //[1:0]
54                       rxdma_error_code                :  5, //[6:2]
55                       reserved_6a                     : 25; //[31:7]
56              uint32_t reserved_7a                     : 20, //[19:0]
57                       ring_id                         :  8, //[27:20]
58                       looping_count                   :  4; //[31:28]
59 };
60 
61 /*
62 
63 struct rx_mpdu_details reo_level_mpdu_frame_info
64 
65 			Consumer: REO
66 
67 			Producer: RXDMA
68 
69 
70 
71 			Details related to the MPDU being pushed into the REO
72 
73 rx_reo_queue_desc_addr_31_0
74 
75 			Consumer: REO
76 
77 			Producer: RXDMA
78 
79 
80 
81 			Address (lower 32 bits) of the REO queue descriptor.
82 
83 			<legal all>
84 
85 rx_reo_queue_desc_addr_39_32
86 
87 			Consumer: REO
88 
89 			Producer: RXDMA
90 
91 
92 
93 			Address (upper 8 bits) of the REO queue descriptor.
94 
95 			<legal all>
96 
97 rounded_mpdu_byte_count
98 
99 			An approximation of the number of bytes received in this
100 			MPDU.
101 
102 			Used to keeps stats on the amount of data flowing
103 			through a queue.
104 
105 			<legal all>
106 
107 reo_destination_indication
108 
109 			RXDMA copy the MPDU's first MSDU's destination
110 			indication field here. This is used for REO to be able to
111 			re-route the packet to a different SW destination ring if
112 			the packet is detected as error in REO.
113 
114 
115 
116 			The ID of the REO exit ring where the MSDU frame shall
117 			push after (MPDU level) reordering has finished.
118 
119 
120 
121 			<enum 0 reo_destination_tcl> Reo will push the frame
122 			into the REO2TCL ring
123 
124 			<enum 1 reo_destination_sw1> Reo will push the frame
125 			into the REO2SW1 ring
126 
127 			<enum 2 reo_destination_sw2> Reo will push the frame
128 			into the REO2SW1 ring
129 
130 			<enum 3 reo_destination_sw3> Reo will push the frame
131 			into the REO2SW1 ring
132 
133 			<enum 4 reo_destination_sw4> Reo will push the frame
134 			into the REO2SW1 ring
135 
136 			<enum 5 reo_destination_release> Reo will push the frame
137 			into the REO_release ring
138 
139 			<enum 6 reo_destination_fw> Reo will push the frame into
140 			the REO2FW ring
141 
142 			<enum 7 reo_destination_7> REO remaps this
143 
144 			<enum 8 reo_destination_8> REO remaps this <enum 9
145 			reo_destination_9> REO remaps this <enum 10
146 			reo_destination_10> REO remaps this
147 
148 			<enum 11 reo_destination_11> REO remaps this
149 
150 			<enum 12 reo_destination_12> REO remaps this <enum 13
151 			reo_destination_13> REO remaps this
152 
153 			<enum 14 reo_destination_14> REO remaps this
154 
155 			<enum 15 reo_destination_15> REO remaps this
156 
157 			<enum 16 reo_destination_16> REO remaps this
158 
159 			<enum 17 reo_destination_17> REO remaps this
160 
161 			<enum 18 reo_destination_18> REO remaps this
162 
163 			<enum 19 reo_destination_19> REO remaps this
164 
165 			<enum 20 reo_destination_20> REO remaps this
166 
167 			<enum 21 reo_destination_21> REO remaps this
168 
169 			<enum 22 reo_destination_22> REO remaps this
170 
171 			<enum 23 reo_destination_23> REO remaps this
172 
173 			<enum 24 reo_destination_24> REO remaps this
174 
175 			<enum 25 reo_destination_25> REO remaps this
176 
177 			<enum 26 reo_destination_26> REO remaps this
178 
179 			<enum 27 reo_destination_27> REO remaps this
180 
181 			<enum 28 reo_destination_28> REO remaps this
182 
183 			<enum 29 reo_destination_29> REO remaps this
184 
185 			<enum 30 reo_destination_30> REO remaps this
186 
187 			<enum 31 reo_destination_31> REO remaps this
188 
189 
190 
191 			<legal all>
192 
193 frameless_bar
194 
195 			When set, this REO entrance ring struct contains BAR
196 			info from a multi TID BAR frame. The original multi TID BAR
197 			frame itself contained all the REO info for the first TID,
198 			but all the subsequent TID info and their linkage to the REO
199 			descriptors is passed down as 'frameless' BAR info.
200 
201 
202 
203 			The only fields valid in this descriptor when this bit
204 			is set are:
205 
206 			Rx_reo_queue_desc_addr_31_0
207 
208 			RX_reo_queue_desc_addr_39_32
209 
210 
211 
212 			And within the
213 
214 			Reo_level_mpdu_frame_info:
215 
216 			   Within Rx_mpdu_desc_info_details:
217 
218 			Mpdu_Sequence_number
219 
220 			BAR_frame
221 
222 			Peer_meta_data
223 
224 			All other fields shall be set to 0
225 
226 
227 
228 			<legal all>
229 
230 reserved_5a
231 
232 			<legal 0>
233 
234 rxdma_push_reason
235 
236 			Indicates why rxdma pushed the frame to this ring
237 
238 
239 
240 			<enum 0 rxdma_error_detected> RXDMA detected an error an
241 			pushed this frame to this queue
242 
243 			<enum 1 rxdma_routing_instruction> RXDMA pushed the
244 			frame to this queue per received routing instructions. No
245 			error within RXDMA was detected
246 
247 
248 
249 			This field is ignored by REO.
250 
251 			<legal 0 - 1>
252 
253 rxdma_error_code
254 
255 			Field only valid when 'rxdma_push_reason' set to
256 			'rxdma_error_detected'.
257 
258 
259 
260 			This field is ignored by REO.
261 
262 
263 
264 			<enum 0 rxdma_overflow_err>MPDU frame is not complete
265 			due to a FIFO overflow error in RXPCU.
266 
267 			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
268 			due to receiving incomplete MPDU from the PHY
269 
270 
271 			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
272 			error or CRYPTO received an encrypted frame, but did not get
273 			a valid corresponding key id in the peer entry.
274 
275 			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
276 			error
277 
278 			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
279 			unencrypted frame error when encrypted was expected
280 
281 			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
282 			length error
283 
284 			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
285 			number of MSDUs allowed in an MPDU got exceeded
286 
287 			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
288 			error
289 
290 			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
291 			parsing error
292 
293 			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
294 			during SA search
295 
296 			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
297 			during DA search
298 
299 			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
300 			timeout during flow search
301 
302 			<enum 13 Rxdma_flush_request>RXDMA received a flush
303 			request
304 
305 reserved_6a
306 
307 			<legal 0>
308 
309 reserved_7a
310 
311 			<legal 0>
312 
313 ring_id
314 
315 			Consumer: SW/REO/DEBUG
316 
317 			Producer: SRNG (of RXDMA)
318 
319 
320 
321 			For debugging.
322 
323 			This field is filled in by the SRNG module.
324 
325 			It help to identify the ring that is being looked <legal
326 			all>
327 
328 looping_count
329 
330 			Consumer: SW/REO/DEBUG
331 
332 			Producer: SRNG (of RXDMA)
333 
334 
335 
336 			For debugging.
337 
338 			This field is filled in by the SRNG module.
339 
340 
341 
342 			A count value that indicates the number of times the
343 			producer of entries into this Ring has looped around the
344 			ring.
345 
346 			At initialization time, this value is set to 0. On the
347 			first loop, this value is set to 1. After the max value is
348 			reached allowed by the number of bits for this field, the
349 			count value continues with 0 again.
350 
351 
352 
353 			In case SW is the consumer of the ring entries, it can
354 			use this field to figure out up to where the producer of
355 			entries has created new entries. This eliminates the need to
356 			check where the head pointer' of the ring is located once
357 			the SW starts processing an interrupt indicating that new
358 			entries have been put into this ring...
359 
360 
361 
362 			Also note that SW if it wants only needs to look at the
363 			LSB bit of this count value.
364 
365 			<legal all>
366 */
367 
368 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000
369 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
370 #define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
371 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004
372 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
373 #define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
374 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008
375 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
376 #define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
377 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c
378 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
379 #define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
380 
381 /* Description		REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
382 
383 			Consumer: REO
384 
385 			Producer: RXDMA
386 
387 
388 
389 			Address (lower 32 bits) of the REO queue descriptor.
390 
391 			<legal all>
392 */
393 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
394 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
395 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
396 
397 /* Description		REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
398 
399 			Consumer: REO
400 
401 			Producer: RXDMA
402 
403 
404 
405 			Address (upper 8 bits) of the REO queue descriptor.
406 
407 			<legal all>
408 */
409 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
410 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
411 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
412 
413 /* Description		REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
414 
415 			An approximation of the number of bytes received in this
416 			MPDU.
417 
418 			Used to keeps stats on the amount of data flowing
419 			through a queue.
420 
421 			<legal all>
422 */
423 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
424 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
425 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
426 
427 /* Description		REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
428 
429 			RXDMA copy the MPDU's first MSDU's destination
430 			indication field here. This is used for REO to be able to
431 			re-route the packet to a different SW destination ring if
432 			the packet is detected as error in REO.
433 
434 
435 
436 			The ID of the REO exit ring where the MSDU frame shall
437 			push after (MPDU level) reordering has finished.
438 
439 
440 
441 			<enum 0 reo_destination_tcl> Reo will push the frame
442 			into the REO2TCL ring
443 
444 			<enum 1 reo_destination_sw1> Reo will push the frame
445 			into the REO2SW1 ring
446 
447 			<enum 2 reo_destination_sw2> Reo will push the frame
448 			into the REO2SW1 ring
449 
450 			<enum 3 reo_destination_sw3> Reo will push the frame
451 			into the REO2SW1 ring
452 
453 			<enum 4 reo_destination_sw4> Reo will push the frame
454 			into the REO2SW1 ring
455 
456 			<enum 5 reo_destination_release> Reo will push the frame
457 			into the REO_release ring
458 
459 			<enum 6 reo_destination_fw> Reo will push the frame into
460 			the REO2FW ring
461 
462 			<enum 7 reo_destination_7> REO remaps this
463 
464 			<enum 8 reo_destination_8> REO remaps this <enum 9
465 			reo_destination_9> REO remaps this <enum 10
466 			reo_destination_10> REO remaps this
467 
468 			<enum 11 reo_destination_11> REO remaps this
469 
470 			<enum 12 reo_destination_12> REO remaps this <enum 13
471 			reo_destination_13> REO remaps this
472 
473 			<enum 14 reo_destination_14> REO remaps this
474 
475 			<enum 15 reo_destination_15> REO remaps this
476 
477 			<enum 16 reo_destination_16> REO remaps this
478 
479 			<enum 17 reo_destination_17> REO remaps this
480 
481 			<enum 18 reo_destination_18> REO remaps this
482 
483 			<enum 19 reo_destination_19> REO remaps this
484 
485 			<enum 20 reo_destination_20> REO remaps this
486 
487 			<enum 21 reo_destination_21> REO remaps this
488 
489 			<enum 22 reo_destination_22> REO remaps this
490 
491 			<enum 23 reo_destination_23> REO remaps this
492 
493 			<enum 24 reo_destination_24> REO remaps this
494 
495 			<enum 25 reo_destination_25> REO remaps this
496 
497 			<enum 26 reo_destination_26> REO remaps this
498 
499 			<enum 27 reo_destination_27> REO remaps this
500 
501 			<enum 28 reo_destination_28> REO remaps this
502 
503 			<enum 29 reo_destination_29> REO remaps this
504 
505 			<enum 30 reo_destination_30> REO remaps this
506 
507 			<enum 31 reo_destination_31> REO remaps this
508 
509 
510 
511 			<legal all>
512 */
513 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
514 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
515 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
516 
517 /* Description		REO_ENTRANCE_RING_5_FRAMELESS_BAR
518 
519 			When set, this REO entrance ring struct contains BAR
520 			info from a multi TID BAR frame. The original multi TID BAR
521 			frame itself contained all the REO info for the first TID,
522 			but all the subsequent TID info and their linkage to the REO
523 			descriptors is passed down as 'frameless' BAR info.
524 
525 
526 
527 			The only fields valid in this descriptor when this bit
528 			is set are:
529 
530 			Rx_reo_queue_desc_addr_31_0
531 
532 			RX_reo_queue_desc_addr_39_32
533 
534 
535 
536 			And within the
537 
538 			Reo_level_mpdu_frame_info:
539 
540 			   Within Rx_mpdu_desc_info_details:
541 
542 			Mpdu_Sequence_number
543 
544 			BAR_frame
545 
546 			Peer_meta_data
547 
548 			All other fields shall be set to 0
549 
550 
551 
552 			<legal all>
553 */
554 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
555 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
556 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
557 
558 /* Description		REO_ENTRANCE_RING_5_RESERVED_5A
559 
560 			<legal 0>
561 */
562 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
563 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
564 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
565 
566 /* Description		REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
567 
568 			Indicates why rxdma pushed the frame to this ring
569 
570 
571 
572 			<enum 0 rxdma_error_detected> RXDMA detected an error an
573 			pushed this frame to this queue
574 
575 			<enum 1 rxdma_routing_instruction> RXDMA pushed the
576 			frame to this queue per received routing instructions. No
577 			error within RXDMA was detected
578 
579 
580 
581 			This field is ignored by REO.
582 
583 			<legal 0 - 1>
584 */
585 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
586 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
587 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
588 
589 /* Description		REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
590 
591 			Field only valid when 'rxdma_push_reason' set to
592 			'rxdma_error_detected'.
593 
594 
595 
596 			This field is ignored by REO.
597 
598 
599 
600 			<enum 0 rxdma_overflow_err>MPDU frame is not complete
601 			due to a FIFO overflow error in RXPCU.
602 
603 			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
604 			due to receiving incomplete MPDU from the PHY
605 
606 
607 			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
608 			error or CRYPTO received an encrypted frame, but did not get
609 			a valid corresponding key id in the peer entry.
610 
611 			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
612 			error
613 
614 			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
615 			unencrypted frame error when encrypted was expected
616 
617 			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
618 			length error
619 
620 			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
621 			number of MSDUs allowed in an MPDU got exceeded
622 
623 			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
624 			error
625 
626 			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
627 			parsing error
628 
629 			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
630 			during SA search
631 
632 			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
633 			during DA search
634 
635 			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
636 			timeout during flow search
637 
638 			<enum 13 Rxdma_flush_request>RXDMA received a flush
639 			request
640 */
641 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
642 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
643 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
644 
645 /* Description		REO_ENTRANCE_RING_6_RESERVED_6A
646 
647 			<legal 0>
648 */
649 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
650 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          7
651 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xffffff80
652 
653 /* Description		REO_ENTRANCE_RING_7_RESERVED_7A
654 
655 			<legal 0>
656 */
657 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
658 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
659 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
660 
661 /* Description		REO_ENTRANCE_RING_7_RING_ID
662 
663 			Consumer: SW/REO/DEBUG
664 
665 			Producer: SRNG (of RXDMA)
666 
667 
668 
669 			For debugging.
670 
671 			This field is filled in by the SRNG module.
672 
673 			It help to identify the ring that is being looked <legal
674 			all>
675 */
676 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
677 #define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
678 #define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
679 
680 /* Description		REO_ENTRANCE_RING_7_LOOPING_COUNT
681 
682 			Consumer: SW/REO/DEBUG
683 
684 			Producer: SRNG (of RXDMA)
685 
686 
687 
688 			For debugging.
689 
690 			This field is filled in by the SRNG module.
691 
692 
693 
694 			A count value that indicates the number of times the
695 			producer of entries into this Ring has looped around the
696 			ring.
697 
698 			At initialization time, this value is set to 0. On the
699 			first loop, this value is set to 1. After the max value is
700 			reached allowed by the number of bits for this field, the
701 			count value continues with 0 again.
702 
703 
704 
705 			In case SW is the consumer of the ring entries, it can
706 			use this field to figure out up to where the producer of
707 			entries has created new entries. This eliminates the need to
708 			check where the head pointer' of the ring is located once
709 			the SW starts processing an interrupt indicating that new
710 			entries have been put into this ring...
711 
712 
713 
714 			Also note that SW if it wants only needs to look at the
715 			LSB bit of this count value.
716 
717 			<legal all>
718 */
719 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
720 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
721 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
722 
723 
724 #endif // _REO_ENTRANCE_RING_H_
725