1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 12/1/2017 22 // User Name:gunjans 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __REO_REG_SEQ_REG_H__ 29 #define __REO_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "reo_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block REO_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register REO_R0_GENERAL_ENABLE //// 45 46 #define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) 47 #define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) 48 #define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0x3fffffff 49 #define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 50 #define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ 51 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) 52 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ 53 in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 54 #define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ 55 out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) 56 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x20000000 64 #define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1d 65 66 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x10000000 67 #define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1c 68 69 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x0e000000 70 #define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x19 71 72 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK 0x01c00000 73 #define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT 0x16 74 75 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00200000 76 #define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x15 77 78 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00100000 79 #define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x14 80 81 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00080000 82 #define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x13 83 84 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00040000 85 #define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x12 86 87 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00020000 88 #define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x11 89 90 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00010000 91 #define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x10 92 93 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00008000 94 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0xf 95 96 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00004000 97 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xe 98 99 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00002000 100 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xd 101 102 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00001000 103 #define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xc 104 105 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000800 106 #define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xb 107 108 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000700 109 #define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x8 110 111 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000080 112 #define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x7 113 114 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070 115 #define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 116 117 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 118 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 119 120 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 121 #define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 122 123 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 124 #define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 125 126 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 127 #define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 128 129 //// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// 130 131 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) 132 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) 133 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffff00 134 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 8 135 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ 136 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) 137 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ 138 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 139 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ 140 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) 141 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ 142 do {\ 143 HWIO_INTLOCK(); \ 144 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ 145 HWIO_INTFREE();\ 146 } while (0) 147 148 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000 149 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1d 150 151 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000 152 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x1a 153 154 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000 155 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x17 156 157 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000 158 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x14 159 160 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000 161 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0x11 162 163 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000 164 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0xe 165 166 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800 167 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0xb 168 169 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700 170 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x8 171 172 //// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// 173 174 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) 175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) 176 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffff00 177 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 8 178 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ 179 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) 180 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ 181 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 182 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ 183 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) 184 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ 185 do {\ 186 HWIO_INTLOCK(); \ 187 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ 188 HWIO_INTFREE();\ 189 } while (0) 190 191 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000 192 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1d 193 194 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000 195 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x1a 196 197 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000 198 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x17 199 200 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000 201 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x14 202 203 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000 204 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0x11 205 206 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000 207 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0xe 208 209 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800 210 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0xb 211 212 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700 213 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x8 214 215 //// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// 216 217 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) 218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) 219 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffff00 220 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 8 221 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ 222 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) 223 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ 224 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 225 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ 226 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) 227 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ 228 do {\ 229 HWIO_INTLOCK(); \ 230 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ 231 HWIO_INTFREE();\ 232 } while (0) 233 234 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000 235 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1d 236 237 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000 238 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x1a 239 240 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000 241 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x17 242 243 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000 244 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x14 245 246 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000 247 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0x11 248 249 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000 250 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0xe 251 252 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800 253 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0xb 254 255 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700 256 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x8 257 258 //// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// 259 260 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) 261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) 262 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffff00 263 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 8 264 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ 265 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) 266 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ 267 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 268 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ 269 out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) 270 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ 271 do {\ 272 HWIO_INTLOCK(); \ 273 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ 274 HWIO_INTFREE();\ 275 } while (0) 276 277 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000 278 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1d 279 280 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000 281 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x1a 282 283 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000 284 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x17 285 286 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000 287 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x14 288 289 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000 290 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0x11 291 292 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000 293 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0xe 294 295 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800 296 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0xb 297 298 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700 299 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x8 300 301 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// 302 303 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) 304 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) 305 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffff00 306 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 8 307 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ 308 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) 309 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ 310 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 311 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ 312 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) 313 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ 314 do {\ 315 HWIO_INTLOCK(); \ 316 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ 317 HWIO_INTFREE();\ 318 } while (0) 319 320 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000 321 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1d 322 323 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000 324 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x1a 325 326 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000 327 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x17 328 329 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000 330 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x14 331 332 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000 333 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0x11 334 335 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000 336 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0xe 337 338 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800 339 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0xb 340 341 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700 342 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x8 343 344 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// 345 346 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) 347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) 348 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffff00 349 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 8 350 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ 351 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) 352 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ 353 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 354 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ 355 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) 356 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ 357 do {\ 358 HWIO_INTLOCK(); \ 359 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ 360 HWIO_INTFREE();\ 361 } while (0) 362 363 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000 364 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1d 365 366 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000 367 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x1a 368 369 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000 370 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x17 371 372 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000 373 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x14 374 375 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000 376 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0x11 377 378 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000 379 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0xe 380 381 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800 382 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0xb 383 384 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700 385 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x8 386 387 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// 388 389 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) 390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) 391 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffff00 392 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 8 393 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ 394 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) 395 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ 396 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 397 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ 398 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) 399 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ 400 do {\ 401 HWIO_INTLOCK(); \ 402 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ 403 HWIO_INTFREE();\ 404 } while (0) 405 406 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000 407 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1d 408 409 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000 410 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x1a 411 412 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000 413 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x17 414 415 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000 416 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x14 417 418 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000 419 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0x11 420 421 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000 422 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0xe 423 424 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800 425 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0xb 426 427 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700 428 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x8 429 430 //// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// 431 432 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) 433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) 434 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffff00 435 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 8 436 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ 437 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) 438 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ 439 in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 440 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ 441 out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) 442 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ 443 do {\ 444 HWIO_INTLOCK(); \ 445 out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ 446 HWIO_INTFREE();\ 447 } while (0) 448 449 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000 450 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1d 451 452 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000 453 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x1a 454 455 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000 456 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x17 457 458 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000 459 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x14 460 461 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000 462 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0x11 463 464 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000 465 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0xe 466 467 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800 468 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0xb 469 470 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700 471 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x8 472 473 //// Register REO_R0_TIMESTAMP //// 474 475 #define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) 476 #define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) 477 #define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff 478 #define HWIO_REO_R0_TIMESTAMP_SHFT 0 479 #define HWIO_REO_R0_TIMESTAMP_IN(x) \ 480 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) 481 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ 482 in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 483 #define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ 484 out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) 485 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ 486 do {\ 487 HWIO_INTLOCK(); \ 488 out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ 489 HWIO_INTFREE();\ 490 } while (0) 491 492 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff 493 #define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 494 495 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// 496 497 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) 498 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) 499 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x3fffffff 500 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 501 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ 502 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) 503 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ 504 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 505 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ 506 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) 507 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ 508 do {\ 509 HWIO_INTLOCK(); \ 510 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ 511 HWIO_INTFREE();\ 512 } while (0) 513 514 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000 515 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT 0x1b 516 517 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000 518 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT 0x18 519 520 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000 521 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x15 522 523 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000 524 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x12 525 526 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000 527 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0xf 528 529 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000 530 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0xc 531 532 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00 533 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0x9 534 535 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0 536 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x6 537 538 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038 539 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x3 540 541 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007 542 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 543 544 //// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// 545 546 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) 547 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) 548 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x0003ffff 549 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 550 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ 551 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) 552 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ 553 in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 554 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ 555 out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) 556 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ 557 do {\ 558 HWIO_INTLOCK(); \ 559 out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ 560 HWIO_INTFREE();\ 561 } while (0) 562 563 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000 564 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0xf 565 566 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000 567 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0xc 568 569 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00 570 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x9 571 572 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0 573 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x6 574 575 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038 576 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0x3 577 578 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007 579 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x0 580 581 //// Register REO_R0_IDLE_REQ_CTRL //// 582 583 #define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) 584 #define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) 585 #define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 586 #define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 587 #define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ 588 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) 589 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ 590 in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 591 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ 592 out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) 593 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ 594 do {\ 595 HWIO_INTLOCK(); \ 596 out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ 597 HWIO_INTFREE();\ 598 } while (0) 599 600 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 601 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 602 603 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 604 #define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 605 606 //// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// 607 608 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) 609 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) 610 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff 611 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 612 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ 613 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) 614 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ 615 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 616 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ 617 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) 618 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ 619 do {\ 620 HWIO_INTLOCK(); \ 621 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ 622 HWIO_INTFREE();\ 623 } while (0) 624 625 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 626 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 627 628 //// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// 629 630 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) 631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) 632 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff 633 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 634 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ 635 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) 636 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ 637 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 638 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ 639 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) 640 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ 641 do {\ 642 HWIO_INTLOCK(); \ 643 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ 644 HWIO_INTFREE();\ 645 } while (0) 646 647 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 648 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 649 650 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 651 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 652 653 //// Register REO_R0_RXDMA2REO0_RING_ID //// 654 655 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) 656 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) 657 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff 658 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 659 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ 660 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) 661 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ 662 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 663 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ 664 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) 665 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ 666 do {\ 667 HWIO_INTLOCK(); \ 668 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ 669 HWIO_INTFREE();\ 670 } while (0) 671 672 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 673 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 674 675 //// Register REO_R0_RXDMA2REO0_RING_STATUS //// 676 677 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) 678 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) 679 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff 680 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 681 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ 682 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) 683 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ 684 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 685 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ 686 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) 687 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ 688 do {\ 689 HWIO_INTLOCK(); \ 690 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ 691 HWIO_INTFREE();\ 692 } while (0) 693 694 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 695 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 696 697 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 698 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 699 700 //// Register REO_R0_RXDMA2REO0_RING_MISC //// 701 702 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) 703 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) 704 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff 705 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 706 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ 707 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) 708 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ 709 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 710 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ 711 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) 712 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ 713 do {\ 714 HWIO_INTLOCK(); \ 715 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ 716 HWIO_INTFREE();\ 717 } while (0) 718 719 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 720 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe 721 722 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 723 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 724 725 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 726 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 727 728 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 729 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 730 731 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 732 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 733 734 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 735 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 736 737 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 738 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 739 740 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 741 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 742 743 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 744 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 745 746 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 747 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 748 749 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 750 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 751 752 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// 753 754 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) 755 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) 756 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff 757 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 758 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ 759 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) 760 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ 761 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 762 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ 763 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) 764 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 765 do {\ 766 HWIO_INTLOCK(); \ 767 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ 768 HWIO_INTFREE();\ 769 } while (0) 770 771 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 772 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 773 774 //// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// 775 776 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) 777 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) 778 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff 779 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 780 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ 781 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) 782 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ 783 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 784 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ 785 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) 786 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 787 do {\ 788 HWIO_INTLOCK(); \ 789 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ 790 HWIO_INTFREE();\ 791 } while (0) 792 793 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 794 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 795 796 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// 797 798 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) 799 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) 800 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 801 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 802 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 803 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) 804 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 805 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 806 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 807 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 808 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 809 do {\ 810 HWIO_INTLOCK(); \ 811 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 812 HWIO_INTFREE();\ 813 } while (0) 814 815 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 816 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 817 818 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 819 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 820 821 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 822 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 823 824 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// 825 826 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) 827 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) 828 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 829 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 830 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 831 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) 832 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 833 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 834 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 835 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 836 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 837 do {\ 838 HWIO_INTLOCK(); \ 839 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 840 HWIO_INTFREE();\ 841 } while (0) 842 843 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 844 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 845 846 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// 847 848 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) 849 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) 850 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 851 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 852 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ 853 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) 854 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 855 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 856 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 857 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) 858 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 859 do {\ 860 HWIO_INTLOCK(); \ 861 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ 862 HWIO_INTFREE();\ 863 } while (0) 864 865 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 866 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 867 868 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 869 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 870 871 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 872 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 873 874 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// 875 876 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) 877 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) 878 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 879 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 880 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 881 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) 882 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 883 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 884 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 885 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 886 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 887 do {\ 888 HWIO_INTLOCK(); \ 889 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 890 HWIO_INTFREE();\ 891 } while (0) 892 893 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 894 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 895 896 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// 897 898 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) 899 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) 900 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 901 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 902 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 903 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) 904 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 905 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 906 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 907 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 908 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 909 do {\ 910 HWIO_INTLOCK(); \ 911 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 912 HWIO_INTFREE();\ 913 } while (0) 914 915 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 916 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 917 918 //// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// 919 920 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) 921 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) 922 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 923 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 924 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 925 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) 926 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 927 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 928 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 929 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 930 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 931 do {\ 932 HWIO_INTLOCK(); \ 933 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 934 HWIO_INTFREE();\ 935 } while (0) 936 937 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 938 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 939 940 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 941 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 942 943 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// 944 945 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) 946 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) 947 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff 948 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 949 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ 950 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) 951 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ 952 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 953 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ 954 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) 955 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 956 do {\ 957 HWIO_INTLOCK(); \ 958 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ 959 HWIO_INTFREE();\ 960 } while (0) 961 962 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 963 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 964 965 //// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// 966 967 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) 968 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) 969 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff 970 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 971 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ 972 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) 973 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ 974 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 975 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ 976 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) 977 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 978 do {\ 979 HWIO_INTLOCK(); \ 980 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ 981 HWIO_INTFREE();\ 982 } while (0) 983 984 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 985 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 986 987 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 988 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 989 990 //// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// 991 992 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) 993 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) 994 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff 995 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 996 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ 997 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) 998 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ 999 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 1000 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ 1001 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) 1002 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ 1003 do {\ 1004 HWIO_INTLOCK(); \ 1005 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ 1006 HWIO_INTFREE();\ 1007 } while (0) 1008 1009 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1010 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 1011 1012 //// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// 1013 1014 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) 1015 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) 1016 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1017 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 1018 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ 1019 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) 1020 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1021 in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1022 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1023 out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1024 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1025 do {\ 1026 HWIO_INTLOCK(); \ 1027 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ 1028 HWIO_INTFREE();\ 1029 } while (0) 1030 1031 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1032 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1033 1034 //// Register REO_R0_RXDMA2REO1_RING_BASE_LSB //// 1035 1036 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x) (x+0x0000008c) 1037 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x) (x+0x0000008c) 1038 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK 0xffffffff 1039 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT 0 1040 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x) \ 1041 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK) 1042 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ 1043 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) 1044 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val) \ 1045 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val) 1046 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ 1047 do {\ 1048 HWIO_INTLOCK(); \ 1049 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \ 1050 HWIO_INTFREE();\ 1051 } while (0) 1052 1053 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1054 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1055 1056 //// Register REO_R0_RXDMA2REO1_RING_BASE_MSB //// 1057 1058 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000090) 1059 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000090) 1060 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK 0x00ffffff 1061 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT 0 1062 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x) \ 1063 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK) 1064 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ 1065 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) 1066 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val) \ 1067 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val) 1068 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ 1069 do {\ 1070 HWIO_INTLOCK(); \ 1071 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \ 1072 HWIO_INTFREE();\ 1073 } while (0) 1074 1075 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1076 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1077 1078 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1079 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1080 1081 //// Register REO_R0_RXDMA2REO1_RING_ID //// 1082 1083 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x) (x+0x00000094) 1084 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x) (x+0x00000094) 1085 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK 0x000000ff 1086 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT 0 1087 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x) \ 1088 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK) 1089 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ 1090 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) 1091 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val) \ 1092 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val) 1093 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ 1094 do {\ 1095 HWIO_INTLOCK(); \ 1096 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \ 1097 HWIO_INTFREE();\ 1098 } while (0) 1099 1100 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1101 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 1102 1103 //// Register REO_R0_RXDMA2REO1_RING_STATUS //// 1104 1105 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x) (x+0x00000098) 1106 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x) (x+0x00000098) 1107 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK 0xffffffff 1108 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT 0 1109 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x) \ 1110 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK) 1111 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ 1112 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) 1113 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val) \ 1114 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val) 1115 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ 1116 do {\ 1117 HWIO_INTLOCK(); \ 1118 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \ 1119 HWIO_INTFREE();\ 1120 } while (0) 1121 1122 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1123 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1124 1125 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1126 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1127 1128 //// Register REO_R0_RXDMA2REO1_RING_MISC //// 1129 1130 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x) (x+0x0000009c) 1131 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x) (x+0x0000009c) 1132 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK 0x003fffff 1133 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT 0 1134 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x) \ 1135 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK) 1136 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ 1137 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) 1138 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val) \ 1139 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val) 1140 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ 1141 do {\ 1142 HWIO_INTLOCK(); \ 1143 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \ 1144 HWIO_INTFREE();\ 1145 } while (0) 1146 1147 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1148 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1149 1150 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1151 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1152 1153 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1154 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1155 1156 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1157 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1158 1159 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1160 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1161 1162 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1163 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1164 1165 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1166 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1167 1168 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1169 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1170 1171 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1172 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 1173 1174 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1175 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1176 1177 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1178 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1179 1180 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB //// 1181 1182 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) 1183 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) 1184 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1185 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT 0 1186 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x) \ 1187 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK) 1188 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ 1189 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 1190 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ 1191 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val) 1192 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1193 do {\ 1194 HWIO_INTLOCK(); \ 1195 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \ 1196 HWIO_INTFREE();\ 1197 } while (0) 1198 1199 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1200 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1201 1202 //// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB //// 1203 1204 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) 1205 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) 1206 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1207 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT 0 1208 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x) \ 1209 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK) 1210 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ 1211 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 1212 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ 1213 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val) 1214 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1215 do {\ 1216 HWIO_INTLOCK(); \ 1217 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \ 1218 HWIO_INTFREE();\ 1219 } while (0) 1220 1221 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1222 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1223 1224 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 //// 1225 1226 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) 1227 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) 1228 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1229 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1230 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1231 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1232 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1233 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1234 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1235 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1236 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1237 do {\ 1238 HWIO_INTLOCK(); \ 1239 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1240 HWIO_INTFREE();\ 1241 } while (0) 1242 1243 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1244 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1245 1246 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1247 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1248 1249 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1250 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1251 1252 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 //// 1253 1254 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) 1255 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) 1256 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1257 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1258 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1259 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1260 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1261 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1262 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1263 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1264 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1265 do {\ 1266 HWIO_INTLOCK(); \ 1267 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1268 HWIO_INTFREE();\ 1269 } while (0) 1270 1271 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1272 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1273 1274 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS //// 1275 1276 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) 1277 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) 1278 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1279 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 1280 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ 1281 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK) 1282 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1283 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1284 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1285 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1286 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1287 do {\ 1288 HWIO_INTLOCK(); \ 1289 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1290 HWIO_INTFREE();\ 1291 } while (0) 1292 1293 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1294 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1295 1296 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1297 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1298 1299 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1300 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1301 1302 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER //// 1303 1304 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) 1305 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) 1306 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1307 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1308 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1309 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1310 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1311 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1312 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1313 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1314 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1315 do {\ 1316 HWIO_INTLOCK(); \ 1317 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1318 HWIO_INTFREE();\ 1319 } while (0) 1320 1321 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1322 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1323 1324 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER //// 1325 1326 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) 1327 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) 1328 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1329 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1330 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1331 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1332 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1333 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1334 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1335 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1336 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1337 do {\ 1338 HWIO_INTLOCK(); \ 1339 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1340 HWIO_INTFREE();\ 1341 } while (0) 1342 1343 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1344 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1345 1346 //// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS //// 1347 1348 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) 1349 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) 1350 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1351 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1352 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1353 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1354 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1355 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1356 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1357 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1358 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1359 do {\ 1360 HWIO_INTLOCK(); \ 1361 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1362 HWIO_INTFREE();\ 1363 } while (0) 1364 1365 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1366 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1367 1368 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1369 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1370 1371 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB //// 1372 1373 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) 1374 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) 1375 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1376 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT 0 1377 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x) \ 1378 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK) 1379 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1380 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1381 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1382 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) 1383 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1384 do {\ 1385 HWIO_INTLOCK(); \ 1386 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \ 1387 HWIO_INTFREE();\ 1388 } while (0) 1389 1390 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1391 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1392 1393 //// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB //// 1394 1395 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) 1396 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) 1397 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1398 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT 0 1399 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x) \ 1400 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK) 1401 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1402 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1403 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1404 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) 1405 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1406 do {\ 1407 HWIO_INTLOCK(); \ 1408 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \ 1409 HWIO_INTFREE();\ 1410 } while (0) 1411 1412 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1413 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1414 1415 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1416 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1417 1418 //// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA //// 1419 1420 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) 1421 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) 1422 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK 0xffffffff 1423 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT 0 1424 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x) \ 1425 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK) 1426 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ 1427 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) 1428 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val) \ 1429 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val) 1430 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1431 do {\ 1432 HWIO_INTLOCK(); \ 1433 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \ 1434 HWIO_INTFREE();\ 1435 } while (0) 1436 1437 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1438 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 1439 1440 //// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET //// 1441 1442 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) 1443 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) 1444 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1445 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 1446 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ 1447 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK) 1448 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1449 in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1450 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1451 out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1452 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1453 do {\ 1454 HWIO_INTLOCK(); \ 1455 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1456 HWIO_INTFREE();\ 1457 } while (0) 1458 1459 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1460 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1461 1462 //// Register REO_R0_RXDMA2REO2_RING_BASE_LSB //// 1463 1464 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x) (x+0x000000e4) 1465 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x) (x+0x000000e4) 1466 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK 0xffffffff 1467 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT 0 1468 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x) \ 1469 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK) 1470 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ 1471 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) 1472 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val) \ 1473 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val) 1474 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ 1475 do {\ 1476 HWIO_INTLOCK(); \ 1477 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \ 1478 HWIO_INTFREE();\ 1479 } while (0) 1480 1481 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1482 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1483 1484 //// Register REO_R0_RXDMA2REO2_RING_BASE_MSB //// 1485 1486 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x) (x+0x000000e8) 1487 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x) (x+0x000000e8) 1488 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK 0x00ffffff 1489 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT 0 1490 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x) \ 1491 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK) 1492 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ 1493 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) 1494 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val) \ 1495 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val) 1496 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ 1497 do {\ 1498 HWIO_INTLOCK(); \ 1499 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \ 1500 HWIO_INTFREE();\ 1501 } while (0) 1502 1503 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1504 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1505 1506 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1507 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1508 1509 //// Register REO_R0_RXDMA2REO2_RING_ID //// 1510 1511 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x) (x+0x000000ec) 1512 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x) (x+0x000000ec) 1513 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK 0x000000ff 1514 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT 0 1515 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x) \ 1516 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK) 1517 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ 1518 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) 1519 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val) \ 1520 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val) 1521 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ 1522 do {\ 1523 HWIO_INTLOCK(); \ 1524 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \ 1525 HWIO_INTFREE();\ 1526 } while (0) 1527 1528 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1529 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT 0x0 1530 1531 //// Register REO_R0_RXDMA2REO2_RING_STATUS //// 1532 1533 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x) (x+0x000000f0) 1534 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x) (x+0x000000f0) 1535 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK 0xffffffff 1536 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT 0 1537 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x) \ 1538 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK) 1539 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ 1540 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) 1541 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val) \ 1542 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val) 1543 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ 1544 do {\ 1545 HWIO_INTLOCK(); \ 1546 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \ 1547 HWIO_INTFREE();\ 1548 } while (0) 1549 1550 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1551 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1552 1553 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1554 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1555 1556 //// Register REO_R0_RXDMA2REO2_RING_MISC //// 1557 1558 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x) (x+0x000000f4) 1559 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x) (x+0x000000f4) 1560 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK 0x003fffff 1561 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT 0 1562 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x) \ 1563 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK) 1564 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ 1565 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) 1566 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val) \ 1567 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val) 1568 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ 1569 do {\ 1570 HWIO_INTLOCK(); \ 1571 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \ 1572 HWIO_INTFREE();\ 1573 } while (0) 1574 1575 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1576 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1577 1578 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1579 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1580 1581 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1582 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1583 1584 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1585 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1586 1587 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1588 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1589 1590 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1591 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1592 1593 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1594 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1595 1596 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1597 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1598 1599 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1600 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT 0x2 1601 1602 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1603 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1604 1605 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1606 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1607 1608 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB //// 1609 1610 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) 1611 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) 1612 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1613 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT 0 1614 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x) \ 1615 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK) 1616 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ 1617 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) 1618 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val) \ 1619 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val) 1620 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1621 do {\ 1622 HWIO_INTLOCK(); \ 1623 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \ 1624 HWIO_INTFREE();\ 1625 } while (0) 1626 1627 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1628 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1629 1630 //// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB //// 1631 1632 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) 1633 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) 1634 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1635 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT 0 1636 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x) \ 1637 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK) 1638 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ 1639 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) 1640 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val) \ 1641 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val) 1642 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1643 do {\ 1644 HWIO_INTLOCK(); \ 1645 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \ 1646 HWIO_INTFREE();\ 1647 } while (0) 1648 1649 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1650 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1651 1652 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 //// 1653 1654 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) 1655 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) 1656 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1657 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1658 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1659 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1660 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1661 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1662 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1663 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1664 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1665 do {\ 1666 HWIO_INTLOCK(); \ 1667 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1668 HWIO_INTFREE();\ 1669 } while (0) 1670 1671 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1672 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1673 1674 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1675 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1676 1677 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1678 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1679 1680 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 //// 1681 1682 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) 1683 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) 1684 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1685 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1686 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1687 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1688 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1689 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1690 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1691 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1692 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1693 do {\ 1694 HWIO_INTLOCK(); \ 1695 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1696 HWIO_INTFREE();\ 1697 } while (0) 1698 1699 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1700 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1701 1702 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS //// 1703 1704 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) 1705 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) 1706 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1707 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT 0 1708 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x) \ 1709 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK) 1710 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1711 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1712 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1713 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1714 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1715 do {\ 1716 HWIO_INTLOCK(); \ 1717 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1718 HWIO_INTFREE();\ 1719 } while (0) 1720 1721 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1722 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1723 1724 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1725 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1726 1727 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1728 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1729 1730 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER //// 1731 1732 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) 1733 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) 1734 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1735 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1736 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1737 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1738 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1739 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1740 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1741 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1742 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1743 do {\ 1744 HWIO_INTLOCK(); \ 1745 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1746 HWIO_INTFREE();\ 1747 } while (0) 1748 1749 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1750 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1751 1752 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER //// 1753 1754 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) 1755 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) 1756 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1757 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1758 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1759 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1760 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1761 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1762 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1763 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1764 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1765 do {\ 1766 HWIO_INTLOCK(); \ 1767 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1768 HWIO_INTFREE();\ 1769 } while (0) 1770 1771 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1772 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1773 1774 //// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS //// 1775 1776 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) 1777 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) 1778 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1779 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1780 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1781 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1782 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1783 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1784 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1785 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1786 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1787 do {\ 1788 HWIO_INTLOCK(); \ 1789 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1790 HWIO_INTFREE();\ 1791 } while (0) 1792 1793 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1794 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1795 1796 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1797 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1798 1799 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB //// 1800 1801 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) 1802 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) 1803 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1804 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT 0 1805 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x) \ 1806 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK) 1807 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1808 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1809 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1810 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val) 1811 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1812 do {\ 1813 HWIO_INTLOCK(); \ 1814 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \ 1815 HWIO_INTFREE();\ 1816 } while (0) 1817 1818 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1819 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1820 1821 //// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB //// 1822 1823 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) 1824 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) 1825 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1826 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT 0 1827 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x) \ 1828 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK) 1829 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1830 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1831 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1832 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val) 1833 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1834 do {\ 1835 HWIO_INTLOCK(); \ 1836 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \ 1837 HWIO_INTFREE();\ 1838 } while (0) 1839 1840 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1841 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1842 1843 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1844 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1845 1846 //// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA //// 1847 1848 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x) (x+0x00000134) 1849 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x) (x+0x00000134) 1850 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK 0xffffffff 1851 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT 0 1852 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x) \ 1853 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK) 1854 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ 1855 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) 1856 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val) \ 1857 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val) 1858 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1859 do {\ 1860 HWIO_INTLOCK(); \ 1861 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \ 1862 HWIO_INTFREE();\ 1863 } while (0) 1864 1865 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1866 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT 0x0 1867 1868 //// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET //// 1869 1870 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) 1871 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) 1872 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1873 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT 0 1874 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x) \ 1875 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK) 1876 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1877 in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1878 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1879 out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1880 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1881 do {\ 1882 HWIO_INTLOCK(); \ 1883 out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1884 HWIO_INTFREE();\ 1885 } while (0) 1886 1887 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1888 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1889 1890 //// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// 1891 1892 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000013c) 1893 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000013c) 1894 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff 1895 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 1896 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ 1897 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) 1898 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ 1899 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 1900 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ 1901 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) 1902 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ 1903 do {\ 1904 HWIO_INTLOCK(); \ 1905 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ 1906 HWIO_INTFREE();\ 1907 } while (0) 1908 1909 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1910 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1911 1912 //// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// 1913 1914 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000140) 1915 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000140) 1916 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff 1917 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 1918 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ 1919 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) 1920 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ 1921 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 1922 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ 1923 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) 1924 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ 1925 do {\ 1926 HWIO_INTLOCK(); \ 1927 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ 1928 HWIO_INTFREE();\ 1929 } while (0) 1930 1931 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1932 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1933 1934 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1935 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1936 1937 //// Register REO_R0_WBM2REO_LINK_RING_ID //// 1938 1939 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000144) 1940 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000144) 1941 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff 1942 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 1943 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ 1944 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) 1945 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ 1946 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 1947 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ 1948 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) 1949 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ 1950 do {\ 1951 HWIO_INTLOCK(); \ 1952 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ 1953 HWIO_INTFREE();\ 1954 } while (0) 1955 1956 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1957 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 1958 1959 //// Register REO_R0_WBM2REO_LINK_RING_STATUS //// 1960 1961 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000148) 1962 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000148) 1963 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff 1964 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 1965 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ 1966 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) 1967 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ 1968 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 1969 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ 1970 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) 1971 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ 1972 do {\ 1973 HWIO_INTLOCK(); \ 1974 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ 1975 HWIO_INTFREE();\ 1976 } while (0) 1977 1978 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1979 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1980 1981 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1982 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1983 1984 //// Register REO_R0_WBM2REO_LINK_RING_MISC //// 1985 1986 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000014c) 1987 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000014c) 1988 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff 1989 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 1990 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ 1991 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) 1992 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ 1993 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 1994 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ 1995 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) 1996 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ 1997 do {\ 1998 HWIO_INTLOCK(); \ 1999 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ 2000 HWIO_INTFREE();\ 2001 } while (0) 2002 2003 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2004 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe 2005 2006 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2007 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2008 2009 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2010 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2011 2012 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2013 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2014 2015 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2016 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 2017 2018 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2019 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2020 2021 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2022 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2023 2024 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2025 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2026 2027 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2028 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 2029 2030 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2031 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2032 2033 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2034 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2035 2036 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// 2037 2038 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) 2039 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) 2040 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff 2041 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 2042 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ 2043 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) 2044 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ 2045 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 2046 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ 2047 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) 2048 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2049 do {\ 2050 HWIO_INTLOCK(); \ 2051 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ 2052 HWIO_INTFREE();\ 2053 } while (0) 2054 2055 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2056 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2057 2058 //// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// 2059 2060 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) 2061 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) 2062 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff 2063 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 2064 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ 2065 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) 2066 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ 2067 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 2068 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ 2069 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) 2070 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2071 do {\ 2072 HWIO_INTLOCK(); \ 2073 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ 2074 HWIO_INTFREE();\ 2075 } while (0) 2076 2077 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2078 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2079 2080 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// 2081 2082 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) 2083 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) 2084 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2085 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2086 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2087 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2088 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2089 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2090 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2091 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2092 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2093 do {\ 2094 HWIO_INTLOCK(); \ 2095 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2096 HWIO_INTFREE();\ 2097 } while (0) 2098 2099 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2100 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2101 2102 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2103 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2104 2105 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2106 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2107 2108 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// 2109 2110 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) 2111 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) 2112 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2113 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2114 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2115 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2116 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2117 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2118 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2119 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2120 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2121 do {\ 2122 HWIO_INTLOCK(); \ 2123 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2124 HWIO_INTFREE();\ 2125 } while (0) 2126 2127 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2128 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2129 2130 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// 2131 2132 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) 2133 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) 2134 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2135 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 2136 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ 2137 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) 2138 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2139 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2140 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2141 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2142 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2143 do {\ 2144 HWIO_INTLOCK(); \ 2145 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ 2146 HWIO_INTFREE();\ 2147 } while (0) 2148 2149 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2150 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2151 2152 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2153 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2154 2155 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2156 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2157 2158 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// 2159 2160 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) 2161 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) 2162 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2163 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2164 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2165 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2166 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2167 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2168 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2169 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2170 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2171 do {\ 2172 HWIO_INTLOCK(); \ 2173 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2174 HWIO_INTFREE();\ 2175 } while (0) 2176 2177 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2178 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2179 2180 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// 2181 2182 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) 2183 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) 2184 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2185 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2186 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2187 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2188 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2189 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2190 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2191 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2192 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2193 do {\ 2194 HWIO_INTLOCK(); \ 2195 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2196 HWIO_INTFREE();\ 2197 } while (0) 2198 2199 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2200 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2201 2202 //// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// 2203 2204 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) 2205 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) 2206 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2207 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2208 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2209 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2210 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2211 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2212 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2213 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2214 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2215 do {\ 2216 HWIO_INTLOCK(); \ 2217 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2218 HWIO_INTFREE();\ 2219 } while (0) 2220 2221 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2222 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2223 2224 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2225 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2226 2227 //// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// 2228 2229 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) 2230 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) 2231 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2232 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 2233 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ 2234 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) 2235 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2236 in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2237 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2238 out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2239 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2240 do {\ 2241 HWIO_INTLOCK(); \ 2242 out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ 2243 HWIO_INTFREE();\ 2244 } while (0) 2245 2246 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2247 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2248 2249 //// Register REO_R0_REO_CMD_RING_BASE_LSB //// 2250 2251 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000194) 2252 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000194) 2253 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff 2254 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 2255 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ 2256 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) 2257 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ 2258 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 2259 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ 2260 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) 2261 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2262 do {\ 2263 HWIO_INTLOCK(); \ 2264 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ 2265 HWIO_INTFREE();\ 2266 } while (0) 2267 2268 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2269 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2270 2271 //// Register REO_R0_REO_CMD_RING_BASE_MSB //// 2272 2273 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000198) 2274 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000198) 2275 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff 2276 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 2277 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ 2278 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) 2279 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ 2280 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 2281 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ 2282 out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) 2283 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2284 do {\ 2285 HWIO_INTLOCK(); \ 2286 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ 2287 HWIO_INTFREE();\ 2288 } while (0) 2289 2290 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2291 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2292 2293 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2294 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2295 2296 //// Register REO_R0_REO_CMD_RING_ID //// 2297 2298 #define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x0000019c) 2299 #define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x0000019c) 2300 #define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff 2301 #define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 2302 #define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ 2303 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) 2304 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ 2305 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 2306 #define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ 2307 out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) 2308 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ 2309 do {\ 2310 HWIO_INTLOCK(); \ 2311 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ 2312 HWIO_INTFREE();\ 2313 } while (0) 2314 2315 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2316 #define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2317 2318 //// Register REO_R0_REO_CMD_RING_STATUS //// 2319 2320 #define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000001a0) 2321 #define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000001a0) 2322 #define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff 2323 #define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 2324 #define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ 2325 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) 2326 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ 2327 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 2328 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ 2329 out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) 2330 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ 2331 do {\ 2332 HWIO_INTLOCK(); \ 2333 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ 2334 HWIO_INTFREE();\ 2335 } while (0) 2336 2337 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2338 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2339 2340 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2341 #define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2342 2343 //// Register REO_R0_REO_CMD_RING_MISC //// 2344 2345 #define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000001a4) 2346 #define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000001a4) 2347 #define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff 2348 #define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 2349 #define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ 2350 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) 2351 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ 2352 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 2353 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ 2354 out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) 2355 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ 2356 do {\ 2357 HWIO_INTLOCK(); \ 2358 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ 2359 HWIO_INTFREE();\ 2360 } while (0) 2361 2362 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2363 #define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 2364 2365 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2366 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2367 2368 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2369 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2370 2371 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2372 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2373 2374 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2375 #define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 2376 2377 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2378 #define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2379 2380 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2381 #define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2382 2383 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2384 #define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2385 2386 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2387 #define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2388 2389 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2390 #define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2391 2392 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2393 #define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2394 2395 //// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// 2396 2397 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) 2398 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) 2399 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2400 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 2401 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ 2402 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) 2403 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2404 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2405 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2406 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2407 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2408 do {\ 2409 HWIO_INTLOCK(); \ 2410 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2411 HWIO_INTFREE();\ 2412 } while (0) 2413 2414 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2415 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2416 2417 //// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// 2418 2419 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) 2420 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) 2421 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2422 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 2423 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ 2424 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) 2425 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2426 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2427 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2428 out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2429 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2430 do {\ 2431 HWIO_INTLOCK(); \ 2432 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2433 HWIO_INTFREE();\ 2434 } while (0) 2435 2436 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2437 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2438 2439 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2440 2441 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) 2442 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) 2443 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2444 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2445 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2446 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2447 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2448 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2449 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2450 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2451 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2452 do {\ 2453 HWIO_INTLOCK(); \ 2454 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2455 HWIO_INTFREE();\ 2456 } while (0) 2457 2458 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2459 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2460 2461 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2462 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2463 2464 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2465 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2466 2467 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2468 2469 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) 2470 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) 2471 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2472 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2473 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2474 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2475 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2476 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2477 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2478 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2479 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2480 do {\ 2481 HWIO_INTLOCK(); \ 2482 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2483 HWIO_INTFREE();\ 2484 } while (0) 2485 2486 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2487 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2488 2489 //// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// 2490 2491 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) 2492 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) 2493 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2494 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2495 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2496 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2497 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2498 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2499 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2500 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2501 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2502 do {\ 2503 HWIO_INTLOCK(); \ 2504 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2505 HWIO_INTFREE();\ 2506 } while (0) 2507 2508 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2509 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2510 2511 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2512 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2513 2514 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2515 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2516 2517 //// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2518 2519 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) 2520 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) 2521 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2522 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2523 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2524 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2525 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2526 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2527 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2528 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2529 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2530 do {\ 2531 HWIO_INTLOCK(); \ 2532 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2533 HWIO_INTFREE();\ 2534 } while (0) 2535 2536 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2537 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2538 2539 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2540 2541 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) 2542 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) 2543 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2544 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2545 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2546 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2547 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2548 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2549 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2550 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2551 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2552 do {\ 2553 HWIO_INTLOCK(); \ 2554 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2555 HWIO_INTFREE();\ 2556 } while (0) 2557 2558 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2559 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2560 2561 //// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2562 2563 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) 2564 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) 2565 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2566 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2567 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2568 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2569 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2570 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2571 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2572 out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2573 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2574 do {\ 2575 HWIO_INTLOCK(); \ 2576 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2577 HWIO_INTFREE();\ 2578 } while (0) 2579 2580 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2581 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2582 2583 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2584 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2585 2586 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// 2587 2588 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) 2589 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) 2590 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2591 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 2592 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2593 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) 2594 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2595 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2596 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2597 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2598 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2599 do {\ 2600 HWIO_INTLOCK(); \ 2601 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2602 HWIO_INTFREE();\ 2603 } while (0) 2604 2605 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2606 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2607 2608 //// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// 2609 2610 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) 2611 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) 2612 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2613 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 2614 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2615 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) 2616 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2617 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2618 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2619 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2620 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2621 do {\ 2622 HWIO_INTLOCK(); \ 2623 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2624 HWIO_INTFREE();\ 2625 } while (0) 2626 2627 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2628 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2629 2630 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2631 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2632 2633 //// Register REO_R0_REO_CMD_RING_MSI1_DATA //// 2634 2635 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) 2636 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) 2637 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2638 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 2639 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ 2640 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) 2641 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ 2642 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 2643 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ 2644 out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) 2645 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2646 do {\ 2647 HWIO_INTLOCK(); \ 2648 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ 2649 HWIO_INTFREE();\ 2650 } while (0) 2651 2652 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2653 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2654 2655 //// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// 2656 2657 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) 2658 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) 2659 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2660 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2661 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2662 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2663 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2664 in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2665 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2666 out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2667 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2668 do {\ 2669 HWIO_INTLOCK(); \ 2670 out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2671 HWIO_INTFREE();\ 2672 } while (0) 2673 2674 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2675 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2676 2677 //// Register REO_R0_SW2REO_RING_BASE_LSB //// 2678 2679 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x000001ec) 2680 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x000001ec) 2681 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff 2682 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 2683 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ 2684 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) 2685 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ 2686 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 2687 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ 2688 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) 2689 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ 2690 do {\ 2691 HWIO_INTLOCK(); \ 2692 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ 2693 HWIO_INTFREE();\ 2694 } while (0) 2695 2696 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2697 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2698 2699 //// Register REO_R0_SW2REO_RING_BASE_MSB //// 2700 2701 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x000001f0) 2702 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x000001f0) 2703 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff 2704 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 2705 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ 2706 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) 2707 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ 2708 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 2709 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ 2710 out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) 2711 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ 2712 do {\ 2713 HWIO_INTLOCK(); \ 2714 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ 2715 HWIO_INTFREE();\ 2716 } while (0) 2717 2718 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2719 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2720 2721 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2722 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2723 2724 //// Register REO_R0_SW2REO_RING_ID //// 2725 2726 #define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x000001f4) 2727 #define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x000001f4) 2728 #define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff 2729 #define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 2730 #define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ 2731 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) 2732 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ 2733 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 2734 #define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ 2735 out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) 2736 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ 2737 do {\ 2738 HWIO_INTLOCK(); \ 2739 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ 2740 HWIO_INTFREE();\ 2741 } while (0) 2742 2743 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2744 #define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 2745 2746 //// Register REO_R0_SW2REO_RING_STATUS //// 2747 2748 #define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x000001f8) 2749 #define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x000001f8) 2750 #define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff 2751 #define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 2752 #define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ 2753 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) 2754 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ 2755 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 2756 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ 2757 out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) 2758 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ 2759 do {\ 2760 HWIO_INTLOCK(); \ 2761 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ 2762 HWIO_INTFREE();\ 2763 } while (0) 2764 2765 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2766 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2767 2768 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2769 #define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2770 2771 //// Register REO_R0_SW2REO_RING_MISC //// 2772 2773 #define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x000001fc) 2774 #define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x000001fc) 2775 #define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff 2776 #define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 2777 #define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ 2778 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) 2779 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ 2780 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 2781 #define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ 2782 out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) 2783 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ 2784 do {\ 2785 HWIO_INTLOCK(); \ 2786 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ 2787 HWIO_INTFREE();\ 2788 } while (0) 2789 2790 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2791 #define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe 2792 2793 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2794 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2795 2796 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2797 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2798 2799 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2800 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2801 2802 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2803 #define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 2804 2805 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2806 #define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2807 2808 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2809 #define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2810 2811 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2812 #define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2813 2814 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2815 #define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 2816 2817 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2818 #define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2819 2820 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2821 #define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2822 2823 //// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// 2824 2825 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) 2826 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) 2827 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff 2828 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 2829 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ 2830 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) 2831 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ 2832 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 2833 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ 2834 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) 2835 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2836 do {\ 2837 HWIO_INTLOCK(); \ 2838 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ 2839 HWIO_INTFREE();\ 2840 } while (0) 2841 2842 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2843 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2844 2845 //// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// 2846 2847 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) 2848 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) 2849 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff 2850 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 2851 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ 2852 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) 2853 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ 2854 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 2855 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ 2856 out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) 2857 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2858 do {\ 2859 HWIO_INTLOCK(); \ 2860 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ 2861 HWIO_INTFREE();\ 2862 } while (0) 2863 2864 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2865 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2866 2867 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// 2868 2869 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) 2870 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) 2871 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2872 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2873 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2874 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2875 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2876 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2877 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2878 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2879 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2880 do {\ 2881 HWIO_INTLOCK(); \ 2882 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2883 HWIO_INTFREE();\ 2884 } while (0) 2885 2886 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2887 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2888 2889 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2890 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2891 2892 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2893 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2894 2895 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// 2896 2897 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) 2898 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) 2899 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2900 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2901 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2902 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2903 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2904 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2905 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2906 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2907 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2908 do {\ 2909 HWIO_INTLOCK(); \ 2910 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2911 HWIO_INTFREE();\ 2912 } while (0) 2913 2914 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2915 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2916 2917 //// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// 2918 2919 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) 2920 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) 2921 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2922 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 2923 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ 2924 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) 2925 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2926 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2927 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2928 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2929 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2930 do {\ 2931 HWIO_INTLOCK(); \ 2932 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ 2933 HWIO_INTFREE();\ 2934 } while (0) 2935 2936 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2937 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2938 2939 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2940 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2941 2942 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2943 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2944 2945 //// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// 2946 2947 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) 2948 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) 2949 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2950 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2951 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2952 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2953 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2954 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2955 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2956 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2957 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2958 do {\ 2959 HWIO_INTLOCK(); \ 2960 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2961 HWIO_INTFREE();\ 2962 } while (0) 2963 2964 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2965 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2966 2967 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// 2968 2969 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) 2970 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) 2971 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2972 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2973 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2974 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2975 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2976 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2977 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2978 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2979 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2980 do {\ 2981 HWIO_INTLOCK(); \ 2982 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2983 HWIO_INTFREE();\ 2984 } while (0) 2985 2986 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2987 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2988 2989 //// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// 2990 2991 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) 2992 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) 2993 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2994 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2995 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2996 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2997 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2998 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2999 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3000 out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3001 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3002 do {\ 3003 HWIO_INTLOCK(); \ 3004 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3005 HWIO_INTFREE();\ 3006 } while (0) 3007 3008 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3009 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3010 3011 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3012 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3013 3014 //// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// 3015 3016 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) 3017 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) 3018 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3019 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 3020 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ 3021 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) 3022 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ 3023 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 3024 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ 3025 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) 3026 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3027 do {\ 3028 HWIO_INTLOCK(); \ 3029 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ 3030 HWIO_INTFREE();\ 3031 } while (0) 3032 3033 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3034 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3035 3036 //// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// 3037 3038 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) 3039 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) 3040 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3041 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 3042 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ 3043 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) 3044 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ 3045 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 3046 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ 3047 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) 3048 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3049 do {\ 3050 HWIO_INTLOCK(); \ 3051 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ 3052 HWIO_INTFREE();\ 3053 } while (0) 3054 3055 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3056 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3057 3058 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3059 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3060 3061 //// Register REO_R0_SW2REO_RING_MSI1_DATA //// 3062 3063 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) 3064 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) 3065 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff 3066 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 3067 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ 3068 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) 3069 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ 3070 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 3071 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ 3072 out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) 3073 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ 3074 do {\ 3075 HWIO_INTLOCK(); \ 3076 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ 3077 HWIO_INTFREE();\ 3078 } while (0) 3079 3080 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3081 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 3082 3083 //// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// 3084 3085 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) 3086 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) 3087 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3088 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 3089 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ 3090 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) 3091 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3092 in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3093 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3094 out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3095 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3096 do {\ 3097 HWIO_INTLOCK(); \ 3098 out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ 3099 HWIO_INTFREE();\ 3100 } while (0) 3101 3102 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3103 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3104 3105 //// Register REO_R0_REO2SW1_RING_BASE_LSB //// 3106 3107 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x00000244) 3108 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x00000244) 3109 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff 3110 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 3111 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ 3112 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) 3113 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ 3114 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 3115 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ 3116 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) 3117 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ 3118 do {\ 3119 HWIO_INTLOCK(); \ 3120 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ 3121 HWIO_INTFREE();\ 3122 } while (0) 3123 3124 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3125 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3126 3127 //// Register REO_R0_REO2SW1_RING_BASE_MSB //// 3128 3129 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x00000248) 3130 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x00000248) 3131 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x00ffffff 3132 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 3133 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ 3134 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) 3135 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ 3136 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 3137 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ 3138 out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) 3139 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ 3140 do {\ 3141 HWIO_INTLOCK(); \ 3142 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ 3143 HWIO_INTFREE();\ 3144 } while (0) 3145 3146 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3147 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3148 3149 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3150 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3151 3152 //// Register REO_R0_REO2SW1_RING_ID //// 3153 3154 #define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x0000024c) 3155 #define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x0000024c) 3156 #define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff 3157 #define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 3158 #define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ 3159 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) 3160 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ 3161 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 3162 #define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ 3163 out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) 3164 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ 3165 do {\ 3166 HWIO_INTLOCK(); \ 3167 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ 3168 HWIO_INTFREE();\ 3169 } while (0) 3170 3171 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 3172 #define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 3173 3174 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3175 #define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 3176 3177 //// Register REO_R0_REO2SW1_RING_STATUS //// 3178 3179 #define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x00000250) 3180 #define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x00000250) 3181 #define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff 3182 #define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 3183 #define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ 3184 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) 3185 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ 3186 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 3187 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ 3188 out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) 3189 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ 3190 do {\ 3191 HWIO_INTLOCK(); \ 3192 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ 3193 HWIO_INTFREE();\ 3194 } while (0) 3195 3196 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3197 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3198 3199 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3200 #define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3201 3202 //// Register REO_R0_REO2SW1_RING_MISC //// 3203 3204 #define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x00000254) 3205 #define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x00000254) 3206 #define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff 3207 #define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 3208 #define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ 3209 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) 3210 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ 3211 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 3212 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ 3213 out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) 3214 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ 3215 do {\ 3216 HWIO_INTLOCK(); \ 3217 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ 3218 HWIO_INTFREE();\ 3219 } while (0) 3220 3221 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3222 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 3223 3224 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3225 #define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3226 3227 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3228 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3229 3230 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3231 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3232 3233 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3234 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3235 3236 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3237 #define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3238 3239 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3240 #define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3241 3242 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3243 #define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3244 3245 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3246 #define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3247 3248 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3249 #define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 3250 3251 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3252 #define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3253 3254 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3255 #define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3256 3257 //// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// 3258 3259 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) 3260 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) 3261 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3262 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 3263 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ 3264 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) 3265 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ 3266 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 3267 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ 3268 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) 3269 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3270 do {\ 3271 HWIO_INTLOCK(); \ 3272 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ 3273 HWIO_INTFREE();\ 3274 } while (0) 3275 3276 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3277 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3278 3279 //// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// 3280 3281 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) 3282 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) 3283 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3284 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 3285 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ 3286 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) 3287 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ 3288 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 3289 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ 3290 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) 3291 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3292 do {\ 3293 HWIO_INTLOCK(); \ 3294 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ 3295 HWIO_INTFREE();\ 3296 } while (0) 3297 3298 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3299 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3300 3301 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// 3302 3303 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) 3304 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) 3305 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3306 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 3307 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ 3308 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) 3309 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3310 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3311 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3312 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3313 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3314 do {\ 3315 HWIO_INTLOCK(); \ 3316 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3317 HWIO_INTFREE();\ 3318 } while (0) 3319 3320 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3321 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3322 3323 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3324 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3325 3326 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3327 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3328 3329 //// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// 3330 3331 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) 3332 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) 3333 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3334 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 3335 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ 3336 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) 3337 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3338 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3339 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3340 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3341 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3342 do {\ 3343 HWIO_INTLOCK(); \ 3344 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3345 HWIO_INTFREE();\ 3346 } while (0) 3347 3348 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3349 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3350 3351 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3352 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3353 3354 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3355 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3356 3357 //// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// 3358 3359 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) 3360 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) 3361 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3362 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3363 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3364 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) 3365 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3366 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3367 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3368 out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3369 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3370 do {\ 3371 HWIO_INTLOCK(); \ 3372 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3373 HWIO_INTFREE();\ 3374 } while (0) 3375 3376 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3377 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3378 3379 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// 3380 3381 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) 3382 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) 3383 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3384 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 3385 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ 3386 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) 3387 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3388 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3389 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3390 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) 3391 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3392 do {\ 3393 HWIO_INTLOCK(); \ 3394 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ 3395 HWIO_INTFREE();\ 3396 } while (0) 3397 3398 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3399 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3400 3401 //// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// 3402 3403 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) 3404 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) 3405 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3406 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 3407 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ 3408 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) 3409 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3410 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3411 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3412 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) 3413 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3414 do {\ 3415 HWIO_INTLOCK(); \ 3416 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ 3417 HWIO_INTFREE();\ 3418 } while (0) 3419 3420 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3421 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3422 3423 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3424 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3425 3426 //// Register REO_R0_REO2SW1_RING_MSI1_DATA //// 3427 3428 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x00000294) 3429 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x00000294) 3430 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff 3431 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 3432 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ 3433 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) 3434 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ 3435 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 3436 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ 3437 out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) 3438 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3439 do {\ 3440 HWIO_INTLOCK(); \ 3441 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ 3442 HWIO_INTFREE();\ 3443 } while (0) 3444 3445 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3446 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 3447 3448 //// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// 3449 3450 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) 3451 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) 3452 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3453 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 3454 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ 3455 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) 3456 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3457 in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3458 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3459 out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3460 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3461 do {\ 3462 HWIO_INTLOCK(); \ 3463 out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3464 HWIO_INTFREE();\ 3465 } while (0) 3466 3467 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3468 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3469 3470 //// Register REO_R0_REO2SW2_RING_BASE_LSB //// 3471 3472 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x0000029c) 3473 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x0000029c) 3474 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff 3475 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 3476 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ 3477 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) 3478 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ 3479 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 3480 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ 3481 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) 3482 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ 3483 do {\ 3484 HWIO_INTLOCK(); \ 3485 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ 3486 HWIO_INTFREE();\ 3487 } while (0) 3488 3489 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3490 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3491 3492 //// Register REO_R0_REO2SW2_RING_BASE_MSB //// 3493 3494 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x000002a0) 3495 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x000002a0) 3496 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x00ffffff 3497 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 3498 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ 3499 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) 3500 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ 3501 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 3502 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ 3503 out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) 3504 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ 3505 do {\ 3506 HWIO_INTLOCK(); \ 3507 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ 3508 HWIO_INTFREE();\ 3509 } while (0) 3510 3511 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3512 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3513 3514 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3515 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3516 3517 //// Register REO_R0_REO2SW2_RING_ID //// 3518 3519 #define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x000002a4) 3520 #define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x000002a4) 3521 #define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff 3522 #define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 3523 #define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ 3524 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) 3525 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ 3526 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 3527 #define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ 3528 out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) 3529 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ 3530 do {\ 3531 HWIO_INTLOCK(); \ 3532 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ 3533 HWIO_INTFREE();\ 3534 } while (0) 3535 3536 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 3537 #define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 3538 3539 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3540 #define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 3541 3542 //// Register REO_R0_REO2SW2_RING_STATUS //// 3543 3544 #define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x000002a8) 3545 #define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x000002a8) 3546 #define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff 3547 #define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 3548 #define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ 3549 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) 3550 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ 3551 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 3552 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ 3553 out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) 3554 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ 3555 do {\ 3556 HWIO_INTLOCK(); \ 3557 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ 3558 HWIO_INTFREE();\ 3559 } while (0) 3560 3561 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3562 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3563 3564 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3565 #define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3566 3567 //// Register REO_R0_REO2SW2_RING_MISC //// 3568 3569 #define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x000002ac) 3570 #define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x000002ac) 3571 #define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff 3572 #define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 3573 #define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ 3574 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) 3575 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ 3576 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 3577 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ 3578 out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) 3579 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ 3580 do {\ 3581 HWIO_INTLOCK(); \ 3582 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ 3583 HWIO_INTFREE();\ 3584 } while (0) 3585 3586 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3587 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 3588 3589 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3590 #define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe 3591 3592 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3593 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3594 3595 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3596 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3597 3598 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3599 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3600 3601 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3602 #define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 3603 3604 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3605 #define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3606 3607 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3608 #define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3609 3610 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3611 #define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3612 3613 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3614 #define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 3615 3616 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3617 #define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3618 3619 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3620 #define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3621 3622 //// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// 3623 3624 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) 3625 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) 3626 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff 3627 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 3628 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ 3629 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) 3630 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ 3631 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 3632 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ 3633 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) 3634 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3635 do {\ 3636 HWIO_INTLOCK(); \ 3637 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ 3638 HWIO_INTFREE();\ 3639 } while (0) 3640 3641 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3642 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3643 3644 //// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// 3645 3646 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) 3647 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) 3648 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff 3649 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 3650 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ 3651 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) 3652 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ 3653 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 3654 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ 3655 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) 3656 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3657 do {\ 3658 HWIO_INTLOCK(); \ 3659 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ 3660 HWIO_INTFREE();\ 3661 } while (0) 3662 3663 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3664 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3665 3666 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// 3667 3668 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) 3669 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) 3670 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3671 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 3672 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ 3673 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) 3674 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3675 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3676 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3677 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3678 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3679 do {\ 3680 HWIO_INTLOCK(); \ 3681 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ 3682 HWIO_INTFREE();\ 3683 } while (0) 3684 3685 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3686 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3687 3688 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3689 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3690 3691 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3692 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3693 3694 //// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// 3695 3696 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) 3697 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) 3698 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3699 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 3700 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ 3701 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) 3702 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3703 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3704 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3705 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3706 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3707 do {\ 3708 HWIO_INTLOCK(); \ 3709 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ 3710 HWIO_INTFREE();\ 3711 } while (0) 3712 3713 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3714 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3715 3716 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3717 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3718 3719 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3720 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3721 3722 //// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// 3723 3724 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) 3725 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) 3726 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3727 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 3728 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3729 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) 3730 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3731 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3732 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3733 out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3734 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3735 do {\ 3736 HWIO_INTLOCK(); \ 3737 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3738 HWIO_INTFREE();\ 3739 } while (0) 3740 3741 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3742 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3743 3744 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// 3745 3746 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) 3747 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) 3748 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3749 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 3750 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ 3751 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) 3752 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ 3753 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 3754 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ 3755 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) 3756 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3757 do {\ 3758 HWIO_INTLOCK(); \ 3759 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ 3760 HWIO_INTFREE();\ 3761 } while (0) 3762 3763 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3764 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3765 3766 //// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// 3767 3768 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) 3769 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) 3770 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3771 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 3772 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ 3773 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) 3774 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ 3775 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 3776 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ 3777 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) 3778 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3779 do {\ 3780 HWIO_INTLOCK(); \ 3781 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ 3782 HWIO_INTFREE();\ 3783 } while (0) 3784 3785 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3786 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3787 3788 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3789 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3790 3791 //// Register REO_R0_REO2SW2_RING_MSI1_DATA //// 3792 3793 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) 3794 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) 3795 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff 3796 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 3797 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ 3798 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) 3799 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ 3800 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 3801 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ 3802 out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) 3803 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ 3804 do {\ 3805 HWIO_INTLOCK(); \ 3806 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ 3807 HWIO_INTFREE();\ 3808 } while (0) 3809 3810 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3811 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 3812 3813 //// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// 3814 3815 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) 3816 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) 3817 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3818 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 3819 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ 3820 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) 3821 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3822 in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3823 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3824 out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3825 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3826 do {\ 3827 HWIO_INTLOCK(); \ 3828 out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ 3829 HWIO_INTFREE();\ 3830 } while (0) 3831 3832 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3833 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3834 3835 //// Register REO_R0_REO2SW3_RING_BASE_LSB //// 3836 3837 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x000002f4) 3838 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x000002f4) 3839 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff 3840 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 3841 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ 3842 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) 3843 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ 3844 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 3845 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ 3846 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) 3847 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ 3848 do {\ 3849 HWIO_INTLOCK(); \ 3850 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ 3851 HWIO_INTFREE();\ 3852 } while (0) 3853 3854 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3855 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3856 3857 //// Register REO_R0_REO2SW3_RING_BASE_MSB //// 3858 3859 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002f8) 3860 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002f8) 3861 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x00ffffff 3862 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 3863 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ 3864 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) 3865 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ 3866 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 3867 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ 3868 out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) 3869 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ 3870 do {\ 3871 HWIO_INTLOCK(); \ 3872 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ 3873 HWIO_INTFREE();\ 3874 } while (0) 3875 3876 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3877 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3878 3879 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3880 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3881 3882 //// Register REO_R0_REO2SW3_RING_ID //// 3883 3884 #define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002fc) 3885 #define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002fc) 3886 #define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff 3887 #define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 3888 #define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ 3889 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) 3890 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ 3891 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 3892 #define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ 3893 out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) 3894 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ 3895 do {\ 3896 HWIO_INTLOCK(); \ 3897 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ 3898 HWIO_INTFREE();\ 3899 } while (0) 3900 3901 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 3902 #define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 3903 3904 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3905 #define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 3906 3907 //// Register REO_R0_REO2SW3_RING_STATUS //// 3908 3909 #define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x00000300) 3910 #define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x00000300) 3911 #define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff 3912 #define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 3913 #define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ 3914 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) 3915 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ 3916 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 3917 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ 3918 out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) 3919 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ 3920 do {\ 3921 HWIO_INTLOCK(); \ 3922 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ 3923 HWIO_INTFREE();\ 3924 } while (0) 3925 3926 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3927 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3928 3929 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3930 #define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3931 3932 //// Register REO_R0_REO2SW3_RING_MISC //// 3933 3934 #define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x00000304) 3935 #define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x00000304) 3936 #define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff 3937 #define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 3938 #define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ 3939 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) 3940 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ 3941 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 3942 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ 3943 out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) 3944 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ 3945 do {\ 3946 HWIO_INTLOCK(); \ 3947 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ 3948 HWIO_INTFREE();\ 3949 } while (0) 3950 3951 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3952 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 3953 3954 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3955 #define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe 3956 3957 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3958 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3959 3960 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3961 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3962 3963 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3964 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3965 3966 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3967 #define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 3968 3969 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3970 #define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3971 3972 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3973 #define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3974 3975 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3976 #define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3977 3978 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3979 #define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 3980 3981 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3982 #define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3983 3984 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3985 #define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3986 3987 //// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// 3988 3989 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) 3990 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) 3991 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff 3992 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 3993 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ 3994 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) 3995 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ 3996 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 3997 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ 3998 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) 3999 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4000 do {\ 4001 HWIO_INTLOCK(); \ 4002 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ 4003 HWIO_INTFREE();\ 4004 } while (0) 4005 4006 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4007 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4008 4009 //// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// 4010 4011 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) 4012 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) 4013 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff 4014 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 4015 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ 4016 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) 4017 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ 4018 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 4019 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ 4020 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) 4021 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4022 do {\ 4023 HWIO_INTLOCK(); \ 4024 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ 4025 HWIO_INTFREE();\ 4026 } while (0) 4027 4028 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4029 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4030 4031 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// 4032 4033 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) 4034 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) 4035 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4036 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 4037 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ 4038 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) 4039 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4040 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4041 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4042 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4043 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4044 do {\ 4045 HWIO_INTLOCK(); \ 4046 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ 4047 HWIO_INTFREE();\ 4048 } while (0) 4049 4050 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4051 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4052 4053 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4054 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4055 4056 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4057 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4058 4059 //// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// 4060 4061 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) 4062 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) 4063 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4064 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 4065 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ 4066 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) 4067 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4068 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4069 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4070 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4071 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4072 do {\ 4073 HWIO_INTLOCK(); \ 4074 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ 4075 HWIO_INTFREE();\ 4076 } while (0) 4077 4078 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4079 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4080 4081 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4082 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4083 4084 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4085 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4086 4087 //// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// 4088 4089 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) 4090 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) 4091 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4092 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 4093 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4094 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) 4095 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4096 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4097 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4098 out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4099 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4100 do {\ 4101 HWIO_INTLOCK(); \ 4102 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4103 HWIO_INTFREE();\ 4104 } while (0) 4105 4106 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4107 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4108 4109 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// 4110 4111 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) 4112 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) 4113 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4114 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 4115 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ 4116 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) 4117 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ 4118 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 4119 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ 4120 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) 4121 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4122 do {\ 4123 HWIO_INTLOCK(); \ 4124 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ 4125 HWIO_INTFREE();\ 4126 } while (0) 4127 4128 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4129 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4130 4131 //// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// 4132 4133 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) 4134 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) 4135 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4136 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 4137 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ 4138 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) 4139 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ 4140 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 4141 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ 4142 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) 4143 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4144 do {\ 4145 HWIO_INTLOCK(); \ 4146 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ 4147 HWIO_INTFREE();\ 4148 } while (0) 4149 4150 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4151 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4152 4153 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4154 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4155 4156 //// Register REO_R0_REO2SW3_RING_MSI1_DATA //// 4157 4158 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x00000344) 4159 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x00000344) 4160 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff 4161 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 4162 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ 4163 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) 4164 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ 4165 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 4166 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ 4167 out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) 4168 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ 4169 do {\ 4170 HWIO_INTLOCK(); \ 4171 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ 4172 HWIO_INTFREE();\ 4173 } while (0) 4174 4175 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4176 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 4177 4178 //// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// 4179 4180 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) 4181 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) 4182 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4183 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 4184 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ 4185 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) 4186 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4187 in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4188 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4189 out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4190 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4191 do {\ 4192 HWIO_INTLOCK(); \ 4193 out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ 4194 HWIO_INTFREE();\ 4195 } while (0) 4196 4197 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4198 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4199 4200 //// Register REO_R0_REO2SW4_RING_BASE_LSB //// 4201 4202 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x0000034c) 4203 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x0000034c) 4204 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff 4205 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 4206 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ 4207 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) 4208 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ 4209 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 4210 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ 4211 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) 4212 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ 4213 do {\ 4214 HWIO_INTLOCK(); \ 4215 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ 4216 HWIO_INTFREE();\ 4217 } while (0) 4218 4219 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4220 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4221 4222 //// Register REO_R0_REO2SW4_RING_BASE_MSB //// 4223 4224 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x00000350) 4225 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x00000350) 4226 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x00ffffff 4227 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 4228 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ 4229 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) 4230 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ 4231 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 4232 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ 4233 out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) 4234 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ 4235 do {\ 4236 HWIO_INTLOCK(); \ 4237 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ 4238 HWIO_INTFREE();\ 4239 } while (0) 4240 4241 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4242 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4243 4244 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4245 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4246 4247 //// Register REO_R0_REO2SW4_RING_ID //// 4248 4249 #define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x00000354) 4250 #define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x00000354) 4251 #define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff 4252 #define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 4253 #define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ 4254 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) 4255 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ 4256 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 4257 #define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ 4258 out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) 4259 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ 4260 do {\ 4261 HWIO_INTLOCK(); \ 4262 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ 4263 HWIO_INTFREE();\ 4264 } while (0) 4265 4266 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 4267 #define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 4268 4269 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4270 #define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 4271 4272 //// Register REO_R0_REO2SW4_RING_STATUS //// 4273 4274 #define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000358) 4275 #define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000358) 4276 #define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff 4277 #define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 4278 #define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ 4279 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) 4280 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ 4281 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 4282 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ 4283 out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) 4284 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ 4285 do {\ 4286 HWIO_INTLOCK(); \ 4287 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ 4288 HWIO_INTFREE();\ 4289 } while (0) 4290 4291 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4292 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4293 4294 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4295 #define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4296 4297 //// Register REO_R0_REO2SW4_RING_MISC //// 4298 4299 #define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x0000035c) 4300 #define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x0000035c) 4301 #define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff 4302 #define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 4303 #define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ 4304 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) 4305 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ 4306 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 4307 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ 4308 out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) 4309 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ 4310 do {\ 4311 HWIO_INTLOCK(); \ 4312 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ 4313 HWIO_INTFREE();\ 4314 } while (0) 4315 4316 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4317 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 4318 4319 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4320 #define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe 4321 4322 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4323 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4324 4325 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4326 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4327 4328 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4329 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4330 4331 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4332 #define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 4333 4334 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4335 #define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4336 4337 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4338 #define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4339 4340 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4341 #define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4342 4343 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4344 #define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 4345 4346 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4347 #define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4348 4349 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4350 #define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4351 4352 //// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// 4353 4354 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) 4355 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) 4356 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff 4357 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 4358 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ 4359 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) 4360 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ 4361 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 4362 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ 4363 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) 4364 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4365 do {\ 4366 HWIO_INTLOCK(); \ 4367 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ 4368 HWIO_INTFREE();\ 4369 } while (0) 4370 4371 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4372 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4373 4374 //// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// 4375 4376 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) 4377 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) 4378 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff 4379 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 4380 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ 4381 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) 4382 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ 4383 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 4384 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ 4385 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) 4386 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4387 do {\ 4388 HWIO_INTLOCK(); \ 4389 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ 4390 HWIO_INTFREE();\ 4391 } while (0) 4392 4393 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4394 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4395 4396 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// 4397 4398 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) 4399 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) 4400 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4401 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 4402 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ 4403 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) 4404 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4405 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4406 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4407 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4408 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4409 do {\ 4410 HWIO_INTLOCK(); \ 4411 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ 4412 HWIO_INTFREE();\ 4413 } while (0) 4414 4415 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4416 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4417 4418 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4419 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4420 4421 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4422 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4423 4424 //// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// 4425 4426 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) 4427 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) 4428 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4429 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 4430 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ 4431 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) 4432 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4433 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4434 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4435 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4436 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4437 do {\ 4438 HWIO_INTLOCK(); \ 4439 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ 4440 HWIO_INTFREE();\ 4441 } while (0) 4442 4443 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4444 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4445 4446 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4447 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4448 4449 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4450 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4451 4452 //// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// 4453 4454 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) 4455 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) 4456 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4457 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 4458 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4459 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) 4460 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4461 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4462 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4463 out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4464 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4465 do {\ 4466 HWIO_INTLOCK(); \ 4467 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4468 HWIO_INTFREE();\ 4469 } while (0) 4470 4471 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4472 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4473 4474 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// 4475 4476 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) 4477 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) 4478 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4479 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 4480 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ 4481 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) 4482 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ 4483 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 4484 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ 4485 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) 4486 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4487 do {\ 4488 HWIO_INTLOCK(); \ 4489 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ 4490 HWIO_INTFREE();\ 4491 } while (0) 4492 4493 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4494 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4495 4496 //// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// 4497 4498 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) 4499 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) 4500 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4501 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 4502 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ 4503 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) 4504 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ 4505 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 4506 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ 4507 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) 4508 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4509 do {\ 4510 HWIO_INTLOCK(); \ 4511 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ 4512 HWIO_INTFREE();\ 4513 } while (0) 4514 4515 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4516 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4517 4518 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4519 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4520 4521 //// Register REO_R0_REO2SW4_RING_MSI1_DATA //// 4522 4523 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) 4524 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) 4525 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff 4526 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 4527 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ 4528 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) 4529 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ 4530 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 4531 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ 4532 out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) 4533 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ 4534 do {\ 4535 HWIO_INTLOCK(); \ 4536 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ 4537 HWIO_INTFREE();\ 4538 } while (0) 4539 4540 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4541 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 4542 4543 //// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// 4544 4545 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) 4546 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) 4547 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4548 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 4549 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ 4550 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) 4551 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4552 in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4553 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4554 out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4555 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4556 do {\ 4557 HWIO_INTLOCK(); \ 4558 out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ 4559 HWIO_INTFREE();\ 4560 } while (0) 4561 4562 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4563 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4564 4565 //// Register REO_R0_REO2TCL_RING_BASE_LSB //// 4566 4567 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003a4) 4568 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003a4) 4569 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff 4570 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 4571 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ 4572 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) 4573 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ 4574 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 4575 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ 4576 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) 4577 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ 4578 do {\ 4579 HWIO_INTLOCK(); \ 4580 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ 4581 HWIO_INTFREE();\ 4582 } while (0) 4583 4584 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4585 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4586 4587 //// Register REO_R0_REO2TCL_RING_BASE_MSB //// 4588 4589 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x000003a8) 4590 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x000003a8) 4591 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x00ffffff 4592 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 4593 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ 4594 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) 4595 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ 4596 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 4597 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ 4598 out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) 4599 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ 4600 do {\ 4601 HWIO_INTLOCK(); \ 4602 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ 4603 HWIO_INTFREE();\ 4604 } while (0) 4605 4606 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4607 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4608 4609 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4610 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4611 4612 //// Register REO_R0_REO2TCL_RING_ID //// 4613 4614 #define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x000003ac) 4615 #define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x000003ac) 4616 #define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff 4617 #define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 4618 #define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ 4619 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) 4620 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ 4621 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 4622 #define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ 4623 out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) 4624 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ 4625 do {\ 4626 HWIO_INTLOCK(); \ 4627 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ 4628 HWIO_INTFREE();\ 4629 } while (0) 4630 4631 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 4632 #define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 4633 4634 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4635 #define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 4636 4637 //// Register REO_R0_REO2TCL_RING_STATUS //// 4638 4639 #define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x000003b0) 4640 #define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x000003b0) 4641 #define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff 4642 #define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 4643 #define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ 4644 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) 4645 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ 4646 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 4647 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ 4648 out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) 4649 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ 4650 do {\ 4651 HWIO_INTLOCK(); \ 4652 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ 4653 HWIO_INTFREE();\ 4654 } while (0) 4655 4656 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4657 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4658 4659 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4660 #define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4661 4662 //// Register REO_R0_REO2TCL_RING_MISC //// 4663 4664 #define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x000003b4) 4665 #define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x000003b4) 4666 #define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff 4667 #define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 4668 #define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ 4669 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) 4670 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ 4671 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 4672 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ 4673 out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) 4674 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ 4675 do {\ 4676 HWIO_INTLOCK(); \ 4677 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ 4678 HWIO_INTFREE();\ 4679 } while (0) 4680 4681 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4682 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 4683 4684 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4685 #define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe 4686 4687 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4688 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4689 4690 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4691 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4692 4693 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4694 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4695 4696 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4697 #define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 4698 4699 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4700 #define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4701 4702 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4703 #define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4704 4705 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4706 #define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4707 4708 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4709 #define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 4710 4711 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4712 #define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4713 4714 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4715 #define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4716 4717 //// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// 4718 4719 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) 4720 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) 4721 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff 4722 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 4723 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ 4724 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) 4725 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ 4726 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 4727 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ 4728 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) 4729 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4730 do {\ 4731 HWIO_INTLOCK(); \ 4732 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ 4733 HWIO_INTFREE();\ 4734 } while (0) 4735 4736 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4737 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4738 4739 //// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// 4740 4741 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) 4742 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) 4743 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff 4744 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 4745 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ 4746 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) 4747 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ 4748 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 4749 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ 4750 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) 4751 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4752 do {\ 4753 HWIO_INTLOCK(); \ 4754 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ 4755 HWIO_INTFREE();\ 4756 } while (0) 4757 4758 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4759 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4760 4761 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// 4762 4763 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) 4764 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) 4765 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4766 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 4767 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ 4768 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) 4769 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4770 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4771 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4772 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4773 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4774 do {\ 4775 HWIO_INTLOCK(); \ 4776 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ 4777 HWIO_INTFREE();\ 4778 } while (0) 4779 4780 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4781 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4782 4783 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4784 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4785 4786 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4787 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4788 4789 //// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// 4790 4791 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) 4792 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) 4793 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4794 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 4795 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ 4796 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) 4797 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4798 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4799 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4800 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4801 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4802 do {\ 4803 HWIO_INTLOCK(); \ 4804 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ 4805 HWIO_INTFREE();\ 4806 } while (0) 4807 4808 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4809 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4810 4811 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4812 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4813 4814 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4815 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4816 4817 //// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// 4818 4819 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) 4820 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) 4821 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4822 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 4823 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4824 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) 4825 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4826 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4827 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4828 out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4829 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4830 do {\ 4831 HWIO_INTLOCK(); \ 4832 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4833 HWIO_INTFREE();\ 4834 } while (0) 4835 4836 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4837 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4838 4839 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// 4840 4841 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) 4842 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) 4843 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4844 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 4845 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ 4846 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) 4847 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ 4848 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 4849 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ 4850 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) 4851 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4852 do {\ 4853 HWIO_INTLOCK(); \ 4854 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ 4855 HWIO_INTFREE();\ 4856 } while (0) 4857 4858 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4859 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4860 4861 //// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// 4862 4863 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) 4864 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) 4865 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4866 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 4867 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ 4868 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) 4869 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ 4870 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 4871 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ 4872 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) 4873 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4874 do {\ 4875 HWIO_INTLOCK(); \ 4876 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ 4877 HWIO_INTFREE();\ 4878 } while (0) 4879 4880 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4881 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4882 4883 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4884 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4885 4886 //// Register REO_R0_REO2TCL_RING_MSI1_DATA //// 4887 4888 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) 4889 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) 4890 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff 4891 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 4892 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ 4893 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) 4894 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ 4895 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 4896 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ 4897 out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) 4898 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ 4899 do {\ 4900 HWIO_INTLOCK(); \ 4901 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ 4902 HWIO_INTFREE();\ 4903 } while (0) 4904 4905 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4906 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 4907 4908 //// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// 4909 4910 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) 4911 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) 4912 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4913 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 4914 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ 4915 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) 4916 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4917 in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4918 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4919 out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4920 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4921 do {\ 4922 HWIO_INTLOCK(); \ 4923 out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ 4924 HWIO_INTFREE();\ 4925 } while (0) 4926 4927 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4928 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4929 4930 //// Register REO_R0_REO2FW_RING_BASE_LSB //// 4931 4932 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x000003fc) 4933 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x000003fc) 4934 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff 4935 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 4936 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ 4937 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) 4938 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ 4939 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 4940 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ 4941 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) 4942 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4943 do {\ 4944 HWIO_INTLOCK(); \ 4945 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ 4946 HWIO_INTFREE();\ 4947 } while (0) 4948 4949 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4950 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4951 4952 //// Register REO_R0_REO2FW_RING_BASE_MSB //// 4953 4954 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000400) 4955 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000400) 4956 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x00ffffff 4957 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 4958 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ 4959 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) 4960 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ 4961 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 4962 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ 4963 out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) 4964 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4965 do {\ 4966 HWIO_INTLOCK(); \ 4967 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ 4968 HWIO_INTFREE();\ 4969 } while (0) 4970 4971 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4972 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4973 4974 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4975 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4976 4977 //// Register REO_R0_REO2FW_RING_ID //// 4978 4979 #define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x00000404) 4980 #define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x00000404) 4981 #define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff 4982 #define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 4983 #define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ 4984 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) 4985 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ 4986 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 4987 #define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ 4988 out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) 4989 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ 4990 do {\ 4991 HWIO_INTLOCK(); \ 4992 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ 4993 HWIO_INTFREE();\ 4994 } while (0) 4995 4996 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4997 #define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 4998 4999 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5000 #define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 5001 5002 //// Register REO_R0_REO2FW_RING_STATUS //// 5003 5004 #define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000408) 5005 #define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000408) 5006 #define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff 5007 #define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 5008 #define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ 5009 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) 5010 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ 5011 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 5012 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ 5013 out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) 5014 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ 5015 do {\ 5016 HWIO_INTLOCK(); \ 5017 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ 5018 HWIO_INTFREE();\ 5019 } while (0) 5020 5021 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5022 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5023 5024 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5025 #define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5026 5027 //// Register REO_R0_REO2FW_RING_MISC //// 5028 5029 #define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x0000040c) 5030 #define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x0000040c) 5031 #define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff 5032 #define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 5033 #define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ 5034 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) 5035 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ 5036 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 5037 #define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ 5038 out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) 5039 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ 5040 do {\ 5041 HWIO_INTLOCK(); \ 5042 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ 5043 HWIO_INTFREE();\ 5044 } while (0) 5045 5046 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5047 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 5048 5049 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5050 #define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 5051 5052 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5053 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5054 5055 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5056 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5057 5058 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5059 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5060 5061 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5062 #define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 5063 5064 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5065 #define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5066 5067 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5068 #define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5069 5070 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5071 #define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5072 5073 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5074 #define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 5075 5076 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5077 #define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5078 5079 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5080 #define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5081 5082 //// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// 5083 5084 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) 5085 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) 5086 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 5087 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 5088 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ 5089 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) 5090 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 5091 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 5092 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 5093 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) 5094 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5095 do {\ 5096 HWIO_INTLOCK(); \ 5097 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ 5098 HWIO_INTFREE();\ 5099 } while (0) 5100 5101 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5102 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5103 5104 //// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// 5105 5106 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) 5107 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) 5108 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 5109 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 5110 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ 5111 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) 5112 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 5113 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 5114 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 5115 out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) 5116 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5117 do {\ 5118 HWIO_INTLOCK(); \ 5119 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ 5120 HWIO_INTFREE();\ 5121 } while (0) 5122 5123 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5124 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5125 5126 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// 5127 5128 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) 5129 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) 5130 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5131 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 5132 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 5133 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) 5134 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5135 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5136 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5137 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5138 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5139 do {\ 5140 HWIO_INTLOCK(); \ 5141 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 5142 HWIO_INTFREE();\ 5143 } while (0) 5144 5145 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5146 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5147 5148 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5149 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5150 5151 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5152 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5153 5154 //// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// 5155 5156 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) 5157 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) 5158 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5159 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 5160 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 5161 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) 5162 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5163 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5164 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5165 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5166 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5167 do {\ 5168 HWIO_INTLOCK(); \ 5169 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 5170 HWIO_INTFREE();\ 5171 } while (0) 5172 5173 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5174 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5175 5176 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5177 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5178 5179 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5180 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5181 5182 //// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// 5183 5184 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) 5185 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) 5186 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5187 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 5188 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5189 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 5190 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5191 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5192 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5193 out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5194 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5195 do {\ 5196 HWIO_INTLOCK(); \ 5197 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5198 HWIO_INTFREE();\ 5199 } while (0) 5200 5201 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5202 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5203 5204 //// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// 5205 5206 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) 5207 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) 5208 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5209 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 5210 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ 5211 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) 5212 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ 5213 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 5214 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ 5215 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) 5216 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5217 do {\ 5218 HWIO_INTLOCK(); \ 5219 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ 5220 HWIO_INTFREE();\ 5221 } while (0) 5222 5223 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5224 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5225 5226 //// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// 5227 5228 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) 5229 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) 5230 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5231 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 5232 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ 5233 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) 5234 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ 5235 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 5236 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ 5237 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) 5238 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5239 do {\ 5240 HWIO_INTLOCK(); \ 5241 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ 5242 HWIO_INTFREE();\ 5243 } while (0) 5244 5245 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5246 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5247 5248 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5249 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5250 5251 //// Register REO_R0_REO2FW_RING_MSI1_DATA //// 5252 5253 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) 5254 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) 5255 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff 5256 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 5257 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ 5258 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) 5259 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ 5260 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 5261 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ 5262 out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) 5263 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ 5264 do {\ 5265 HWIO_INTLOCK(); \ 5266 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ 5267 HWIO_INTFREE();\ 5268 } while (0) 5269 5270 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5271 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 5272 5273 //// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// 5274 5275 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) 5276 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) 5277 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5278 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 5279 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 5280 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) 5281 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5282 in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5283 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5284 out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5285 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5286 do {\ 5287 HWIO_INTLOCK(); \ 5288 out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 5289 HWIO_INTFREE();\ 5290 } while (0) 5291 5292 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5293 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5294 5295 //// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// 5296 5297 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000454) 5298 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000454) 5299 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff 5300 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 5301 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ 5302 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) 5303 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ 5304 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 5305 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ 5306 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) 5307 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ 5308 do {\ 5309 HWIO_INTLOCK(); \ 5310 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ 5311 HWIO_INTFREE();\ 5312 } while (0) 5313 5314 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5315 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5316 5317 //// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// 5318 5319 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000458) 5320 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000458) 5321 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff 5322 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 5323 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ 5324 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) 5325 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ 5326 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 5327 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ 5328 out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) 5329 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ 5330 do {\ 5331 HWIO_INTLOCK(); \ 5332 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ 5333 HWIO_INTFREE();\ 5334 } while (0) 5335 5336 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5337 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5338 5339 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5340 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5341 5342 //// Register REO_R0_REO_RELEASE_RING_ID //// 5343 5344 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000045c) 5345 #define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000045c) 5346 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff 5347 #define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 5348 #define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ 5349 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) 5350 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ 5351 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 5352 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ 5353 out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) 5354 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ 5355 do {\ 5356 HWIO_INTLOCK(); \ 5357 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ 5358 HWIO_INTFREE();\ 5359 } while (0) 5360 5361 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 5362 #define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 5363 5364 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5365 #define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 5366 5367 //// Register REO_R0_REO_RELEASE_RING_STATUS //// 5368 5369 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x00000460) 5370 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x00000460) 5371 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff 5372 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 5373 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ 5374 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) 5375 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ 5376 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 5377 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ 5378 out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) 5379 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ 5380 do {\ 5381 HWIO_INTLOCK(); \ 5382 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ 5383 HWIO_INTFREE();\ 5384 } while (0) 5385 5386 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5387 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5388 5389 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5390 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5391 5392 //// Register REO_R0_REO_RELEASE_RING_MISC //// 5393 5394 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x00000464) 5395 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x00000464) 5396 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff 5397 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 5398 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ 5399 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) 5400 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ 5401 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 5402 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ 5403 out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) 5404 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ 5405 do {\ 5406 HWIO_INTLOCK(); \ 5407 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ 5408 HWIO_INTFREE();\ 5409 } while (0) 5410 5411 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5412 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 5413 5414 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5415 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe 5416 5417 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5418 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5419 5420 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5421 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5422 5423 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5424 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5425 5426 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5427 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 5428 5429 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5430 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5431 5432 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5433 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5434 5435 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5436 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5437 5438 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5439 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 5440 5441 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5442 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5443 5444 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5445 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5446 5447 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// 5448 5449 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) 5450 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) 5451 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff 5452 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 5453 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ 5454 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) 5455 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ 5456 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 5457 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ 5458 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) 5459 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5460 do {\ 5461 HWIO_INTLOCK(); \ 5462 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ 5463 HWIO_INTFREE();\ 5464 } while (0) 5465 5466 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5467 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5468 5469 //// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// 5470 5471 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) 5472 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) 5473 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff 5474 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 5475 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ 5476 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) 5477 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ 5478 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 5479 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ 5480 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) 5481 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5482 do {\ 5483 HWIO_INTLOCK(); \ 5484 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ 5485 HWIO_INTFREE();\ 5486 } while (0) 5487 5488 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5489 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5490 5491 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// 5492 5493 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) 5494 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) 5495 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5496 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 5497 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ 5498 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) 5499 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5500 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5501 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5502 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5503 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5504 do {\ 5505 HWIO_INTLOCK(); \ 5506 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ 5507 HWIO_INTFREE();\ 5508 } while (0) 5509 5510 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5511 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5512 5513 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5514 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5515 5516 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5517 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5518 5519 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// 5520 5521 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) 5522 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) 5523 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5524 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 5525 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ 5526 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) 5527 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5528 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5529 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5530 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5531 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5532 do {\ 5533 HWIO_INTLOCK(); \ 5534 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ 5535 HWIO_INTFREE();\ 5536 } while (0) 5537 5538 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5539 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5540 5541 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5542 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5543 5544 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5545 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5546 5547 //// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// 5548 5549 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) 5550 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) 5551 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5552 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 5553 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5554 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) 5555 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5556 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5557 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5558 out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5559 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5560 do {\ 5561 HWIO_INTLOCK(); \ 5562 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5563 HWIO_INTFREE();\ 5564 } while (0) 5565 5566 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5567 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5568 5569 //// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// 5570 5571 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) 5572 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) 5573 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5574 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 5575 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ 5576 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) 5577 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5578 in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5579 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5580 out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5581 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5582 do {\ 5583 HWIO_INTLOCK(); \ 5584 out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ 5585 HWIO_INTFREE();\ 5586 } while (0) 5587 5588 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5589 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5590 5591 //// Register REO_R0_REO_STATUS_RING_BASE_LSB //// 5592 5593 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x000004ac) 5594 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x000004ac) 5595 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff 5596 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 5597 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ 5598 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) 5599 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ 5600 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 5601 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ 5602 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) 5603 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 5604 do {\ 5605 HWIO_INTLOCK(); \ 5606 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ 5607 HWIO_INTFREE();\ 5608 } while (0) 5609 5610 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 5611 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 5612 5613 //// Register REO_R0_REO_STATUS_RING_BASE_MSB //// 5614 5615 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x000004b0) 5616 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x000004b0) 5617 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 5618 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 5619 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ 5620 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) 5621 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ 5622 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 5623 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ 5624 out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) 5625 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 5626 do {\ 5627 HWIO_INTLOCK(); \ 5628 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ 5629 HWIO_INTFREE();\ 5630 } while (0) 5631 5632 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 5633 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 5634 5635 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 5636 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 5637 5638 //// Register REO_R0_REO_STATUS_RING_ID //// 5639 5640 #define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x000004b4) 5641 #define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x000004b4) 5642 #define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff 5643 #define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 5644 #define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ 5645 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) 5646 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ 5647 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 5648 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ 5649 out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) 5650 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ 5651 do {\ 5652 HWIO_INTLOCK(); \ 5653 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ 5654 HWIO_INTFREE();\ 5655 } while (0) 5656 5657 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 5658 #define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 5659 5660 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 5661 #define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 5662 5663 //// Register REO_R0_REO_STATUS_RING_STATUS //// 5664 5665 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x000004b8) 5666 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x000004b8) 5667 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff 5668 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 5669 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ 5670 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) 5671 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ 5672 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 5673 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ 5674 out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) 5675 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ 5676 do {\ 5677 HWIO_INTLOCK(); \ 5678 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ 5679 HWIO_INTFREE();\ 5680 } while (0) 5681 5682 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 5683 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 5684 5685 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 5686 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 5687 5688 //// Register REO_R0_REO_STATUS_RING_MISC //// 5689 5690 #define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x000004bc) 5691 #define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x000004bc) 5692 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff 5693 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 5694 #define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ 5695 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) 5696 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ 5697 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 5698 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ 5699 out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) 5700 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ 5701 do {\ 5702 HWIO_INTLOCK(); \ 5703 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ 5704 HWIO_INTFREE();\ 5705 } while (0) 5706 5707 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 5708 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 5709 5710 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 5711 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 5712 5713 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 5714 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 5715 5716 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 5717 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 5718 5719 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 5720 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 5721 5722 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 5723 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 5724 5725 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 5726 #define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 5727 5728 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 5729 #define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 5730 5731 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 5732 #define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 5733 5734 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 5735 #define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 5736 5737 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 5738 #define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 5739 5740 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 5741 #define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 5742 5743 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// 5744 5745 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) 5746 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) 5747 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 5748 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 5749 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ 5750 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) 5751 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 5752 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 5753 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 5754 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 5755 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 5756 do {\ 5757 HWIO_INTLOCK(); \ 5758 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 5759 HWIO_INTFREE();\ 5760 } while (0) 5761 5762 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 5763 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 5764 5765 //// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// 5766 5767 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) 5768 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) 5769 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 5770 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 5771 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ 5772 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) 5773 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 5774 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 5775 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 5776 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 5777 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 5778 do {\ 5779 HWIO_INTLOCK(); \ 5780 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 5781 HWIO_INTFREE();\ 5782 } while (0) 5783 5784 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 5785 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 5786 5787 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// 5788 5789 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) 5790 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) 5791 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 5792 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 5793 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 5794 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 5795 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 5796 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 5797 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 5798 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 5799 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 5800 do {\ 5801 HWIO_INTLOCK(); \ 5802 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 5803 HWIO_INTFREE();\ 5804 } while (0) 5805 5806 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 5807 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 5808 5809 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 5810 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 5811 5812 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 5813 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 5814 5815 //// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// 5816 5817 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) 5818 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) 5819 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 5820 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 5821 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 5822 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 5823 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 5824 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 5825 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 5826 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 5827 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 5828 do {\ 5829 HWIO_INTLOCK(); \ 5830 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 5831 HWIO_INTFREE();\ 5832 } while (0) 5833 5834 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 5835 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 5836 5837 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 5838 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 5839 5840 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 5841 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 5842 5843 //// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// 5844 5845 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) 5846 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) 5847 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 5848 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 5849 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 5850 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 5851 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 5852 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 5853 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 5854 out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 5855 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 5856 do {\ 5857 HWIO_INTLOCK(); \ 5858 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 5859 HWIO_INTFREE();\ 5860 } while (0) 5861 5862 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 5863 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 5864 5865 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// 5866 5867 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) 5868 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) 5869 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 5870 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 5871 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 5872 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) 5873 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 5874 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 5875 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 5876 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 5877 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 5878 do {\ 5879 HWIO_INTLOCK(); \ 5880 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 5881 HWIO_INTFREE();\ 5882 } while (0) 5883 5884 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 5885 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 5886 5887 //// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// 5888 5889 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) 5890 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) 5891 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 5892 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 5893 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 5894 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) 5895 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 5896 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 5897 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 5898 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 5899 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 5900 do {\ 5901 HWIO_INTLOCK(); \ 5902 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 5903 HWIO_INTFREE();\ 5904 } while (0) 5905 5906 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 5907 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 5908 5909 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 5910 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 5911 5912 //// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// 5913 5914 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) 5915 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) 5916 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 5917 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 5918 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ 5919 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) 5920 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ 5921 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 5922 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ 5923 out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) 5924 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 5925 do {\ 5926 HWIO_INTLOCK(); \ 5927 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ 5928 HWIO_INTFREE();\ 5929 } while (0) 5930 5931 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 5932 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 5933 5934 //// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// 5935 5936 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) 5937 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) 5938 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 5939 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 5940 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 5941 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 5942 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 5943 in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 5944 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 5945 out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 5946 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 5947 do {\ 5948 HWIO_INTLOCK(); \ 5949 out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 5950 HWIO_INTFREE();\ 5951 } while (0) 5952 5953 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 5954 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 5955 5956 //// Register REO_R0_WATCHDOG_TIMEOUT //// 5957 5958 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x00000504) 5959 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x00000504) 5960 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00000fff 5961 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 5962 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ 5963 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) 5964 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ 5965 in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 5966 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ 5967 out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) 5968 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ 5969 do {\ 5970 HWIO_INTLOCK(); \ 5971 out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ 5972 HWIO_INTFREE();\ 5973 } while (0) 5974 5975 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff 5976 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 5977 5978 //// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// 5979 5980 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000508) 5981 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000508) 5982 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff 5983 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 5984 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ 5985 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) 5986 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ 5987 in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 5988 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ 5989 out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) 5990 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ 5991 do {\ 5992 HWIO_INTLOCK(); \ 5993 out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ 5994 HWIO_INTFREE();\ 5995 } while (0) 5996 5997 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff 5998 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 5999 6000 //// Register REO_R0_AGING_THRESHOLD_IX_0 //// 6001 6002 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x0000050c) 6003 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x0000050c) 6004 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff 6005 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 6006 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ 6007 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) 6008 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ 6009 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 6010 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ 6011 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) 6012 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ 6013 do {\ 6014 HWIO_INTLOCK(); \ 6015 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ 6016 HWIO_INTFREE();\ 6017 } while (0) 6018 6019 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff 6020 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 6021 6022 //// Register REO_R0_AGING_THRESHOLD_IX_1 //// 6023 6024 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000510) 6025 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000510) 6026 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff 6027 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 6028 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ 6029 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) 6030 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ 6031 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 6032 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ 6033 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) 6034 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ 6035 do {\ 6036 HWIO_INTLOCK(); \ 6037 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ 6038 HWIO_INTFREE();\ 6039 } while (0) 6040 6041 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff 6042 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 6043 6044 //// Register REO_R0_AGING_THRESHOLD_IX_2 //// 6045 6046 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x00000514) 6047 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x00000514) 6048 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff 6049 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 6050 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ 6051 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) 6052 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ 6053 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 6054 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ 6055 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) 6056 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ 6057 do {\ 6058 HWIO_INTLOCK(); \ 6059 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ 6060 HWIO_INTFREE();\ 6061 } while (0) 6062 6063 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff 6064 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 6065 6066 //// Register REO_R0_AGING_THRESHOLD_IX_3 //// 6067 6068 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000518) 6069 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000518) 6070 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff 6071 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 6072 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ 6073 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) 6074 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ 6075 in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 6076 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ 6077 out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) 6078 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ 6079 do {\ 6080 HWIO_INTLOCK(); \ 6081 out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ 6082 HWIO_INTFREE();\ 6083 } while (0) 6084 6085 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff 6086 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 6087 6088 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// 6089 6090 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x0000051c) 6091 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x0000051c) 6092 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff 6093 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 6094 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ 6095 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) 6096 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ 6097 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 6098 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ 6099 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) 6100 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ 6101 do {\ 6102 HWIO_INTLOCK(); \ 6103 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ 6104 HWIO_INTFREE();\ 6105 } while (0) 6106 6107 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6108 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 6109 6110 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// 6111 6112 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000520) 6113 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000520) 6114 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff 6115 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 6116 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ 6117 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) 6118 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ 6119 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 6120 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ 6121 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) 6122 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ 6123 do {\ 6124 HWIO_INTLOCK(); \ 6125 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ 6126 HWIO_INTFREE();\ 6127 } while (0) 6128 6129 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6130 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 6131 6132 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// 6133 6134 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x00000524) 6135 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x00000524) 6136 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff 6137 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 6138 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ 6139 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) 6140 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ 6141 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 6142 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ 6143 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) 6144 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ 6145 do {\ 6146 HWIO_INTLOCK(); \ 6147 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ 6148 HWIO_INTFREE();\ 6149 } while (0) 6150 6151 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6152 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 6153 6154 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// 6155 6156 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000528) 6157 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000528) 6158 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff 6159 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 6160 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ 6161 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) 6162 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ 6163 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 6164 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ 6165 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) 6166 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ 6167 do {\ 6168 HWIO_INTLOCK(); \ 6169 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ 6170 HWIO_INTFREE();\ 6171 } while (0) 6172 6173 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6174 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 6175 6176 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// 6177 6178 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x0000052c) 6179 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x0000052c) 6180 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff 6181 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 6182 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ 6183 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) 6184 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ 6185 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 6186 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ 6187 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) 6188 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ 6189 do {\ 6190 HWIO_INTLOCK(); \ 6191 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ 6192 HWIO_INTFREE();\ 6193 } while (0) 6194 6195 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6196 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 6197 6198 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// 6199 6200 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000530) 6201 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000530) 6202 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff 6203 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 6204 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ 6205 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) 6206 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ 6207 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 6208 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ 6209 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) 6210 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ 6211 do {\ 6212 HWIO_INTLOCK(); \ 6213 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ 6214 HWIO_INTFREE();\ 6215 } while (0) 6216 6217 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6218 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 6219 6220 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// 6221 6222 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x00000534) 6223 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x00000534) 6224 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff 6225 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 6226 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ 6227 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) 6228 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ 6229 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 6230 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ 6231 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) 6232 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ 6233 do {\ 6234 HWIO_INTLOCK(); \ 6235 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ 6236 HWIO_INTFREE();\ 6237 } while (0) 6238 6239 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6240 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 6241 6242 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// 6243 6244 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000538) 6245 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000538) 6246 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff 6247 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 6248 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ 6249 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) 6250 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ 6251 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 6252 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ 6253 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) 6254 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ 6255 do {\ 6256 HWIO_INTLOCK(); \ 6257 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ 6258 HWIO_INTFREE();\ 6259 } while (0) 6260 6261 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6262 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 6263 6264 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// 6265 6266 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x0000053c) 6267 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x0000053c) 6268 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff 6269 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 6270 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ 6271 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) 6272 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ 6273 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 6274 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ 6275 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) 6276 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ 6277 do {\ 6278 HWIO_INTLOCK(); \ 6279 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ 6280 HWIO_INTFREE();\ 6281 } while (0) 6282 6283 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6284 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 6285 6286 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// 6287 6288 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000540) 6289 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000540) 6290 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff 6291 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 6292 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ 6293 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) 6294 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ 6295 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 6296 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ 6297 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) 6298 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ 6299 do {\ 6300 HWIO_INTLOCK(); \ 6301 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ 6302 HWIO_INTFREE();\ 6303 } while (0) 6304 6305 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6306 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 6307 6308 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// 6309 6310 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x00000544) 6311 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x00000544) 6312 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff 6313 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 6314 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ 6315 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) 6316 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ 6317 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 6318 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ 6319 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) 6320 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ 6321 do {\ 6322 HWIO_INTLOCK(); \ 6323 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ 6324 HWIO_INTFREE();\ 6325 } while (0) 6326 6327 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6328 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 6329 6330 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// 6331 6332 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x00000548) 6333 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x00000548) 6334 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff 6335 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 6336 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ 6337 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) 6338 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ 6339 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 6340 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ 6341 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) 6342 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ 6343 do {\ 6344 HWIO_INTLOCK(); \ 6345 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ 6346 HWIO_INTFREE();\ 6347 } while (0) 6348 6349 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6350 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 6351 6352 //// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// 6353 6354 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x0000054c) 6355 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x0000054c) 6356 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff 6357 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 6358 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ 6359 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) 6360 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ 6361 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 6362 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ 6363 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) 6364 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ 6365 do {\ 6366 HWIO_INTLOCK(); \ 6367 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ 6368 HWIO_INTFREE();\ 6369 } while (0) 6370 6371 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff 6372 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 6373 6374 //// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// 6375 6376 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x00000550) 6377 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x00000550) 6378 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff 6379 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 6380 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ 6381 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) 6382 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ 6383 in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 6384 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ 6385 out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) 6386 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ 6387 do {\ 6388 HWIO_INTLOCK(); \ 6389 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ 6390 HWIO_INTFREE();\ 6391 } while (0) 6392 6393 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff 6394 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 6395 6396 //// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// 6397 6398 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x00000554) 6399 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x00000554) 6400 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff 6401 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 6402 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ 6403 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) 6404 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ 6405 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 6406 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ 6407 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) 6408 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ 6409 do {\ 6410 HWIO_INTLOCK(); \ 6411 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ 6412 HWIO_INTFREE();\ 6413 } while (0) 6414 6415 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff 6416 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 6417 6418 //// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// 6419 6420 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x00000558) 6421 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x00000558) 6422 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff 6423 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 6424 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ 6425 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) 6426 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ 6427 in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 6428 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ 6429 out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) 6430 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ 6431 do {\ 6432 HWIO_INTLOCK(); \ 6433 out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ 6434 HWIO_INTFREE();\ 6435 } while (0) 6436 6437 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff 6438 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 6439 6440 //// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// 6441 6442 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x0000055c) 6443 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x0000055c) 6444 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff 6445 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 6446 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ 6447 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) 6448 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ 6449 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 6450 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ 6451 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) 6452 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ 6453 do {\ 6454 HWIO_INTLOCK(); \ 6455 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ 6456 HWIO_INTFREE();\ 6457 } while (0) 6458 6459 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff 6460 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 6461 6462 //// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// 6463 6464 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x00000560) 6465 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x00000560) 6466 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff 6467 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 6468 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ 6469 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) 6470 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ 6471 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 6472 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ 6473 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) 6474 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ 6475 do {\ 6476 HWIO_INTLOCK(); \ 6477 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ 6478 HWIO_INTFREE();\ 6479 } while (0) 6480 6481 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff 6482 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 6483 6484 //// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// 6485 6486 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x00000564) 6487 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x00000564) 6488 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff 6489 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 6490 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ 6491 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) 6492 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ 6493 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 6494 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ 6495 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) 6496 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ 6497 do {\ 6498 HWIO_INTLOCK(); \ 6499 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ 6500 HWIO_INTFREE();\ 6501 } while (0) 6502 6503 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff 6504 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 6505 6506 //// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// 6507 6508 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x00000568) 6509 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x00000568) 6510 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff 6511 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 6512 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ 6513 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) 6514 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ 6515 in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 6516 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ 6517 out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) 6518 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ 6519 do {\ 6520 HWIO_INTLOCK(); \ 6521 out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ 6522 HWIO_INTFREE();\ 6523 } while (0) 6524 6525 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff 6526 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 6527 6528 //// Register REO_R0_AGING_TIMESTAMP_IX_0 //// 6529 6530 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x0000056c) 6531 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x0000056c) 6532 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff 6533 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 6534 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ 6535 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) 6536 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ 6537 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 6538 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ 6539 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) 6540 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ 6541 do {\ 6542 HWIO_INTLOCK(); \ 6543 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ 6544 HWIO_INTFREE();\ 6545 } while (0) 6546 6547 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff 6548 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 6549 6550 //// Register REO_R0_AGING_TIMESTAMP_IX_1 //// 6551 6552 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x00000570) 6553 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x00000570) 6554 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff 6555 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 6556 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ 6557 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) 6558 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ 6559 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 6560 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ 6561 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) 6562 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ 6563 do {\ 6564 HWIO_INTLOCK(); \ 6565 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ 6566 HWIO_INTFREE();\ 6567 } while (0) 6568 6569 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff 6570 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 6571 6572 //// Register REO_R0_AGING_TIMESTAMP_IX_2 //// 6573 6574 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x00000574) 6575 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x00000574) 6576 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff 6577 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 6578 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ 6579 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) 6580 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ 6581 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 6582 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ 6583 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) 6584 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ 6585 do {\ 6586 HWIO_INTLOCK(); \ 6587 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ 6588 HWIO_INTFREE();\ 6589 } while (0) 6590 6591 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff 6592 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 6593 6594 //// Register REO_R0_AGING_TIMESTAMP_IX_3 //// 6595 6596 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x00000578) 6597 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x00000578) 6598 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff 6599 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 6600 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ 6601 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) 6602 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ 6603 in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 6604 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ 6605 out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) 6606 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ 6607 do {\ 6608 HWIO_INTLOCK(); \ 6609 out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ 6610 HWIO_INTFREE();\ 6611 } while (0) 6612 6613 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff 6614 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 6615 6616 //// Register REO_R0_AGING_CONTROL //// 6617 6618 #define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x0000057c) 6619 #define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x0000057c) 6620 #define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f 6621 #define HWIO_REO_R0_AGING_CONTROL_SHFT 0 6622 #define HWIO_REO_R0_AGING_CONTROL_IN(x) \ 6623 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) 6624 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ 6625 in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 6626 #define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ 6627 out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) 6628 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ 6629 do {\ 6630 HWIO_INTLOCK(); \ 6631 out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ 6632 HWIO_INTFREE();\ 6633 } while (0) 6634 6635 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f 6636 #define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 6637 6638 //// Register REO_R0_HIGH_MEMORY_THRESHOLD //// 6639 6640 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x00000580) 6641 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x00000580) 6642 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff 6643 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 6644 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ 6645 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) 6646 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ 6647 in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 6648 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ 6649 out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) 6650 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ 6651 do {\ 6652 HWIO_INTLOCK(); \ 6653 out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ 6654 HWIO_INTFREE();\ 6655 } while (0) 6656 6657 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff 6658 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 6659 6660 //// Register REO_R0_AC_BUFFERS_USED_IX_0 //// 6661 6662 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x00000584) 6663 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x00000584) 6664 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff 6665 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 6666 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ 6667 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) 6668 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ 6669 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 6670 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ 6671 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) 6672 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ 6673 do {\ 6674 HWIO_INTLOCK(); \ 6675 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ 6676 HWIO_INTFREE();\ 6677 } while (0) 6678 6679 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff 6680 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 6681 6682 //// Register REO_R0_AC_BUFFERS_USED_IX_1 //// 6683 6684 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x00000588) 6685 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x00000588) 6686 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff 6687 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 6688 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ 6689 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) 6690 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ 6691 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 6692 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ 6693 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) 6694 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ 6695 do {\ 6696 HWIO_INTLOCK(); \ 6697 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ 6698 HWIO_INTFREE();\ 6699 } while (0) 6700 6701 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff 6702 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 6703 6704 //// Register REO_R0_AC_BUFFERS_USED_IX_2 //// 6705 6706 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x0000058c) 6707 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x0000058c) 6708 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff 6709 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 6710 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ 6711 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) 6712 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ 6713 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 6714 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ 6715 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) 6716 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ 6717 do {\ 6718 HWIO_INTLOCK(); \ 6719 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ 6720 HWIO_INTFREE();\ 6721 } while (0) 6722 6723 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff 6724 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 6725 6726 //// Register REO_R0_AC_BUFFERS_USED_IX_3 //// 6727 6728 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x00000590) 6729 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x00000590) 6730 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff 6731 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 6732 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ 6733 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) 6734 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ 6735 in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 6736 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ 6737 out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) 6738 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ 6739 do {\ 6740 HWIO_INTLOCK(); \ 6741 out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ 6742 HWIO_INTFREE();\ 6743 } while (0) 6744 6745 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff 6746 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 6747 6748 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// 6749 6750 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x00000594) 6751 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x00000594) 6752 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff 6753 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 6754 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ 6755 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) 6756 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ 6757 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 6758 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ 6759 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) 6760 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ 6761 do {\ 6762 HWIO_INTLOCK(); \ 6763 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ 6764 HWIO_INTFREE();\ 6765 } while (0) 6766 6767 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff 6768 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 6769 6770 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// 6771 6772 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x00000598) 6773 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x00000598) 6774 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff 6775 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 6776 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ 6777 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) 6778 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ 6779 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 6780 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ 6781 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) 6782 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ 6783 do {\ 6784 HWIO_INTLOCK(); \ 6785 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ 6786 HWIO_INTFREE();\ 6787 } while (0) 6788 6789 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff 6790 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 6791 6792 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// 6793 6794 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x0000059c) 6795 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x0000059c) 6796 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff 6797 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 6798 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ 6799 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) 6800 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ 6801 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 6802 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ 6803 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) 6804 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ 6805 do {\ 6806 HWIO_INTLOCK(); \ 6807 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ 6808 HWIO_INTFREE();\ 6809 } while (0) 6810 6811 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff 6812 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 6813 6814 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// 6815 6816 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005a0) 6817 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005a0) 6818 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff 6819 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 6820 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ 6821 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) 6822 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ 6823 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 6824 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ 6825 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) 6826 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ 6827 do {\ 6828 HWIO_INTLOCK(); \ 6829 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ 6830 HWIO_INTFREE();\ 6831 } while (0) 6832 6833 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff 6834 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 6835 6836 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// 6837 6838 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x000005a4) 6839 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x000005a4) 6840 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff 6841 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 6842 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ 6843 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) 6844 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ 6845 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 6846 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ 6847 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) 6848 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ 6849 do {\ 6850 HWIO_INTLOCK(); \ 6851 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ 6852 HWIO_INTFREE();\ 6853 } while (0) 6854 6855 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff 6856 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 6857 6858 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// 6859 6860 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x000005a8) 6861 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x000005a8) 6862 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff 6863 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 6864 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ 6865 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) 6866 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ 6867 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 6868 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ 6869 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) 6870 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ 6871 do {\ 6872 HWIO_INTLOCK(); \ 6873 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ 6874 HWIO_INTFREE();\ 6875 } while (0) 6876 6877 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff 6878 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 6879 6880 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// 6881 6882 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x000005ac) 6883 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x000005ac) 6884 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff 6885 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 6886 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ 6887 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) 6888 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ 6889 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 6890 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ 6891 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) 6892 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ 6893 do {\ 6894 HWIO_INTLOCK(); \ 6895 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ 6896 HWIO_INTFREE();\ 6897 } while (0) 6898 6899 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff 6900 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 6901 6902 //// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// 6903 6904 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x000005b0) 6905 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x000005b0) 6906 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 6907 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 6908 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ 6909 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) 6910 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ 6911 in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 6912 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ 6913 out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) 6914 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ 6915 do {\ 6916 HWIO_INTLOCK(); \ 6917 out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ 6918 HWIO_INTFREE();\ 6919 } while (0) 6920 6921 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 6922 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 6923 6924 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// 6925 6926 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x000005b4) 6927 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x000005b4) 6928 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff 6929 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 6930 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ 6931 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) 6932 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ 6933 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 6934 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ 6935 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) 6936 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ 6937 do {\ 6938 HWIO_INTLOCK(); \ 6939 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ 6940 HWIO_INTFREE();\ 6941 } while (0) 6942 6943 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff 6944 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 6945 6946 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// 6947 6948 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x000005b8) 6949 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x000005b8) 6950 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff 6951 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 6952 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ 6953 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) 6954 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ 6955 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 6956 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ 6957 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) 6958 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ 6959 do {\ 6960 HWIO_INTLOCK(); \ 6961 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ 6962 HWIO_INTFREE();\ 6963 } while (0) 6964 6965 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff 6966 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 6967 6968 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// 6969 6970 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x000005bc) 6971 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x000005bc) 6972 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff 6973 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 6974 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ 6975 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) 6976 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ 6977 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 6978 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ 6979 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) 6980 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ 6981 do {\ 6982 HWIO_INTLOCK(); \ 6983 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ 6984 HWIO_INTFREE();\ 6985 } while (0) 6986 6987 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff 6988 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 6989 6990 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// 6991 6992 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x000005c0) 6993 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x000005c0) 6994 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff 6995 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 6996 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ 6997 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) 6998 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ 6999 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 7000 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ 7001 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) 7002 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ 7003 do {\ 7004 HWIO_INTLOCK(); \ 7005 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ 7006 HWIO_INTFREE();\ 7007 } while (0) 7008 7009 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff 7010 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 7011 7012 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// 7013 7014 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x000005c4) 7015 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x000005c4) 7016 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff 7017 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 7018 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ 7019 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) 7020 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ 7021 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 7022 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ 7023 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) 7024 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ 7025 do {\ 7026 HWIO_INTLOCK(); \ 7027 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ 7028 HWIO_INTFREE();\ 7029 } while (0) 7030 7031 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff 7032 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 7033 7034 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// 7035 7036 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x000005c8) 7037 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x000005c8) 7038 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff 7039 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 7040 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ 7041 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) 7042 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ 7043 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 7044 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ 7045 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) 7046 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ 7047 do {\ 7048 HWIO_INTLOCK(); \ 7049 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ 7050 HWIO_INTFREE();\ 7051 } while (0) 7052 7053 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff 7054 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 7055 7056 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// 7057 7058 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x000005cc) 7059 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x000005cc) 7060 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff 7061 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 7062 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ 7063 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) 7064 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ 7065 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 7066 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ 7067 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) 7068 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ 7069 do {\ 7070 HWIO_INTLOCK(); \ 7071 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ 7072 HWIO_INTFREE();\ 7073 } while (0) 7074 7075 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff 7076 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 7077 7078 //// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// 7079 7080 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x000005d0) 7081 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x000005d0) 7082 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff 7083 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 7084 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ 7085 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) 7086 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ 7087 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 7088 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ 7089 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) 7090 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ 7091 do {\ 7092 HWIO_INTLOCK(); \ 7093 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ 7094 HWIO_INTFREE();\ 7095 } while (0) 7096 7097 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff 7098 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 7099 7100 //// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// 7101 7102 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x000005d4) 7103 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x000005d4) 7104 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f 7105 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 7106 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ 7107 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) 7108 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ 7109 in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 7110 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ 7111 out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) 7112 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ 7113 do {\ 7114 HWIO_INTLOCK(); \ 7115 out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ 7116 HWIO_INTFREE();\ 7117 } while (0) 7118 7119 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 7120 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 7121 7122 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f 7123 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 7124 7125 //// Register REO_R0_GXI_TESTBUS_LOWER //// 7126 7127 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000005d8) 7128 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000005d8) 7129 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 7130 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 7131 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ 7132 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) 7133 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 7134 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 7135 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 7136 out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 7137 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 7138 do {\ 7139 HWIO_INTLOCK(); \ 7140 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ 7141 HWIO_INTFREE();\ 7142 } while (0) 7143 7144 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 7145 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 7146 7147 //// Register REO_R0_GXI_TESTBUS_UPPER //// 7148 7149 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000005dc) 7150 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000005dc) 7151 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 7152 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 7153 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ 7154 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) 7155 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 7156 in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 7157 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 7158 out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 7159 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 7160 do {\ 7161 HWIO_INTLOCK(); \ 7162 out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ 7163 HWIO_INTFREE();\ 7164 } while (0) 7165 7166 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 7167 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 7168 7169 //// Register REO_R0_GXI_SM_STATES_IX_0 //// 7170 7171 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000005e0) 7172 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000005e0) 7173 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 7174 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 7175 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ 7176 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) 7177 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 7178 in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 7179 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 7180 out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 7181 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 7182 do {\ 7183 HWIO_INTLOCK(); \ 7184 out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ 7185 HWIO_INTFREE();\ 7186 } while (0) 7187 7188 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 7189 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 7190 7191 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 7192 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 7193 7194 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 7195 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 7196 7197 //// Register REO_R0_GXI_END_OF_TEST_CHECK //// 7198 7199 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000005e4) 7200 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000005e4) 7201 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 7202 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 7203 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 7204 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) 7205 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 7206 in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 7207 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 7208 out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 7209 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7210 do {\ 7211 HWIO_INTLOCK(); \ 7212 out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 7213 HWIO_INTFREE();\ 7214 } while (0) 7215 7216 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7217 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7218 7219 //// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// 7220 7221 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000005e8) 7222 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000005e8) 7223 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 7224 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 7225 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 7226 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 7227 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 7228 in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 7229 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 7230 out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 7231 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 7232 do {\ 7233 HWIO_INTLOCK(); \ 7234 out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 7235 HWIO_INTFREE();\ 7236 } while (0) 7237 7238 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 7239 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 7240 7241 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 7242 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 7243 7244 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 7245 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 7246 7247 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 7248 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 7249 7250 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 7251 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 7252 7253 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 7254 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 7255 7256 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 7257 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 7258 7259 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 7260 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 7261 7262 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 7263 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 7264 7265 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 7266 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 7267 7268 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 7269 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 7270 7271 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 7272 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 7273 7274 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 7275 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 7276 7277 //// Register REO_R0_GXI_GXI_ERR_INTS //// 7278 7279 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000005ec) 7280 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000005ec) 7281 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 7282 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 7283 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ 7284 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) 7285 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 7286 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 7287 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 7288 out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 7289 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 7290 do {\ 7291 HWIO_INTLOCK(); \ 7292 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ 7293 HWIO_INTFREE();\ 7294 } while (0) 7295 7296 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 7297 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 7298 7299 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 7300 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 7301 7302 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 7303 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 7304 7305 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 7306 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 7307 7308 //// Register REO_R0_GXI_GXI_ERR_STATS //// 7309 7310 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000005f0) 7311 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000005f0) 7312 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 7313 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 7314 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ 7315 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) 7316 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 7317 in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 7318 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 7319 out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 7320 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 7321 do {\ 7322 HWIO_INTLOCK(); \ 7323 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ 7324 HWIO_INTFREE();\ 7325 } while (0) 7326 7327 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 7328 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 7329 7330 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 7331 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 7332 7333 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 7334 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 7335 7336 //// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// 7337 7338 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000005f4) 7339 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000005f4) 7340 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 7341 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 7342 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 7343 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 7344 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 7345 in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 7346 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 7347 out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 7348 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 7349 do {\ 7350 HWIO_INTLOCK(); \ 7351 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 7352 HWIO_INTFREE();\ 7353 } while (0) 7354 7355 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 7356 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 7357 7358 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7359 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 7360 7361 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 7362 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 7363 7364 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 7365 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 7366 7367 //// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// 7368 7369 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000005f8) 7370 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000005f8) 7371 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 7372 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 7373 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 7374 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 7375 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 7376 in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 7377 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 7378 out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 7379 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 7380 do {\ 7381 HWIO_INTLOCK(); \ 7382 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 7383 HWIO_INTFREE();\ 7384 } while (0) 7385 7386 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 7387 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 7388 7389 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 7390 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 7391 7392 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 7393 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 7394 7395 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 7396 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 7397 7398 //// Register REO_R0_GXI_GXI_MISC_CONTROL //// 7399 7400 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000005fc) 7401 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000005fc) 7402 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 7403 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 7404 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 7405 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) 7406 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 7407 in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 7408 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 7409 out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 7410 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 7411 do {\ 7412 HWIO_INTLOCK(); \ 7413 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 7414 HWIO_INTFREE();\ 7415 } while (0) 7416 7417 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 7418 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 7419 7420 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 7421 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 7422 7423 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 7424 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 7425 7426 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 7427 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 7428 7429 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 7430 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 7431 7432 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 7433 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 7434 7435 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 7436 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 7437 7438 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 7439 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 7440 7441 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 7442 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 7443 7444 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 7445 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 7446 7447 //// Register REO_R0_GXI_GXI_WDOG_CONTROL //// 7448 7449 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000600) 7450 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000600) 7451 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 7452 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 7453 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 7454 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) 7455 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 7456 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 7457 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 7458 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 7459 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 7460 do {\ 7461 HWIO_INTLOCK(); \ 7462 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 7463 HWIO_INTFREE();\ 7464 } while (0) 7465 7466 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 7467 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 7468 7469 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 7470 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 7471 7472 //// Register REO_R0_GXI_GXI_WDOG_STATUS //// 7473 7474 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000604) 7475 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000604) 7476 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 7477 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 7478 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 7479 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) 7480 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 7481 in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 7482 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 7483 out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 7484 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 7485 do {\ 7486 HWIO_INTLOCK(); \ 7487 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 7488 HWIO_INTFREE();\ 7489 } while (0) 7490 7491 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 7492 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 7493 7494 //// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// 7495 7496 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000608) 7497 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000608) 7498 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 7499 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 7500 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 7501 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 7502 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 7503 in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 7504 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 7505 out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 7506 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 7507 do {\ 7508 HWIO_INTLOCK(); \ 7509 out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 7510 HWIO_INTFREE();\ 7511 } while (0) 7512 7513 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 7514 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 7515 7516 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 7517 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 7518 7519 //// Register REO_R0_CACHE_CTL_CONFIG //// 7520 7521 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x0000060c) 7522 #define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x0000060c) 7523 #define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0x7fff7fff 7524 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 7525 #define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ 7526 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) 7527 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ 7528 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 7529 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ 7530 out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) 7531 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ 7532 do {\ 7533 HWIO_INTLOCK(); \ 7534 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ 7535 HWIO_INTFREE();\ 7536 } while (0) 7537 7538 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0x7f800000 7539 #define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x17 7540 7541 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00400000 7542 #define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x16 7543 7544 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00200000 7545 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x15 7546 7547 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00100000 7548 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x14 7549 7550 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00080000 7551 #define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x13 7552 7553 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00040000 7554 #define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x12 7555 7556 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00020000 7557 #define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x11 7558 7559 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00010000 7560 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x10 7561 7562 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x00007f00 7563 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x8 7564 7565 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000000ff 7566 #define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 7567 7568 //// Register REO_R0_CACHE_CTL_CONTROL //// 7569 7570 #define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x00000610) 7571 #define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x00000610) 7572 #define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000001 7573 #define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 7574 #define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ 7575 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) 7576 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ 7577 in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 7578 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ 7579 out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) 7580 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ 7581 do {\ 7582 HWIO_INTLOCK(); \ 7583 out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ 7584 HWIO_INTFREE();\ 7585 } while (0) 7586 7587 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 7588 #define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 7589 7590 //// Register REO_R0_CLK_GATE_CTRL //// 7591 7592 #define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000614) 7593 #define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000614) 7594 #define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff 7595 #define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 7596 #define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ 7597 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) 7598 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ 7599 in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 7600 #define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ 7601 out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) 7602 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ 7603 do {\ 7604 HWIO_INTLOCK(); \ 7605 out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ 7606 HWIO_INTFREE();\ 7607 } while (0) 7608 7609 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 7610 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 7611 7612 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 7613 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 7614 7615 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 7616 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 7617 7618 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 7619 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf 7620 7621 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 7622 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe 7623 7624 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 7625 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd 7626 7627 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK 0x00001000 7628 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT 0xc 7629 7630 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK 0x00000800 7631 #define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT 0xb 7632 7633 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 7634 #define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa 7635 7636 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff 7637 #define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 7638 7639 //// Register REO_R0_EVENTMASK_IX_0 //// 7640 7641 #define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x00000618) 7642 #define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x00000618) 7643 #define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff 7644 #define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 7645 #define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ 7646 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) 7647 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ 7648 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 7649 #define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ 7650 out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) 7651 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ 7652 do {\ 7653 HWIO_INTLOCK(); \ 7654 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ 7655 HWIO_INTFREE();\ 7656 } while (0) 7657 7658 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 7659 #define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 7660 7661 //// Register REO_R0_EVENTMASK_IX_1 //// 7662 7663 #define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x0000061c) 7664 #define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x0000061c) 7665 #define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff 7666 #define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 7667 #define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ 7668 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) 7669 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ 7670 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 7671 #define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ 7672 out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) 7673 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ 7674 do {\ 7675 HWIO_INTLOCK(); \ 7676 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ 7677 HWIO_INTFREE();\ 7678 } while (0) 7679 7680 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 7681 #define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 7682 7683 //// Register REO_R0_EVENTMASK_IX_2 //// 7684 7685 #define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x00000620) 7686 #define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x00000620) 7687 #define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff 7688 #define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 7689 #define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ 7690 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) 7691 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ 7692 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 7693 #define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ 7694 out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) 7695 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ 7696 do {\ 7697 HWIO_INTLOCK(); \ 7698 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ 7699 HWIO_INTFREE();\ 7700 } while (0) 7701 7702 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff 7703 #define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 7704 7705 //// Register REO_R0_EVENTMASK_IX_3 //// 7706 7707 #define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x00000624) 7708 #define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x00000624) 7709 #define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff 7710 #define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 7711 #define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ 7712 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) 7713 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ 7714 in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 7715 #define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ 7716 out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) 7717 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ 7718 do {\ 7719 HWIO_INTLOCK(); \ 7720 out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ 7721 HWIO_INTFREE();\ 7722 } while (0) 7723 7724 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff 7725 #define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 7726 7727 //// Register REO_R1_MISC_DEBUG_CTRL //// 7728 7729 #define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) 7730 #define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) 7731 #define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0x3fffffff 7732 #define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 7733 #define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ 7734 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) 7735 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ 7736 in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 7737 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ 7738 out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) 7739 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ 7740 do {\ 7741 HWIO_INTLOCK(); \ 7742 out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ 7743 HWIO_INTFREE();\ 7744 } while (0) 7745 7746 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 7747 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 7748 7749 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 7750 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa 7751 7752 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff 7753 #define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 7754 7755 //// Register REO_R1_MISC_PERF_DEBUG_CTRL //// 7756 7757 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) 7758 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) 7759 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff 7760 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 7761 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ 7762 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) 7763 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ 7764 in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 7765 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ 7766 out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) 7767 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ 7768 do {\ 7769 HWIO_INTLOCK(); \ 7770 out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ 7771 HWIO_INTFREE();\ 7772 } while (0) 7773 7774 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 7775 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc 7776 7777 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff 7778 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 7779 7780 //// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// 7781 7782 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) 7783 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) 7784 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x000003ff 7785 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 7786 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ 7787 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) 7788 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ 7789 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 7790 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ 7791 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) 7792 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ 7793 do {\ 7794 HWIO_INTLOCK(); \ 7795 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ 7796 HWIO_INTFREE();\ 7797 } while (0) 7798 7799 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000200 7800 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0x9 7801 7802 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000100 7803 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0x8 7804 7805 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000080 7806 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x7 7807 7808 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x0000007f 7809 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 7810 7811 //// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// 7812 7813 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) 7814 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) 7815 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff 7816 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 7817 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ 7818 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) 7819 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ 7820 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 7821 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ 7822 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) 7823 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ 7824 do {\ 7825 HWIO_INTLOCK(); \ 7826 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ 7827 HWIO_INTFREE();\ 7828 } while (0) 7829 7830 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff 7831 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 7832 7833 //// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// 7834 7835 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) 7836 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) 7837 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff 7838 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 7839 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ 7840 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) 7841 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ 7842 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 7843 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ 7844 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) 7845 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ 7846 do {\ 7847 HWIO_INTLOCK(); \ 7848 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ 7849 HWIO_INTFREE();\ 7850 } while (0) 7851 7852 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff 7853 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 7854 7855 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// 7856 7857 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) 7858 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) 7859 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff 7860 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 7861 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ 7862 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) 7863 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ 7864 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 7865 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ 7866 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) 7867 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ 7868 do {\ 7869 HWIO_INTLOCK(); \ 7870 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ 7871 HWIO_INTFREE();\ 7872 } while (0) 7873 7874 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff 7875 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 7876 7877 //// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// 7878 7879 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) 7880 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) 7881 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0x03ffffff 7882 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 7883 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ 7884 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) 7885 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ 7886 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 7887 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ 7888 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) 7889 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ 7890 do {\ 7891 HWIO_INTLOCK(); \ 7892 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ 7893 HWIO_INTFREE();\ 7894 } while (0) 7895 7896 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0x03ffffff 7897 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 7898 7899 //// Register REO_R1_CACHE_CTL_DEBUG_STM //// 7900 7901 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) 7902 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) 7903 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff 7904 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 7905 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ 7906 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) 7907 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ 7908 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 7909 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ 7910 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) 7911 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ 7912 do {\ 7913 HWIO_INTLOCK(); \ 7914 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ 7915 HWIO_INTFREE();\ 7916 } while (0) 7917 7918 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff 7919 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 7920 7921 //// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// 7922 7923 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) 7924 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) 7925 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0xffffffff 7926 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 7927 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ 7928 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) 7929 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ 7930 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 7931 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ 7932 out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) 7933 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ 7934 do {\ 7935 HWIO_INTLOCK(); \ 7936 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ 7937 HWIO_INTFREE();\ 7938 } while (0) 7939 7940 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK 0xff000000 7941 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT 0x18 7942 7943 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_BMSK 0x00ff0000 7944 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_SHFT 0x10 7945 7946 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0000ff00 7947 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0x8 7948 7949 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000000ff 7950 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 7951 7952 //// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// 7953 7954 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x00002024) 7955 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x00002024) 7956 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 7957 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 7958 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ 7959 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) 7960 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ 7961 in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 7962 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ 7963 out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) 7964 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7965 do {\ 7966 HWIO_INTLOCK(); \ 7967 out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ 7968 HWIO_INTFREE();\ 7969 } while (0) 7970 7971 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7972 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7973 7974 //// Register REO_R1_END_OF_TEST_CHECK //// 7975 7976 #define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002028) 7977 #define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002028) 7978 #define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 7979 #define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 7980 #define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ 7981 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) 7982 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ 7983 in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 7984 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ 7985 out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) 7986 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 7987 do {\ 7988 HWIO_INTLOCK(); \ 7989 out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ 7990 HWIO_INTFREE();\ 7991 } while (0) 7992 7993 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 7994 #define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 7995 7996 //// Register REO_R1_SM_ALL_IDLE //// 7997 7998 #define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x0000202c) 7999 #define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x0000202c) 8000 #define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 8001 #define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 8002 #define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ 8003 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) 8004 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ 8005 in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 8006 #define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ 8007 out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) 8008 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ 8009 do {\ 8010 HWIO_INTLOCK(); \ 8011 out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ 8012 HWIO_INTFREE();\ 8013 } while (0) 8014 8015 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 8016 #define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 8017 8018 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 8019 #define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 8020 8021 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 8022 #define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 8023 8024 //// Register REO_R1_TESTBUS_CTRL //// 8025 8026 #define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002030) 8027 #define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002030) 8028 #define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f 8029 #define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 8030 #define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ 8031 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) 8032 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ 8033 in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 8034 #define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ 8035 out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) 8036 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 8037 do {\ 8038 HWIO_INTLOCK(); \ 8039 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ 8040 HWIO_INTFREE();\ 8041 } while (0) 8042 8043 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f 8044 #define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 8045 8046 //// Register REO_R1_TESTBUS_LOWER //// 8047 8048 #define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002034) 8049 #define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002034) 8050 #define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff 8051 #define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 8052 #define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ 8053 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) 8054 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ 8055 in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 8056 #define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ 8057 out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) 8058 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ 8059 do {\ 8060 HWIO_INTLOCK(); \ 8061 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ 8062 HWIO_INTFREE();\ 8063 } while (0) 8064 8065 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 8066 #define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 8067 8068 //// Register REO_R1_TESTBUS_HIGHER //// 8069 8070 #define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002038) 8071 #define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002038) 8072 #define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff 8073 #define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 8074 #define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ 8075 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) 8076 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ 8077 in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 8078 #define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ 8079 out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) 8080 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ 8081 do {\ 8082 HWIO_INTLOCK(); \ 8083 out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ 8084 HWIO_INTFREE();\ 8085 } while (0) 8086 8087 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff 8088 #define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 8089 8090 //// Register REO_R1_SM_STATES_IX_0 //// 8091 8092 #define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x0000203c) 8093 #define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x0000203c) 8094 #define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff 8095 #define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 8096 #define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ 8097 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) 8098 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ 8099 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 8100 #define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ 8101 out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) 8102 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 8103 do {\ 8104 HWIO_INTLOCK(); \ 8105 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ 8106 HWIO_INTFREE();\ 8107 } while (0) 8108 8109 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff 8110 #define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 8111 8112 //// Register REO_R1_SM_STATES_IX_1 //// 8113 8114 #define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002040) 8115 #define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002040) 8116 #define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff 8117 #define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 8118 #define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ 8119 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) 8120 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ 8121 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 8122 #define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ 8123 out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) 8124 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 8125 do {\ 8126 HWIO_INTLOCK(); \ 8127 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ 8128 HWIO_INTFREE();\ 8129 } while (0) 8130 8131 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff 8132 #define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 8133 8134 //// Register REO_R1_SM_STATES_IX_2 //// 8135 8136 #define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x00002044) 8137 #define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x00002044) 8138 #define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff 8139 #define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 8140 #define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ 8141 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) 8142 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ 8143 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 8144 #define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ 8145 out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) 8146 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ 8147 do {\ 8148 HWIO_INTLOCK(); \ 8149 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ 8150 HWIO_INTFREE();\ 8151 } while (0) 8152 8153 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff 8154 #define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 8155 8156 //// Register REO_R1_SM_STATES_IX_3 //// 8157 8158 #define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002048) 8159 #define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002048) 8160 #define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff 8161 #define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 8162 #define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ 8163 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) 8164 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ 8165 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 8166 #define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ 8167 out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) 8168 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ 8169 do {\ 8170 HWIO_INTLOCK(); \ 8171 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ 8172 HWIO_INTFREE();\ 8173 } while (0) 8174 8175 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff 8176 #define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 8177 8178 //// Register REO_R1_SM_STATES_IX_4 //// 8179 8180 #define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x0000204c) 8181 #define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x0000204c) 8182 #define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff 8183 #define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 8184 #define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ 8185 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) 8186 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ 8187 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 8188 #define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ 8189 out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) 8190 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ 8191 do {\ 8192 HWIO_INTLOCK(); \ 8193 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ 8194 HWIO_INTFREE();\ 8195 } while (0) 8196 8197 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff 8198 #define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 8199 8200 //// Register REO_R1_SM_STATES_IX_5 //// 8201 8202 #define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002050) 8203 #define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002050) 8204 #define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff 8205 #define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 8206 #define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ 8207 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) 8208 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ 8209 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 8210 #define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ 8211 out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) 8212 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ 8213 do {\ 8214 HWIO_INTLOCK(); \ 8215 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ 8216 HWIO_INTFREE();\ 8217 } while (0) 8218 8219 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff 8220 #define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 8221 8222 //// Register REO_R1_SM_STATES_IX_6 //// 8223 8224 #define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x00002054) 8225 #define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x00002054) 8226 #define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff 8227 #define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 8228 #define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ 8229 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) 8230 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ 8231 in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 8232 #define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ 8233 out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) 8234 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ 8235 do {\ 8236 HWIO_INTLOCK(); \ 8237 out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ 8238 HWIO_INTFREE();\ 8239 } while (0) 8240 8241 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff 8242 #define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 8243 8244 //// Register REO_R1_IDLE_STATES_IX_0 //// 8245 8246 #define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002058) 8247 #define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002058) 8248 #define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff 8249 #define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 8250 #define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ 8251 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) 8252 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ 8253 in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 8254 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ 8255 out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) 8256 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ 8257 do {\ 8258 HWIO_INTLOCK(); \ 8259 out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ 8260 HWIO_INTFREE();\ 8261 } while (0) 8262 8263 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff 8264 #define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 8265 8266 //// Register REO_R1_INVALID_APB_ACCESS //// 8267 8268 #define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x0000205c) 8269 #define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x0000205c) 8270 #define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff 8271 #define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 8272 #define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ 8273 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) 8274 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ 8275 in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 8276 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ 8277 out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) 8278 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ 8279 do {\ 8280 HWIO_INTLOCK(); \ 8281 out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ 8282 HWIO_INTFREE();\ 8283 } while (0) 8284 8285 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 8286 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 8287 8288 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff 8289 #define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 8290 8291 //// Register REO_R2_RXDMA2REO0_RING_HP //// 8292 8293 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) 8294 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) 8295 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff 8296 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 8297 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ 8298 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) 8299 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ 8300 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 8301 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ 8302 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) 8303 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ 8304 do {\ 8305 HWIO_INTLOCK(); \ 8306 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ 8307 HWIO_INTFREE();\ 8308 } while (0) 8309 8310 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8311 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 8312 8313 //// Register REO_R2_RXDMA2REO0_RING_TP //// 8314 8315 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) 8316 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) 8317 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff 8318 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 8319 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ 8320 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) 8321 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ 8322 in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 8323 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ 8324 out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) 8325 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ 8326 do {\ 8327 HWIO_INTLOCK(); \ 8328 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ 8329 HWIO_INTFREE();\ 8330 } while (0) 8331 8332 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8333 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 8334 8335 //// Register REO_R2_RXDMA2REO1_RING_HP //// 8336 8337 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x) (x+0x00003008) 8338 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x) (x+0x00003008) 8339 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK 0x0000ffff 8340 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT 0 8341 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x) \ 8342 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK) 8343 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ 8344 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) 8345 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val) \ 8346 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val) 8347 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ 8348 do {\ 8349 HWIO_INTLOCK(); \ 8350 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \ 8351 HWIO_INTFREE();\ 8352 } while (0) 8353 8354 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8355 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT 0x0 8356 8357 //// Register REO_R2_RXDMA2REO1_RING_TP //// 8358 8359 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x) (x+0x0000300c) 8360 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x) (x+0x0000300c) 8361 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK 0x0000ffff 8362 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT 0 8363 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x) \ 8364 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK) 8365 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ 8366 in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) 8367 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val) \ 8368 out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val) 8369 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ 8370 do {\ 8371 HWIO_INTLOCK(); \ 8372 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \ 8373 HWIO_INTFREE();\ 8374 } while (0) 8375 8376 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8377 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT 0x0 8378 8379 //// Register REO_R2_RXDMA2REO2_RING_HP //// 8380 8381 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x) (x+0x00003010) 8382 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x) (x+0x00003010) 8383 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK 0x0000ffff 8384 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT 0 8385 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x) \ 8386 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK) 8387 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ 8388 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) 8389 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val) \ 8390 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val) 8391 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ 8392 do {\ 8393 HWIO_INTLOCK(); \ 8394 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \ 8395 HWIO_INTFREE();\ 8396 } while (0) 8397 8398 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8399 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT 0x0 8400 8401 //// Register REO_R2_RXDMA2REO2_RING_TP //// 8402 8403 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x) (x+0x00003014) 8404 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x) (x+0x00003014) 8405 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK 0x0000ffff 8406 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT 0 8407 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x) \ 8408 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK) 8409 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ 8410 in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) 8411 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val) \ 8412 out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val) 8413 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ 8414 do {\ 8415 HWIO_INTLOCK(); \ 8416 out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \ 8417 HWIO_INTFREE();\ 8418 } while (0) 8419 8420 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8421 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT 0x0 8422 8423 //// Register REO_R2_WBM2REO_LINK_RING_HP //// 8424 8425 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003018) 8426 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003018) 8427 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff 8428 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 8429 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ 8430 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) 8431 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ 8432 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 8433 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ 8434 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) 8435 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ 8436 do {\ 8437 HWIO_INTLOCK(); \ 8438 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ 8439 HWIO_INTFREE();\ 8440 } while (0) 8441 8442 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8443 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 8444 8445 //// Register REO_R2_WBM2REO_LINK_RING_TP //// 8446 8447 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000301c) 8448 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000301c) 8449 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff 8450 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 8451 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ 8452 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) 8453 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ 8454 in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 8455 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ 8456 out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) 8457 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ 8458 do {\ 8459 HWIO_INTLOCK(); \ 8460 out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ 8461 HWIO_INTFREE();\ 8462 } while (0) 8463 8464 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8465 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 8466 8467 //// Register REO_R2_REO_CMD_RING_HP //// 8468 8469 #define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003020) 8470 #define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003020) 8471 #define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff 8472 #define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 8473 #define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ 8474 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) 8475 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ 8476 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 8477 #define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ 8478 out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) 8479 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ 8480 do {\ 8481 HWIO_INTLOCK(); \ 8482 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ 8483 HWIO_INTFREE();\ 8484 } while (0) 8485 8486 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8487 #define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 8488 8489 //// Register REO_R2_REO_CMD_RING_TP //// 8490 8491 #define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003024) 8492 #define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003024) 8493 #define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff 8494 #define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 8495 #define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ 8496 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) 8497 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ 8498 in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 8499 #define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ 8500 out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) 8501 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ 8502 do {\ 8503 HWIO_INTLOCK(); \ 8504 out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ 8505 HWIO_INTFREE();\ 8506 } while (0) 8507 8508 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8509 #define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 8510 8511 //// Register REO_R2_SW2REO_RING_HP //// 8512 8513 #define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003028) 8514 #define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003028) 8515 #define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff 8516 #define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 8517 #define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ 8518 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) 8519 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ 8520 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 8521 #define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ 8522 out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) 8523 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ 8524 do {\ 8525 HWIO_INTLOCK(); \ 8526 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ 8527 HWIO_INTFREE();\ 8528 } while (0) 8529 8530 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8531 #define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 8532 8533 //// Register REO_R2_SW2REO_RING_TP //// 8534 8535 #define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000302c) 8536 #define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000302c) 8537 #define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff 8538 #define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 8539 #define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ 8540 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) 8541 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ 8542 in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 8543 #define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ 8544 out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) 8545 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ 8546 do {\ 8547 HWIO_INTLOCK(); \ 8548 out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ 8549 HWIO_INTFREE();\ 8550 } while (0) 8551 8552 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8553 #define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 8554 8555 //// Register REO_R2_REO2SW1_RING_HP //// 8556 8557 #define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003030) 8558 #define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003030) 8559 #define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x0000ffff 8560 #define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 8561 #define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ 8562 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) 8563 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ 8564 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 8565 #define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ 8566 out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) 8567 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ 8568 do {\ 8569 HWIO_INTLOCK(); \ 8570 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ 8571 HWIO_INTFREE();\ 8572 } while (0) 8573 8574 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8575 #define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 8576 8577 //// Register REO_R2_REO2SW1_RING_TP //// 8578 8579 #define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x00003034) 8580 #define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x00003034) 8581 #define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x0000ffff 8582 #define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 8583 #define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ 8584 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) 8585 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ 8586 in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 8587 #define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ 8588 out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) 8589 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ 8590 do {\ 8591 HWIO_INTLOCK(); \ 8592 out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ 8593 HWIO_INTFREE();\ 8594 } while (0) 8595 8596 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8597 #define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 8598 8599 //// Register REO_R2_REO2SW2_RING_HP //// 8600 8601 #define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003038) 8602 #define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003038) 8603 #define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x0000ffff 8604 #define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 8605 #define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ 8606 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) 8607 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ 8608 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 8609 #define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ 8610 out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) 8611 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ 8612 do {\ 8613 HWIO_INTLOCK(); \ 8614 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ 8615 HWIO_INTFREE();\ 8616 } while (0) 8617 8618 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8619 #define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 8620 8621 //// Register REO_R2_REO2SW2_RING_TP //// 8622 8623 #define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x0000303c) 8624 #define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x0000303c) 8625 #define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x0000ffff 8626 #define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 8627 #define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ 8628 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) 8629 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ 8630 in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 8631 #define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ 8632 out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) 8633 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ 8634 do {\ 8635 HWIO_INTLOCK(); \ 8636 out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ 8637 HWIO_INTFREE();\ 8638 } while (0) 8639 8640 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8641 #define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 8642 8643 //// Register REO_R2_REO2SW3_RING_HP //// 8644 8645 #define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003040) 8646 #define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003040) 8647 #define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x0000ffff 8648 #define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 8649 #define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ 8650 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) 8651 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ 8652 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 8653 #define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ 8654 out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) 8655 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ 8656 do {\ 8657 HWIO_INTLOCK(); \ 8658 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ 8659 HWIO_INTFREE();\ 8660 } while (0) 8661 8662 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8663 #define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 8664 8665 //// Register REO_R2_REO2SW3_RING_TP //// 8666 8667 #define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x00003044) 8668 #define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x00003044) 8669 #define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x0000ffff 8670 #define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 8671 #define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ 8672 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) 8673 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ 8674 in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 8675 #define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ 8676 out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) 8677 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ 8678 do {\ 8679 HWIO_INTLOCK(); \ 8680 out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ 8681 HWIO_INTFREE();\ 8682 } while (0) 8683 8684 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8685 #define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 8686 8687 //// Register REO_R2_REO2SW4_RING_HP //// 8688 8689 #define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003048) 8690 #define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003048) 8691 #define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x0000ffff 8692 #define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 8693 #define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ 8694 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) 8695 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ 8696 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 8697 #define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ 8698 out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) 8699 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ 8700 do {\ 8701 HWIO_INTLOCK(); \ 8702 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ 8703 HWIO_INTFREE();\ 8704 } while (0) 8705 8706 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8707 #define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 8708 8709 //// Register REO_R2_REO2SW4_RING_TP //// 8710 8711 #define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x0000304c) 8712 #define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x0000304c) 8713 #define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x0000ffff 8714 #define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 8715 #define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ 8716 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) 8717 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ 8718 in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 8719 #define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ 8720 out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) 8721 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ 8722 do {\ 8723 HWIO_INTLOCK(); \ 8724 out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ 8725 HWIO_INTFREE();\ 8726 } while (0) 8727 8728 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8729 #define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 8730 8731 //// Register REO_R2_REO2TCL_RING_HP //// 8732 8733 #define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003050) 8734 #define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003050) 8735 #define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x0000ffff 8736 #define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 8737 #define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ 8738 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) 8739 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ 8740 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 8741 #define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ 8742 out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) 8743 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ 8744 do {\ 8745 HWIO_INTLOCK(); \ 8746 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ 8747 HWIO_INTFREE();\ 8748 } while (0) 8749 8750 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8751 #define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 8752 8753 //// Register REO_R2_REO2TCL_RING_TP //// 8754 8755 #define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x00003054) 8756 #define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x00003054) 8757 #define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x0000ffff 8758 #define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 8759 #define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ 8760 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) 8761 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ 8762 in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 8763 #define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ 8764 out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) 8765 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ 8766 do {\ 8767 HWIO_INTLOCK(); \ 8768 out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ 8769 HWIO_INTFREE();\ 8770 } while (0) 8771 8772 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8773 #define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 8774 8775 //// Register REO_R2_REO2FW_RING_HP //// 8776 8777 #define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003058) 8778 #define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003058) 8779 #define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x0000ffff 8780 #define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 8781 #define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ 8782 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) 8783 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ 8784 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 8785 #define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ 8786 out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) 8787 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ 8788 do {\ 8789 HWIO_INTLOCK(); \ 8790 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ 8791 HWIO_INTFREE();\ 8792 } while (0) 8793 8794 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8795 #define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 8796 8797 //// Register REO_R2_REO2FW_RING_TP //// 8798 8799 #define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x0000305c) 8800 #define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x0000305c) 8801 #define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x0000ffff 8802 #define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 8803 #define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ 8804 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) 8805 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ 8806 in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 8807 #define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ 8808 out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) 8809 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ 8810 do {\ 8811 HWIO_INTLOCK(); \ 8812 out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ 8813 HWIO_INTFREE();\ 8814 } while (0) 8815 8816 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8817 #define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 8818 8819 //// Register REO_R2_REO_RELEASE_RING_HP //// 8820 8821 #define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003060) 8822 #define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003060) 8823 #define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff 8824 #define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 8825 #define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ 8826 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) 8827 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ 8828 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 8829 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ 8830 out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) 8831 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ 8832 do {\ 8833 HWIO_INTLOCK(); \ 8834 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ 8835 HWIO_INTFREE();\ 8836 } while (0) 8837 8838 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8839 #define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 8840 8841 //// Register REO_R2_REO_RELEASE_RING_TP //// 8842 8843 #define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003064) 8844 #define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003064) 8845 #define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff 8846 #define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 8847 #define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ 8848 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) 8849 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ 8850 in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 8851 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ 8852 out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) 8853 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ 8854 do {\ 8855 HWIO_INTLOCK(); \ 8856 out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ 8857 HWIO_INTFREE();\ 8858 } while (0) 8859 8860 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8861 #define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 8862 8863 //// Register REO_R2_REO_STATUS_RING_HP //// 8864 8865 #define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003068) 8866 #define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003068) 8867 #define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff 8868 #define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 8869 #define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ 8870 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) 8871 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ 8872 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 8873 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ 8874 out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) 8875 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ 8876 do {\ 8877 HWIO_INTLOCK(); \ 8878 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ 8879 HWIO_INTFREE();\ 8880 } while (0) 8881 8882 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 8883 #define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 8884 8885 //// Register REO_R2_REO_STATUS_RING_TP //// 8886 8887 #define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x0000306c) 8888 #define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x0000306c) 8889 #define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff 8890 #define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 8891 #define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ 8892 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) 8893 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ 8894 in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 8895 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ 8896 out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) 8897 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ 8898 do {\ 8899 HWIO_INTLOCK(); \ 8900 out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ 8901 HWIO_INTFREE();\ 8902 } while (0) 8903 8904 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 8905 #define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 8906 8907 8908 #endif 8909 8910