1 /*
2  * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 ///////////////////////////////////////////////////////////////////////////////////////////////
20 //
21 // wcss_seq_hwiobase.h : automatically generated by Autoseq  3.1 8/17/2017
22 // User Name:gunjans
23 //
24 // !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
25 //
26 ///////////////////////////////////////////////////////////////////////////////////////////////
27 
28 #ifndef __WCSS_SEQ_BASE_H__
29 #define __WCSS_SEQ_BASE_H__
30 
31 #ifdef SCALE_INCLUDES
32 	#include "HALhwio.h"
33 #else
34 	#include "msmhwio.h"
35 #endif
36 
37 
38 ///////////////////////////////////////////////////////////////////////////////////////////////
39 // Instance Relative Offsets from Block wcss
40 ///////////////////////////////////////////////////////////////////////////////////////////////
41 
42 #define SEQ_WCSS_ECAHB_OFFSET                                        0x00008400
43 #define SEQ_WCSS_ECAHB_TSLV_OFFSET                                   0x00009000
44 #define SEQ_WCSS_UMAC_NOC_OFFSET                                     0x00140000
45 #define SEQ_WCSS_MPSS_OFFSET                                         0x00200000
46 #define SEQ_WCSS_MPSS_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET          0x00200000
47 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_OFFSET                     0x00280000
48 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET          0x00281800
49 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET            0x00281c00
50 #define SEQ_WCSS_PHYA_OFFSET                                         0x00400000
51 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                 0x00400000
52 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET                       0x00480000
53 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                 0x00480400
54 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                 0x00480800
55 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                 0x00480c00
56 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                 0x00481000
57 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                 0x00481400
58 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET            0x00481800
59 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET              0x00481c00
60 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC5_REG_MAP_OFFSET                 0x00482c00
61 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET                        0x00484000
62 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET                       0x00488000
63 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA1_REG_MAP_OFFSET             0x00490000
64 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET                       0x00500000
65 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET                       0x00520000
66 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET                       0x00528000
67 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET              0x00530000
68 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET                      0x005a0000
69 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET                     0x005c0000
70 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET             0x005d4000
71 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET         0x005d4000
72 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET      0x005d4300
73 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET      0x005d4800
74 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET     0x005d4c00
75 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET    0x005d5000
76 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET  0x005d5040
77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET    0x005d5080
78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET    0x005d50c0
79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400
80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000
81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040
82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080
83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d60c0
84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6100
85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6140
86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6200
87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800
88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840
89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6880
90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d68c0
91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900
92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940
93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00
94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET     0x005d7c00
95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET              0x005d8000
96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET        0x005d8000
97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET        0x005d8400
98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET  0x005d8800
99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880
100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0
101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET  0x005d8940
102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET  0x005d8980
103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET              0x005dc000
104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET       0x005dc000
105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET       0x005dc400
106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET       0x005dc600
107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET  0x005dc800
108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dc840
109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET  0x005dc880
110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET  0x005dc8c0
111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET              0x005e0000
112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000
113 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x005e0400
114 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x005e0800
115 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000
116 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
117 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x005e1600
118 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x005e1640
119 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000
120 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x005e2400
121 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x005e2500
122 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x005e2580
123 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x005e2590
124 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x005e2600
125 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x005e26c0
126 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x005e2740
127 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x005e2768
128 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000
129 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000
130 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x005e8400
131 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x005e8800
132 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9180
133 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9480
134 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x005e9600
135 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x005e9640
136 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
137 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x005ea400
138 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x005ea500
139 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x005ea580
140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x005ea590
141 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x005ea600
142 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x005ea6c0
143 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x005ea740
144 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x005ea768
145 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000
146 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000
147 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x005f0400
148 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x005f0800
149 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000
150 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300
151 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x005f1600
152 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x005f1640
153 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000
154 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400
155 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x005f2500
156 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580
157 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x005f2590
158 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x005f2600
159 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x005f26c0
160 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x005f2740
161 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x005f2768
162 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000
163 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000
164 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400
165 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800
166 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9180
167 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9480
168 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x005f9600
169 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x005f9640
170 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000
171 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x005fa400
172 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x005fa500
173 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x005fa580
174 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x005fa590
175 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x005fa600
176 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x005fa6c0
177 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x005fa740
178 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x005fa768
179 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000
180 #define SEQ_WCSS_PHYB_OFFSET                                         0x00600000
181 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET               0x00600000
182 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET                     0x00680000
183 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET               0x00680400
184 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET               0x00680800
185 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET               0x00680c00
186 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET               0x00681000
187 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET               0x00681400
188 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET          0x00681800
189 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET            0x00681c00
190 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET               0x00682c00
191 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET                      0x00684000
192 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET                     0x00688000
193 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET                     0x00700000
194 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET                     0x00720000
195 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET                     0x00728000
196 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET            0x00730000
197 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET                    0x007a0000
198 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET                   0x007c0000
199 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET           0x007d4000
200 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET       0x007d4000
201 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET    0x007d4300
202 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET    0x007d4800
203 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET   0x007d4c00
204 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET  0x007d5000
205 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x007d5040
206 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET  0x007d5080
207 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET  0x007d50c0
208 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x007d5400
209 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000
210 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040
211 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080
212 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d60c0
213 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6100
214 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6140
215 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x007d6200
216 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800
217 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840
218 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d6880
219 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d68c0
220 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900
221 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940
222 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00
223 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET   0x007d7c00
224 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET            0x007d8000
225 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET      0x007d8000
226 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET      0x007d8400
227 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x007d8800
228 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x007d8880
229 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x007d88c0
230 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x007d8940
231 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x007d8980
232 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET            0x007dc000
233 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET     0x007dc000
234 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET     0x007dc400
235 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET     0x007dc600
236 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x007dc800
237 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x007dc840
238 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x007dc880
239 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x007dc8c0
240 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET            0x007e0000
241 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x007e0000
242 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x007e0400
243 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x007e0800
244 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x007e1000
245 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300
246 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x007e1600
247 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x007e1640
248 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000
249 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x007e2400
250 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x007e2500
251 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x007e2580
252 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x007e2590
253 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x007e2600
254 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x007e26c0
255 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x007e2740
256 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x007e2768
257 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x007e4000
258 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x007e8000
259 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x007e8400
260 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x007e8800
261 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9180
262 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9480
263 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x007e9600
264 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x007e9640
265 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000
266 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x007ea400
267 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x007ea500
268 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x007ea580
269 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x007ea590
270 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x007ea600
271 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x007ea6c0
272 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x007ea740
273 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x007ea768
274 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x007ec000
275 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x007f0000
276 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x007f0400
277 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x007f0800
278 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x007f1000
279 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300
280 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x007f1600
281 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x007f1640
282 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000
283 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400
284 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x007f2500
285 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580
286 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x007f2590
287 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x007f2600
288 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x007f26c0
289 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x007f2740
290 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x007f2768
291 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000
292 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000
293 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400
294 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800
295 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9180
296 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9480
297 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x007f9600
298 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x007f9640
299 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000
300 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x007fa400
301 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x007fa500
302 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x007fa580
303 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x007fa590
304 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x007fa600
305 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x007fa6c0
306 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x007fa740
307 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x007fa768
308 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x007fc000
309 #define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
310 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET                           0x00a00000
311 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000
312 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000
313 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000
314 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000
315 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000
316 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000
317 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000
318 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000
319 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000
320 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000
321 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000
322 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000
323 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000
324 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000
325 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000
326 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000
327 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000
328 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000
329 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000
330 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000
331 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000
332 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000
333 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000
334 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000
335 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET        0x00a18000
336 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
337 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
338 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                0x00a22000
339 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET            0x00a24000
340 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET                 0x00a26000
341 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET                 0x00a28000
342 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET                 0x00a2a000
343 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET                          0x00a30000
344 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET                                 0x00a34000
345 #define SEQ_WCSS_UMAC_REO_REG_OFFSET                                 0x00a38000
346 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET                                 0x00a3c000
347 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET                           0x00a40000
348 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET                             0x00a44000
349 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET                      0x00a47000
350 #define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET                             0x00a4a000
351 #define SEQ_WCSS_WMAC0_OFFSET                                        0x00a80000
352 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET                            0x00a80000
353 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET                          0x00a83000
354 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET                          0x00a86000
355 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET                           0x00a89000
356 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET                          0x00a8c000
357 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET                          0x00a8f000
358 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET                           0x00a92000
359 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET                          0x00a95000
360 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET                   0x00a98000
361 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET                            0x00a9b000
362 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET                          0x00a9e000
363 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET                   0x00aa1000
364 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET                            0x00aa4000
365 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET                         0x00aa7000
366 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET                          0x00aaa000
367 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET                            0x00ab0000
368 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET                            0x00ab3000
369 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET                         0x00ab6000
370 #define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET                           0x00ab9000
371 #define SEQ_WCSS_WMAC1_OFFSET                                        0x00b00000
372 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET                            0x00b00000
373 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET                          0x00b03000
374 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET                          0x00b06000
375 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET                           0x00b09000
376 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET                          0x00b0c000
377 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET                          0x00b0f000
378 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET                           0x00b12000
379 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET                          0x00b15000
380 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET                   0x00b18000
381 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET                            0x00b1b000
382 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET                          0x00b1e000
383 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET                   0x00b21000
384 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET                            0x00b24000
385 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET                         0x00b27000
386 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET                          0x00b2a000
387 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET                            0x00b30000
388 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET                            0x00b33000
389 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET                         0x00b36000
390 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET                           0x00b39000
391 #define SEQ_WCSS_APB_TSLV_OFFSET                                     0x00b40000
392 #define SEQ_WCSS_WCMN_OFFSET                                         0x00b50000
393 #define SEQ_WCSS_WFSS_PMM_OFFSET                                     0x00b60000
394 #define SEQ_WCSS_PMM_OFFSET                                          0x00b70000
395 #define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
396 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET                      0x00b90000
397 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET                         0x00b91000
398 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET                            0x00b92000
399 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET                    0x00b94000
400 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
401 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
402 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET  0x00b98000
403 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280
404 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000
405 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET     0x00b99000
406 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280
407 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000
408 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET        0x00b9a000
409 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET                  0x00b9b000
410 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET                        0x00b9c000
411 #define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET                        0x00ba0000
412 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bb0000
413 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET                   0x00bb1000
414 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET                        0x00bb6000
415 #define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET                      0x00bbe000
416 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bc0000
417 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET                   0x00bc1000
418 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET                        0x00bc6000
419 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET                      0x00bce000
420 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET                       0x00bf0000
421 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00bf1000
422 #define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c10000
423 #define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00c20000
424 #define SEQ_WCSS_CC_OFFSET                                           0x00c30000
425 #define SEQ_WCSS_ACMT_OFFSET                                         0x00c40000
426 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET                                  0x00d00000
427 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET                      0x00d00000
428 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET                                 0x00d80000
429 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET                     0x00d80000
430 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET                   0x00d90000
431 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET                 0x00da0000
432 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET                         0x00da1000
433 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET                         0x00da2000
434 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET                         0x00da3000
435 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET                    0x00db0000
436 
437 
438 ///////////////////////////////////////////////////////////////////////////////////////////////
439 // Instance Relative Offsets from Block mpss_top
440 ///////////////////////////////////////////////////////////////////////////////////////////////
441 
442 #define SEQ_MPSS_TOP_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET           0x00000000
443 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_OFFSET                      0x00080000
444 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET           0x00081800
445 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET             0x00081c00
446 
447 
448 ///////////////////////////////////////////////////////////////////////////////////////////////
449 // Instance Relative Offsets from Block wfax_top
450 ///////////////////////////////////////////////////////////////////////////////////////////////
451 
452 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                  0x00000000
453 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET                        0x00080000
454 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                  0x00080400
455 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                  0x00080800
456 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                  0x00080c00
457 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                  0x00081000
458 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                  0x00081400
459 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET             0x00081800
460 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET               0x00081c00
461 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC5_REG_MAP_OFFSET                  0x00082c00
462 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET                         0x00084000
463 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET                        0x00088000
464 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA1_REG_MAP_OFFSET              0x00090000
465 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET                        0x00100000
466 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x00120000
467 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET                        0x00128000
468 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET               0x00130000
469 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET                       0x001a0000
470 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      0x001c0000
471 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET              0x001d4000
472 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET          0x001d4000
473 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET       0x001d4300
474 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET       0x001d4800
475 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET      0x001d4c00
476 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET     0x001d5000
477 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET   0x001d5040
478 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET     0x001d5080
479 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET     0x001d50c0
480 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400
481 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000
482 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040
483 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080
484 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0
485 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100
486 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140
487 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200
488 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800
489 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840
490 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880
491 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0
492 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900
493 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940
494 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00
495 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET      0x001d7c00
496 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET               0x001d8000
497 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET         0x001d8000
498 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET         0x001d8400
499 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET   0x001d8800
500 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x001d8880
501 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0
502 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET   0x001d8940
503 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET   0x001d8980
504 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET               0x001dc000
505 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET        0x001dc000
506 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET        0x001dc400
507 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET        0x001dc600
508 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET   0x001dc800
509 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840
510 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET   0x001dc880
511 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET   0x001dc8c0
512 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET               0x001e0000
513 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET  0x001e0000
514 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400
515 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800
516 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000
517 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
518 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x001e1600
519 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET  0x001e1640
520 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
521 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400
522 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500
523 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580
524 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x001e2590
525 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x001e2600
526 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x001e26c0
527 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740
528 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x001e2768
529 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000
530 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET  0x001e8000
531 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400
532 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800
533 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180
534 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480
535 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x001e9600
536 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET  0x001e9640
537 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
538 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400
539 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500
540 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580
541 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x001ea590
542 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x001ea600
543 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea6c0
544 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740
545 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea768
546 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000
547 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET  0x001f0000
548 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400
549 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800
550 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000
551 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
552 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x001f1600
553 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET  0x001f1640
554 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
555 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400
556 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500
557 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580
558 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x001f2590
559 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x001f2600
560 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x001f26c0
561 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740
562 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x001f2768
563 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000
564 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET  0x001f8000
565 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
566 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800
567 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180
568 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480
569 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x001f9600
570 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET  0x001f9640
571 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000
572 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400
573 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500
574 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580
575 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x001fa590
576 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x001fa600
577 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa6c0
578 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740
579 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa768
580 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000
581 
582 
583 ///////////////////////////////////////////////////////////////////////////////////////////////
584 // Instance Relative Offsets from Block rfa_from_wsi
585 ///////////////////////////////////////////////////////////////////////////////////////////////
586 
587 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
588 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
589 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET                       0x00014300
590 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014800
591 #define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET                      0x00014c00
592 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BS_OFFSET                     0x00015000
593 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BIST_OFFSET                   0x00015040
594 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_PC_OFFSET                     0x00015080
595 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_AC_OFFSET                     0x000150c0
596 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET                0x00015400
597 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016000
598 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016040
599 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016080
600 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET                 0x000160c0
601 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET               0x00016100
602 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET                 0x00016140
603 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET                 0x00016200
604 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET                 0x00016800
605 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET               0x00016840
606 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00016880
607 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x000168c0
608 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00016900
609 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x00016940
610 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET                 0x00016a00
611 #define SEQ_RFA_FROM_WSI_RFA_CMN_DRM_REG_OFFSET                      0x00017c00
612 #define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET                               0x00018000
613 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET                         0x00018000
614 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET                         0x00018400
615 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET                   0x00018800
616 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET                 0x00018880
617 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET                 0x000188c0
618 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET                   0x00018940
619 #define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET                   0x00018980
620 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
621 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET                        0x0001c000
622 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH1_OFFSET                        0x0001c400
623 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH0_OFFSET                        0x0001c600
624 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET                   0x0001c800
625 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET                 0x0001c840
626 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET                   0x0001c880
627 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET                   0x0001c8c0
628 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
629 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET                  0x00020000
630 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET                0x00020400
631 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET                0x00020800
632 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET                0x00021000
633 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET                0x00021300
634 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET              0x00021600
635 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_2G_CH0_OFFSET                  0x00021640
636 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET                 0x00022000
637 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET               0x00022400
638 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH0_OFFSET               0x00022500
639 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET                 0x00022580
640 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET           0x00022590
641 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET        0x00022600
642 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET       0x000226c0
643 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH0_OFFSET                 0x00022740
644 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET       0x00022768
645 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET                 0x00024000
646 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET                  0x00028000
647 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET                0x00028400
648 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET                0x00028800
649 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET                0x00029180
650 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET                0x00029480
651 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET              0x00029600
652 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_5G_CH0_OFFSET                  0x00029640
653 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET                 0x0002a000
654 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET               0x0002a400
655 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH0_OFFSET               0x0002a500
656 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET                 0x0002a580
657 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET           0x0002a590
658 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET        0x0002a600
659 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET       0x0002a6c0
660 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH0_OFFSET                 0x0002a740
661 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET       0x0002a768
662 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET                 0x0002c000
663 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET                  0x00030000
664 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET                0x00030400
665 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET                0x00030800
666 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET                0x00031000
667 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET                0x00031300
668 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET              0x00031600
669 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_2G_CH1_OFFSET                  0x00031640
670 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET                 0x00032000
671 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET               0x00032400
672 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH1_OFFSET               0x00032500
673 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET                 0x00032580
674 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET           0x00032590
675 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET        0x00032600
676 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET       0x000326c0
677 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_2G_CH1_OFFSET                 0x00032740
678 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET       0x00032768
679 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET                 0x00034000
680 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET                  0x00038000
681 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET                0x00038400
682 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET                0x00038800
683 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET                0x00039180
684 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET                0x00039480
685 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET              0x00039600
686 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_5G_CH1_OFFSET                  0x00039640
687 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET                 0x0003a000
688 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET               0x0003a400
689 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH1_OFFSET               0x0003a500
690 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET                 0x0003a580
691 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET           0x0003a590
692 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET        0x0003a600
693 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET       0x0003a6c0
694 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_5G_CH1_OFFSET                 0x0003a740
695 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET       0x0003a768
696 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET                 0x0003c000
697 
698 
699 ///////////////////////////////////////////////////////////////////////////////////////////////
700 // Instance Relative Offsets from Block rfa_cmn
701 ///////////////////////////////////////////////////////////////////////////////////////////////
702 
703 #define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
704 #define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
705 #define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000800
706 #define SEQ_RFA_CMN_BTFMPLL_OFFSET                                   0x00000c00
707 #define SEQ_RFA_CMN_BBPLL_BS_OFFSET                                  0x00001000
708 #define SEQ_RFA_CMN_BBPLL_BIST_OFFSET                                0x00001040
709 #define SEQ_RFA_CMN_BBPLL_PC_OFFSET                                  0x00001080
710 #define SEQ_RFA_CMN_BBPLL_AC_OFFSET                                  0x000010c0
711 #define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET                             0x00001400
712 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002000
713 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002040
714 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002080
715 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x000020c0
716 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002100
717 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x00002140
718 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET                              0x00002200
719 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00002800
720 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00002840
721 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00002880
722 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x000028c0
723 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00002900
724 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x00002940
725 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET                              0x00002a00
726 #define SEQ_RFA_CMN_DRM_REG_OFFSET                                   0x00003c00
727 
728 
729 ///////////////////////////////////////////////////////////////////////////////////////////////
730 // Instance Relative Offsets from Block rfa_fm
731 ///////////////////////////////////////////////////////////////////////////////////////////////
732 
733 #define SEQ_RFA_FM_FM_MC_OFFSET                                      0x00000000
734 #define SEQ_RFA_FM_FM_RX_OFFSET                                      0x00000400
735 #define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET                                0x00000800
736 #define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET                              0x00000880
737 #define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET                              0x000008c0
738 #define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET                                0x00000940
739 #define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET                                0x00000980
740 
741 
742 ///////////////////////////////////////////////////////////////////////////////////////////////
743 // Instance Relative Offsets from Block rfa_bt
744 ///////////////////////////////////////////////////////////////////////////////////////////////
745 
746 #define SEQ_RFA_BT_BT_CH2_OFFSET                                     0x00000000
747 #define SEQ_RFA_BT_BT_CH1_OFFSET                                     0x00000400
748 #define SEQ_RFA_BT_BT_CH0_OFFSET                                     0x00000600
749 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET                                0x00000800
750 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET                              0x00000840
751 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET                                0x00000880
752 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET                                0x000008c0
753 
754 
755 ///////////////////////////////////////////////////////////////////////////////////////////////
756 // Instance Relative Offsets from Block rfa_wl
757 ///////////////////////////////////////////////////////////////////////////////////////////////
758 
759 #define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET                               0x00000000
760 #define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET                             0x00000400
761 #define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET                             0x00000800
762 #define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET                             0x00001000
763 #define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET                             0x00001300
764 #define SEQ_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET                           0x00001600
765 #define SEQ_RFA_WL_WL_LO_2G_CH0_OFFSET                               0x00001640
766 #define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET                              0x00002000
767 #define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET                            0x00002400
768 #define SEQ_RFA_WL_RBIST_RX_2G_CH0_OFFSET                            0x00002500
769 #define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET                              0x00002580
770 #define SEQ_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET                        0x00002590
771 #define SEQ_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET                     0x00002600
772 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET                    0x000026c0
773 #define SEQ_RFA_WL_WL_ADC_2G_CH0_OFFSET                              0x00002740
774 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET                    0x00002768
775 #define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET                              0x00004000
776 #define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET                               0x00008000
777 #define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET                             0x00008400
778 #define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET                             0x00008800
779 #define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET                             0x00009180
780 #define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET                             0x00009480
781 #define SEQ_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET                           0x00009600
782 #define SEQ_RFA_WL_WL_LO_5G_CH0_OFFSET                               0x00009640
783 #define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET                              0x0000a000
784 #define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET                            0x0000a400
785 #define SEQ_RFA_WL_RBIST_RX_5G_CH0_OFFSET                            0x0000a500
786 #define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET                              0x0000a580
787 #define SEQ_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET                        0x0000a590
788 #define SEQ_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET                     0x0000a600
789 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET                    0x0000a6c0
790 #define SEQ_RFA_WL_WL_ADC_5G_CH0_OFFSET                              0x0000a740
791 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET                    0x0000a768
792 #define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET                              0x0000c000
793 #define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET                               0x00010000
794 #define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET                             0x00010400
795 #define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET                             0x00010800
796 #define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET                             0x00011000
797 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET                             0x00011300
798 #define SEQ_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET                           0x00011600
799 #define SEQ_RFA_WL_WL_LO_2G_CH1_OFFSET                               0x00011640
800 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET                              0x00012000
801 #define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET                            0x00012400
802 #define SEQ_RFA_WL_RBIST_RX_2G_CH1_OFFSET                            0x00012500
803 #define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET                              0x00012580
804 #define SEQ_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET                        0x00012590
805 #define SEQ_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET                     0x00012600
806 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET                    0x000126c0
807 #define SEQ_RFA_WL_WL_ADC_2G_CH1_OFFSET                              0x00012740
808 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET                    0x00012768
809 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET                              0x00014000
810 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET                               0x00018000
811 #define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET                             0x00018400
812 #define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET                             0x00018800
813 #define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET                             0x00019180
814 #define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET                             0x00019480
815 #define SEQ_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET                           0x00019600
816 #define SEQ_RFA_WL_WL_LO_5G_CH1_OFFSET                               0x00019640
817 #define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET                              0x0001a000
818 #define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET                            0x0001a400
819 #define SEQ_RFA_WL_RBIST_RX_5G_CH1_OFFSET                            0x0001a500
820 #define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET                              0x0001a580
821 #define SEQ_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET                        0x0001a590
822 #define SEQ_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET                     0x0001a600
823 #define SEQ_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET                    0x0001a6c0
824 #define SEQ_RFA_WL_WL_ADC_5G_CH1_OFFSET                              0x0001a740
825 #define SEQ_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET                    0x0001a768
826 #define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET                              0x0001c000
827 
828 
829 ///////////////////////////////////////////////////////////////////////////////////////////////
830 // Instance Relative Offsets from Block wfax_top_b
831 ///////////////////////////////////////////////////////////////////////////////////////////////
832 
833 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET              0x00000000
834 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET                    0x00080000
835 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET              0x00080400
836 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET              0x00080800
837 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET              0x00080c00
838 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET              0x00081000
839 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET              0x00081400
840 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET         0x00081800
841 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET           0x00081c00
842 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET              0x00082c00
843 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET                     0x00084000
844 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET                    0x00088000
845 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET                    0x00100000
846 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET                    0x00120000
847 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET                    0x00128000
848 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET           0x00130000
849 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET                   0x001a0000
850 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET                  0x001c0000
851 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET          0x001d4000
852 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET      0x001d4000
853 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET   0x001d4300
854 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET   0x001d4800
855 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET  0x001d4c00
856 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x001d5000
857 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x001d5040
858 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x001d5080
859 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x001d50c0
860 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400
861 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000
862 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040
863 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080
864 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0
865 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100
866 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140
867 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200
868 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800
869 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840
870 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880
871 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0
872 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900
873 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940
874 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00
875 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET  0x001d7c00
876 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET           0x001d8000
877 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET     0x001d8000
878 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET     0x001d8400
879 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x001d8800
880 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x001d8880
881 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0
882 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x001d8940
883 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x001d8980
884 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET           0x001dc000
885 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET    0x001dc000
886 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET    0x001dc400
887 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET    0x001dc600
888 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dc800
889 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840
890 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dc880
891 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dc8c0
892 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET           0x001e0000
893 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000
894 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400
895 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800
896 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000
897 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
898 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH0_OFFSET 0x001e1600
899 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH0_OFFSET 0x001e1640
900 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
901 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400
902 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500
903 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580
904 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH0_OFFSET 0x001e2590
905 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH0_OFFSET 0x001e2600
906 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH0_OFFSET 0x001e26c0
907 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH0_OFFSET 0x001e2740
908 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH0_OFFSET 0x001e2768
909 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x001e4000
910 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000
911 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400
912 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800
913 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180
914 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480
915 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH0_OFFSET 0x001e9600
916 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH0_OFFSET 0x001e9640
917 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
918 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400
919 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500
920 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580
921 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH0_OFFSET 0x001ea590
922 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH0_OFFSET 0x001ea600
923 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea6c0
924 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH0_OFFSET 0x001ea740
925 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH0_OFFSET 0x001ea768
926 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x001ec000
927 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000
928 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400
929 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800
930 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000
931 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
932 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_2G_CH1_OFFSET 0x001f1600
933 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_2G_CH1_OFFSET 0x001f1640
934 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
935 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400
936 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500
937 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580
938 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_2G_CH1_OFFSET 0x001f2590
939 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_2G_CH1_OFFSET 0x001f2600
940 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_2G_CH1_OFFSET 0x001f26c0
941 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_2G_CH1_OFFSET 0x001f2740
942 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_2G_CH1_OFFSET 0x001f2768
943 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000
944 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
945 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
946 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800
947 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180
948 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480
949 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_5G_CH1_OFFSET 0x001f9600
950 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_5G_CH1_OFFSET 0x001f9640
951 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000
952 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400
953 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500
954 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580
955 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_CALIB_5G_CH1_OFFSET 0x001fa590
956 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_REGARRAY_5G_CH1_OFFSET 0x001fa600
957 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa6c0
958 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_5G_CH1_OFFSET 0x001fa740
959 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BB_CLKGEN_5G_CH1_OFFSET 0x001fa768
960 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x001fc000
961 
962 
963 ///////////////////////////////////////////////////////////////////////////////////////////////
964 // Instance Relative Offsets from Block umac_top_reg
965 ///////////////////////////////////////////////////////////////////////////////////////////////
966 
967 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET                        0x00000000
968 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
969 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
970 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
971 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
972 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
973 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
974 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
975 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
976 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
977 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
978 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
979 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
980 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
981 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
982 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
983 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
984 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
985 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
986 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
987 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
988 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
989 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
990 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
991 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
992 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET     0x00018000
993 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET                          0x00020000
994 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET              0x00020000
995 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET             0x00022000
996 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET         0x00024000
997 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET              0x00026000
998 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET              0x00028000
999 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET              0x0002a000
1000 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET                       0x00030000
1001 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET                              0x00034000
1002 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET                              0x00038000
1003 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET                              0x0003c000
1004 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET                        0x00040000
1005 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET                          0x00044000
1006 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET                   0x00047000
1007 #define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0004a000
1008 
1009 
1010 ///////////////////////////////////////////////////////////////////////////////////////////////
1011 // Instance Relative Offsets from Block wfss_ce_reg
1012 ///////////////////////////////////////////////////////////////////////////////////////////////
1013 
1014 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET             0x00000000
1015 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET             0x00001000
1016 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET             0x00002000
1017 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET             0x00003000
1018 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET             0x00004000
1019 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET             0x00005000
1020 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET             0x00006000
1021 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET             0x00007000
1022 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET             0x00008000
1023 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET             0x00009000
1024 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET             0x0000a000
1025 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET             0x0000b000
1026 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET             0x0000c000
1027 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET             0x0000d000
1028 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET             0x0000e000
1029 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET             0x0000f000
1030 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET             0x00010000
1031 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET             0x00011000
1032 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET             0x00012000
1033 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET             0x00013000
1034 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET            0x00014000
1035 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET            0x00015000
1036 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET            0x00016000
1037 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET            0x00017000
1038 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET                    0x00018000
1039 
1040 
1041 ///////////////////////////////////////////////////////////////////////////////////////////////
1042 // Instance Relative Offsets from Block cxc_top_reg
1043 ///////////////////////////////////////////////////////////////////////////////////////////////
1044 
1045 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET                           0x00000000
1046 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                          0x00002000
1047 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET                      0x00004000
1048 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET                           0x00006000
1049 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET                           0x00008000
1050 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET                           0x0000a000
1051 
1052 
1053 ///////////////////////////////////////////////////////////////////////////////////////////////
1054 // Instance Relative Offsets from Block wmac_top_reg
1055 ///////////////////////////////////////////////////////////////////////////////////////////////
1056 
1057 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET                          0x00000000
1058 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET                        0x00003000
1059 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET                        0x00006000
1060 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET                         0x00009000
1061 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET                        0x0000c000
1062 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET                        0x0000f000
1063 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET                         0x00012000
1064 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET                        0x00015000
1065 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET                 0x00018000
1066 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0001b000
1067 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET                        0x0001e000
1068 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET                 0x00021000
1069 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET                          0x00024000
1070 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET                       0x00027000
1071 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET                        0x0002a000
1072 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET                          0x00030000
1073 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET                          0x00033000
1074 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET                       0x00036000
1075 #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET                         0x00039000
1076 
1077 
1078 ///////////////////////////////////////////////////////////////////////////////////////////////
1079 // Instance Relative Offsets from Block wcssdbg_napier
1080 ///////////////////////////////////////////////////////////////////////////////////////////////
1081 
1082 #define SEQ_WCSSDBG_NAPIER_ROM_WCSS_DBG_DAPROM_OFFSET                0x00000000
1083 #define SEQ_WCSSDBG_NAPIER_CSR_WCSS_DBG_CSR_OFFSET                   0x00001000
1084 #define SEQ_WCSSDBG_NAPIER_TSGEN_CXTSGEN_OFFSET                      0x00002000
1085 #define SEQ_WCSSDBG_NAPIER_CTIDBG_QC_CTI_24T_8CH_OFFSET              0x00004000
1086 #define SEQ_WCSSDBG_NAPIER_CTINOC_QC_CTI_8T_8CH_OFFSET               0x00005000
1087 #define SEQ_WCSSDBG_NAPIER_CTIIRQ_QC_CTI_32T_8CH_OFFSET              0x00006000
1088 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000
1089 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280
1090 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000
1091 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000
1092 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280
1093 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000
1094 #define SEQ_WCSSDBG_NAPIER_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET  0x0000a000
1095 #define SEQ_WCSSDBG_NAPIER_FUN_CXATBFUNNEL_128W8SP_OFFSET            0x0000b000
1096 #define SEQ_WCSSDBG_NAPIER_TMC_CXTMC_F128W8K_OFFSET                  0x0000c000
1097 #define SEQ_WCSSDBG_NAPIER_UMAC_NOC_UMAC_NOC_OFFSET                  0x00010000
1098 #define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET        0x00020000
1099 #define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_8T_8CH_OFFSET             0x00021000
1100 #define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET                  0x00026000
1101 #define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_M3_AHB_AP_OFFSET                0x0002e000
1102 #define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET        0x00030000
1103 #define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_8T_8CH_OFFSET             0x00031000
1104 #define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET                  0x00036000
1105 #define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_M3_AHB_AP_OFFSET                0x0003e000
1106 #define SEQ_WCSSDBG_NAPIER_UMAC_CPU_M3_AHB_AP_OFFSET                 0x00060000
1107 #define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET                        0x00061000
1108 
1109 
1110 ///////////////////////////////////////////////////////////////////////////////////////////////
1111 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
1112 ///////////////////////////////////////////////////////////////////////////////////////////////
1113 
1114 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
1115 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
1116 
1117 
1118 ///////////////////////////////////////////////////////////////////////////////////////////////
1119 // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd
1120 ///////////////////////////////////////////////////////////////////////////////////////////////
1121 
1122 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280
1123 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000
1124 
1125 
1126 ///////////////////////////////////////////////////////////////////////////////////////////////
1127 // Instance Relative Offsets from Block qdsp6ss_public
1128 ///////////////////////////////////////////////////////////////////////////////////////////////
1129 
1130 #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET                        0x00000000
1131 
1132 
1133 ///////////////////////////////////////////////////////////////////////////////////////////////
1134 // Instance Relative Offsets from Block qdsp6ss_private
1135 ///////////////////////////////////////////////////////////////////////////////////////////////
1136 
1137 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET                       0x00000000
1138 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET                     0x00010000
1139 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET                   0x00020000
1140 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET                           0x00021000
1141 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET                           0x00022000
1142 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET                           0x00023000
1143 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET                      0x00030000
1144 
1145 
1146 #endif
1147 
1148