1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 8/17/2017 22 // User Name:gunjans 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 29 #define __MAC_TCL_REG_SEQ_REG_H__ 30 31 #include "seq_hwio.h" 32 #include "mac_tcl_reg_seq_hwiobase.h" 33 #ifdef SCALE_INCLUDES 34 #include "HALhwio.h" 35 #else 36 #include "msmhwio.h" 37 #endif 38 39 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 // Register Data for Block MAC_TCL_REG 42 /////////////////////////////////////////////////////////////////////////////////////////////// 43 44 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 45 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 48 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 49 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 50 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 51 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 52 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 53 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 55 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 56 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 57 do {\ 58 HWIO_INTLOCK(); \ 59 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 60 HWIO_INTFREE();\ 61 } while (0) 62 63 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 65 66 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 67 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 68 69 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 70 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 73 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 74 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 75 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 76 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 77 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 78 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 80 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 81 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 82 do {\ 83 HWIO_INTLOCK(); \ 84 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 85 HWIO_INTFREE();\ 86 } while (0) 87 88 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 90 91 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 92 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 93 94 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 95 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 98 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 99 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 100 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 101 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 102 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 103 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 105 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 106 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 107 do {\ 108 HWIO_INTLOCK(); \ 109 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 110 HWIO_INTFREE();\ 111 } while (0) 112 113 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 115 116 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 117 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 118 119 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 120 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 123 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 124 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 125 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 126 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 127 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 128 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 130 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 131 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 132 do {\ 133 HWIO_INTLOCK(); \ 134 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 135 HWIO_INTFREE();\ 136 } while (0) 137 138 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 140 141 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 142 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 143 144 //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// 145 146 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) 147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) 148 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 149 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 150 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ 151 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) 152 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ 153 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ 155 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) 156 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ 157 do {\ 158 HWIO_INTLOCK(); \ 159 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ 160 HWIO_INTFREE();\ 161 } while (0) 162 163 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 165 166 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 167 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 168 169 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 170 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 173 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x003fffff 174 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 175 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 176 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 177 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 178 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 180 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 181 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 182 do {\ 183 HWIO_INTLOCK(); \ 184 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 185 HWIO_INTFREE();\ 186 } while (0) 187 188 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00200000 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x15 190 191 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00100000 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x14 193 194 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00080000 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x13 196 197 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FSE_CACHE_FAILURES_EN_BMSK 0x00040000 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FSE_CACHE_FAILURES_EN_SHFT 0x12 199 200 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ASE_CACHE_FAILURES_EN_BMSK 0x00020000 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ASE_CACHE_FAILURES_EN_SHFT 0x11 202 203 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 205 206 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 208 209 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc 211 212 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 214 215 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 217 218 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 220 221 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 223 224 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 226 227 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 229 230 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 232 233 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 234 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 235 236 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 237 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 238 239 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 240 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 241 242 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 243 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 244 245 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 246 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 247 248 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 249 250 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 251 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 252 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00003fff 253 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 254 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 255 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 256 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 257 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 258 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 259 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 260 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 261 do {\ 262 HWIO_INTLOCK(); \ 263 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 264 HWIO_INTFREE();\ 265 } while (0) 266 267 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 268 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd 269 270 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 271 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc 272 273 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 274 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 275 276 //// Register TCL_R0_TCL2FW_RING_CTRL //// 277 278 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 279 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 280 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 281 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 282 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 283 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 284 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 285 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 286 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 287 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 288 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 289 do {\ 290 HWIO_INTLOCK(); \ 291 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 292 HWIO_INTFREE();\ 293 } while (0) 294 295 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 296 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 297 298 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 299 300 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 301 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 302 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 303 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 304 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 305 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 306 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 307 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 308 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 309 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 310 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 311 do {\ 312 HWIO_INTLOCK(); \ 313 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 314 HWIO_INTFREE();\ 315 } while (0) 316 317 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 318 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 319 320 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 321 322 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 323 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 324 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 325 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 326 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 327 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 328 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 329 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 330 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 331 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 332 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 333 do {\ 334 HWIO_INTLOCK(); \ 335 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 336 HWIO_INTFREE();\ 337 } while (0) 338 339 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 340 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 341 342 //// Register TCL_R0_GEN_CTRL //// 343 344 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 345 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 346 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb 347 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 348 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 349 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 350 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 351 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 352 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 353 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 354 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 355 do {\ 356 HWIO_INTLOCK(); \ 357 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 358 HWIO_INTFREE();\ 359 } while (0) 360 361 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 362 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 363 364 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 365 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 366 367 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 368 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 369 370 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 371 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 372 373 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 374 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 375 376 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 377 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 378 379 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 380 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 381 382 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 383 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 384 385 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 386 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 387 388 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 389 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 390 391 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 392 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 393 394 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 395 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 396 397 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 398 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 399 400 //// Register TCL_R0_DSCP_TID_MAP_n //// 401 402 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) 403 #define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) 404 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 405 #define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 406 #define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 407 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ 408 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) 409 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ 410 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) 411 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ 412 out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) 413 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ 414 do {\ 415 HWIO_INTLOCK(); \ 416 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ 417 HWIO_INTFREE();\ 418 } while (0) 419 420 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff 421 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 422 423 //// Register TCL_R0_PCP_TID_MAP //// 424 425 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) 426 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) 427 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 428 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 429 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 430 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 431 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 432 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 433 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 434 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 435 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 436 do {\ 437 HWIO_INTLOCK(); \ 438 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 439 HWIO_INTFREE();\ 440 } while (0) 441 442 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 443 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 444 445 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 446 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 447 448 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 449 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 450 451 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 452 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 453 454 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 455 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 456 457 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 458 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 459 460 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 461 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 462 463 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 464 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 465 466 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 467 468 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) 469 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) 470 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 471 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 472 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 473 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 474 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 475 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 476 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 477 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 478 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 479 do {\ 480 HWIO_INTLOCK(); \ 481 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 482 HWIO_INTFREE();\ 483 } while (0) 484 485 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 486 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 487 488 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 489 490 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) 491 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) 492 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 493 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 494 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 495 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 496 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 497 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 498 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 499 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 500 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 501 do {\ 502 HWIO_INTLOCK(); \ 503 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 504 HWIO_INTFREE();\ 505 } while (0) 506 507 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 508 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 509 510 //// Register TCL_R0_ASE_HASH_KEY_64 //// 511 512 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) 513 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) 514 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 515 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 516 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 517 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 518 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 519 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 520 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 521 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 522 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 523 do {\ 524 HWIO_INTLOCK(); \ 525 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 526 HWIO_INTFREE();\ 527 } while (0) 528 529 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 530 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 531 532 //// Register TCL_R0_FSE_HASH_KEY_31_0 //// 533 534 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x000004bc) 535 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x000004bc) 536 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff 537 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 538 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ 539 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) 540 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ 541 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 542 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ 543 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) 544 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ 545 do {\ 546 HWIO_INTLOCK(); \ 547 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ 548 HWIO_INTFREE();\ 549 } while (0) 550 551 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 552 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 553 554 //// Register TCL_R0_FSE_HASH_KEY_63_32 //// 555 556 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x000004c0) 557 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x000004c0) 558 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff 559 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 560 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ 561 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) 562 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ 563 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 564 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ 565 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) 566 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ 567 do {\ 568 HWIO_INTLOCK(); \ 569 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ 570 HWIO_INTFREE();\ 571 } while (0) 572 573 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 574 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 575 576 //// Register TCL_R0_FSE_HASH_KEY_95_64 //// 577 578 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x000004c4) 579 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x000004c4) 580 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff 581 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 582 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ 583 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) 584 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ 585 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 586 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ 587 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) 588 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ 589 do {\ 590 HWIO_INTLOCK(); \ 591 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ 592 HWIO_INTFREE();\ 593 } while (0) 594 595 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff 596 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 597 598 //// Register TCL_R0_FSE_HASH_KEY_127_96 //// 599 600 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x000004c8) 601 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x000004c8) 602 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff 603 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 604 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ 605 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) 606 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ 607 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 608 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ 609 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) 610 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ 611 do {\ 612 HWIO_INTLOCK(); \ 613 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ 614 HWIO_INTFREE();\ 615 } while (0) 616 617 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff 618 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 619 620 //// Register TCL_R0_FSE_HASH_KEY_159_128 //// 621 622 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x000004cc) 623 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x000004cc) 624 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff 625 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 626 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ 627 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) 628 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ 629 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 630 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ 631 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) 632 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ 633 do {\ 634 HWIO_INTLOCK(); \ 635 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ 636 HWIO_INTFREE();\ 637 } while (0) 638 639 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff 640 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 641 642 //// Register TCL_R0_FSE_HASH_KEY_191_160 //// 643 644 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x000004d0) 645 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x000004d0) 646 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff 647 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 648 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ 649 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) 650 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ 651 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 652 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ 653 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) 654 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ 655 do {\ 656 HWIO_INTLOCK(); \ 657 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ 658 HWIO_INTFREE();\ 659 } while (0) 660 661 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff 662 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 663 664 //// Register TCL_R0_FSE_HASH_KEY_223_192 //// 665 666 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x000004d4) 667 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x000004d4) 668 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff 669 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 670 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ 671 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) 672 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ 673 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 674 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ 675 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) 676 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ 677 do {\ 678 HWIO_INTLOCK(); \ 679 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ 680 HWIO_INTFREE();\ 681 } while (0) 682 683 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff 684 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 685 686 //// Register TCL_R0_FSE_HASH_KEY_255_224 //// 687 688 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x000004d8) 689 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x000004d8) 690 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff 691 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 692 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ 693 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) 694 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ 695 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 696 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ 697 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) 698 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ 699 do {\ 700 HWIO_INTLOCK(); \ 701 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ 702 HWIO_INTFREE();\ 703 } while (0) 704 705 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff 706 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 707 708 //// Register TCL_R0_FSE_HASH_KEY_287_256 //// 709 710 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x000004dc) 711 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x000004dc) 712 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff 713 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 714 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ 715 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) 716 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ 717 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 718 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ 719 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) 720 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ 721 do {\ 722 HWIO_INTLOCK(); \ 723 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ 724 HWIO_INTFREE();\ 725 } while (0) 726 727 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff 728 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 729 730 //// Register TCL_R0_FSE_HASH_KEY_314_288 //// 731 732 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x000004e0) 733 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x000004e0) 734 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff 735 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 736 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ 737 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) 738 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ 739 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 740 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ 741 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) 742 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ 743 do {\ 744 HWIO_INTLOCK(); \ 745 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ 746 HWIO_INTFREE();\ 747 } while (0) 748 749 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff 750 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 751 752 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 753 754 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004e4) 755 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004e4) 756 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x007ffdfc 757 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 758 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 759 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 760 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 761 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 762 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 763 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 764 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 765 do {\ 766 HWIO_INTLOCK(); \ 767 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 768 HWIO_INTFREE();\ 769 } while (0) 770 771 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 772 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 773 774 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 775 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 776 777 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 778 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe 779 780 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 781 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 782 783 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 784 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 785 786 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 787 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 788 789 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 790 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 791 792 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 793 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 794 795 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 796 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 797 798 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 799 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 800 801 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 802 803 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004e8) 804 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004e8) 805 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 806 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 807 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 808 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 809 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 810 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 811 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 812 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 813 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 814 do {\ 815 HWIO_INTLOCK(); \ 816 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 817 HWIO_INTFREE();\ 818 } while (0) 819 820 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 821 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 822 823 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 824 825 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004ec) 826 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004ec) 827 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 828 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 829 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 830 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 831 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 832 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 833 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 834 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 835 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 836 do {\ 837 HWIO_INTLOCK(); \ 838 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 839 HWIO_INTFREE();\ 840 } while (0) 841 842 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 843 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 844 845 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 846 847 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004f0) 848 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004f0) 849 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 850 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 851 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 852 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 853 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 854 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 855 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 856 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 857 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 858 do {\ 859 HWIO_INTLOCK(); \ 860 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 861 HWIO_INTFREE();\ 862 } while (0) 863 864 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 865 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 866 867 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 868 869 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004f4) 870 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004f4) 871 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 872 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 873 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 874 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 875 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 876 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 877 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 878 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 879 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 880 do {\ 881 HWIO_INTLOCK(); \ 882 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 883 HWIO_INTFREE();\ 884 } while (0) 885 886 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 887 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 888 889 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 890 891 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004f8) 892 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004f8) 893 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 894 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 895 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 896 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 897 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 898 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 899 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 900 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 901 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 902 do {\ 903 HWIO_INTLOCK(); \ 904 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 905 HWIO_INTFREE();\ 906 } while (0) 907 908 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 909 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 910 911 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 912 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 913 914 //// Register TCL_R0_TID_MAP_PRTY //// 915 916 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004fc) 917 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004fc) 918 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 919 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 920 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 921 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 922 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 923 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 924 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 925 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 926 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 927 do {\ 928 HWIO_INTLOCK(); \ 929 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 930 HWIO_INTFREE();\ 931 } while (0) 932 933 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 934 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 935 936 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 937 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 938 939 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 940 941 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000500) 942 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000500) 943 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 944 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 945 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 946 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 947 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 948 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 949 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 950 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 951 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 952 do {\ 953 HWIO_INTLOCK(); \ 954 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 955 HWIO_INTFREE();\ 956 } while (0) 957 958 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 959 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 960 961 //// Register TCL_R0_WATCHDOG //// 962 963 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x00000504) 964 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x00000504) 965 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 966 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 967 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 968 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 969 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 970 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 971 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 972 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 973 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 974 do {\ 975 HWIO_INTLOCK(); \ 976 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 977 HWIO_INTFREE();\ 978 } while (0) 979 980 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 981 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 982 983 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 984 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 985 986 //// Register TCL_R0_CLKGATE_DISABLE //// 987 988 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000508) 989 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000508) 990 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 991 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 992 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 993 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 994 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 995 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 996 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 997 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 998 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 999 do {\ 1000 HWIO_INTLOCK(); \ 1001 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 1002 HWIO_INTFREE();\ 1003 } while (0) 1004 1005 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 1006 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 1007 1008 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 1009 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 1010 1011 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 1012 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 1013 1014 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 1015 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 1016 1017 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 1018 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 1019 1020 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 1021 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 1022 1023 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 1024 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 1025 1026 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 1027 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 1028 1029 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 1030 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 1031 1032 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 1033 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 1034 1035 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 1036 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 1037 1038 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 1039 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 1040 1041 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 1042 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 1043 1044 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 1045 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 1046 1047 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 1048 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 1049 1050 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 1051 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 1052 1053 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 1054 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 1055 1056 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 1057 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 1058 1059 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 1060 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 1061 1062 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 1063 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 1064 1065 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 1066 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 1067 1068 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 1069 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 1070 1071 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 1072 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 1073 1074 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 1075 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 1076 1077 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 1078 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 1079 1080 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 1081 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 1082 1083 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 1084 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 1085 1086 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 1087 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 1088 1089 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 1090 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 1091 1092 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 1093 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 1094 1095 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_BMSK 0x00000002 1096 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_SHFT 0x1 1097 1098 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 1099 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 1100 1101 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 1102 1103 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x0000050c) 1104 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x0000050c) 1105 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 1106 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1107 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1108 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1109 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1110 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1111 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1112 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1113 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1114 do {\ 1115 HWIO_INTLOCK(); \ 1116 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1117 HWIO_INTFREE();\ 1118 } while (0) 1119 1120 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1121 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1122 1123 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1124 1125 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000510) 1126 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000510) 1127 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 1128 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1129 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1130 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1131 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1132 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1133 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1134 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1135 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1136 do {\ 1137 HWIO_INTLOCK(); \ 1138 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1139 HWIO_INTFREE();\ 1140 } while (0) 1141 1142 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1143 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1144 1145 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1146 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1147 1148 //// Register TCL_R0_SW2TCL1_RING_ID //// 1149 1150 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x00000514) 1151 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x00000514) 1152 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1153 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1154 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1155 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1156 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1157 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1158 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1159 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1160 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1161 do {\ 1162 HWIO_INTLOCK(); \ 1163 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1164 HWIO_INTFREE();\ 1165 } while (0) 1166 1167 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1168 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1169 1170 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1171 1172 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x00000518) 1173 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x00000518) 1174 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1175 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1176 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1177 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1178 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1179 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1180 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1181 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1182 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1183 do {\ 1184 HWIO_INTLOCK(); \ 1185 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1186 HWIO_INTFREE();\ 1187 } while (0) 1188 1189 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1190 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1191 1192 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1193 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1194 1195 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1196 1197 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x0000051c) 1198 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x0000051c) 1199 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1200 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1201 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1202 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1203 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1204 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1205 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1206 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1207 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1208 do {\ 1209 HWIO_INTLOCK(); \ 1210 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1211 HWIO_INTFREE();\ 1212 } while (0) 1213 1214 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1215 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1216 1217 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1218 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1219 1220 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1221 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1222 1223 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1224 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1225 1226 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1227 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1228 1229 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1230 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1231 1232 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1233 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1234 1235 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1236 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1237 1238 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1239 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1240 1241 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1242 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1243 1244 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1245 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1246 1247 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1248 1249 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000528) 1250 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000528) 1251 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1252 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1253 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1254 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1255 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1256 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1257 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1258 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1259 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1260 do {\ 1261 HWIO_INTLOCK(); \ 1262 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1263 HWIO_INTFREE();\ 1264 } while (0) 1265 1266 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1267 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1268 1269 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1270 1271 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000052c) 1272 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000052c) 1273 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1274 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1275 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1276 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1277 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1278 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1279 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1280 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1281 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1282 do {\ 1283 HWIO_INTLOCK(); \ 1284 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1285 HWIO_INTFREE();\ 1286 } while (0) 1287 1288 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1289 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1290 1291 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1292 1293 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000053c) 1294 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000053c) 1295 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1296 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1297 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1298 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1299 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1300 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1301 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1302 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1303 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1304 do {\ 1305 HWIO_INTLOCK(); \ 1306 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1307 HWIO_INTFREE();\ 1308 } while (0) 1309 1310 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1311 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1312 1313 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1314 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1315 1316 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1317 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1318 1319 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1320 1321 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000540) 1322 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000540) 1323 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1324 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1325 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1326 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1327 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1328 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1329 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1330 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1331 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1332 do {\ 1333 HWIO_INTLOCK(); \ 1334 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1335 HWIO_INTFREE();\ 1336 } while (0) 1337 1338 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1339 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1340 1341 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1342 1343 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000544) 1344 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000544) 1345 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1346 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1347 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1348 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1349 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1350 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1351 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1352 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1353 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1354 do {\ 1355 HWIO_INTLOCK(); \ 1356 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1357 HWIO_INTFREE();\ 1358 } while (0) 1359 1360 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1361 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1362 1363 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1364 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1365 1366 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1367 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1368 1369 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1370 1371 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000548) 1372 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000548) 1373 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1374 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1375 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1376 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1377 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1378 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1379 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1380 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1381 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1382 do {\ 1383 HWIO_INTLOCK(); \ 1384 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1385 HWIO_INTFREE();\ 1386 } while (0) 1387 1388 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1389 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1390 1391 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1392 1393 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000054c) 1394 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000054c) 1395 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1396 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1397 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1398 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1399 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1400 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1401 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1402 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1403 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1404 do {\ 1405 HWIO_INTLOCK(); \ 1406 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1407 HWIO_INTFREE();\ 1408 } while (0) 1409 1410 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1411 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1412 1413 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1414 1415 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000550) 1416 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000550) 1417 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1418 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1419 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1420 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1421 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1422 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1423 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1424 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1425 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1426 do {\ 1427 HWIO_INTLOCK(); \ 1428 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1429 HWIO_INTFREE();\ 1430 } while (0) 1431 1432 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1433 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1434 1435 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1436 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1437 1438 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1439 1440 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000554) 1441 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000554) 1442 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1443 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1444 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1445 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1446 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1447 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1448 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1449 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1450 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1451 do {\ 1452 HWIO_INTLOCK(); \ 1453 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1454 HWIO_INTFREE();\ 1455 } while (0) 1456 1457 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1458 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1459 1460 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1461 1462 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000558) 1463 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000558) 1464 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1465 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1466 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1467 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1468 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1469 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1470 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1471 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1472 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1473 do {\ 1474 HWIO_INTLOCK(); \ 1475 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1476 HWIO_INTFREE();\ 1477 } while (0) 1478 1479 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1480 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1481 1482 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1483 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1484 1485 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1486 1487 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x0000055c) 1488 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x0000055c) 1489 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1490 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1491 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1492 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1493 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1494 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1495 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1496 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1497 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1498 do {\ 1499 HWIO_INTLOCK(); \ 1500 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1501 HWIO_INTFREE();\ 1502 } while (0) 1503 1504 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1505 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1506 1507 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1508 1509 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000560) 1510 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000560) 1511 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1512 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1513 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1514 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1515 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1516 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1517 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1518 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1519 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1520 do {\ 1521 HWIO_INTLOCK(); \ 1522 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1523 HWIO_INTFREE();\ 1524 } while (0) 1525 1526 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1527 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1528 1529 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 1530 1531 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x00000564) 1532 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x00000564) 1533 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 1534 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 1535 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 1536 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 1537 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 1538 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 1539 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 1540 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 1541 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 1542 do {\ 1543 HWIO_INTLOCK(); \ 1544 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 1545 HWIO_INTFREE();\ 1546 } while (0) 1547 1548 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1549 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1550 1551 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 1552 1553 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x00000568) 1554 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x00000568) 1555 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x00ffffff 1556 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 1557 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 1558 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 1559 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 1560 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 1561 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 1562 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 1563 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 1564 do {\ 1565 HWIO_INTLOCK(); \ 1566 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 1567 HWIO_INTFREE();\ 1568 } while (0) 1569 1570 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1571 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1572 1573 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1574 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1575 1576 //// Register TCL_R0_SW2TCL2_RING_ID //// 1577 1578 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x0000056c) 1579 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x0000056c) 1580 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 1581 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 1582 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 1583 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 1584 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 1585 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 1586 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 1587 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 1588 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 1589 do {\ 1590 HWIO_INTLOCK(); \ 1591 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 1592 HWIO_INTFREE();\ 1593 } while (0) 1594 1595 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1596 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 1597 1598 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 1599 1600 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000570) 1601 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000570) 1602 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 1603 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 1604 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 1605 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 1606 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 1607 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 1608 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 1609 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 1610 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 1611 do {\ 1612 HWIO_INTLOCK(); \ 1613 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 1614 HWIO_INTFREE();\ 1615 } while (0) 1616 1617 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1618 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1619 1620 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1621 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1622 1623 //// Register TCL_R0_SW2TCL2_RING_MISC //// 1624 1625 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x00000574) 1626 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x00000574) 1627 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 1628 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 1629 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 1630 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 1631 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 1632 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 1633 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 1634 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 1635 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 1636 do {\ 1637 HWIO_INTLOCK(); \ 1638 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 1639 HWIO_INTFREE();\ 1640 } while (0) 1641 1642 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1643 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1644 1645 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1646 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1647 1648 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1649 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1650 1651 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1652 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1653 1654 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1655 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1656 1657 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1658 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1659 1660 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1661 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1662 1663 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1664 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1665 1666 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1667 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 1668 1669 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1670 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1671 1672 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1673 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1674 1675 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 1676 1677 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000580) 1678 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000580) 1679 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1680 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 1681 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 1682 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 1683 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 1684 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 1685 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 1686 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 1687 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1688 do {\ 1689 HWIO_INTLOCK(); \ 1690 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 1691 HWIO_INTFREE();\ 1692 } while (0) 1693 1694 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1695 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1696 1697 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 1698 1699 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000584) 1700 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000584) 1701 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1702 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 1703 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 1704 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 1705 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 1706 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 1707 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 1708 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 1709 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1710 do {\ 1711 HWIO_INTLOCK(); \ 1712 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 1713 HWIO_INTFREE();\ 1714 } while (0) 1715 1716 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1717 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1718 1719 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 1720 1721 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000594) 1722 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000594) 1723 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1724 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1725 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1726 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1727 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1728 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1729 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1730 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1731 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1732 do {\ 1733 HWIO_INTLOCK(); \ 1734 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1735 HWIO_INTFREE();\ 1736 } while (0) 1737 1738 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1739 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1740 1741 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1742 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1743 1744 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1745 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1746 1747 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 1748 1749 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000598) 1750 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000598) 1751 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1752 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1753 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1754 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1755 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1756 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1757 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1758 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1759 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1760 do {\ 1761 HWIO_INTLOCK(); \ 1762 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1763 HWIO_INTFREE();\ 1764 } while (0) 1765 1766 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1767 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1768 1769 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 1770 1771 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000059c) 1772 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000059c) 1773 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1774 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 1775 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 1776 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 1777 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1778 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1779 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1780 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1781 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1782 do {\ 1783 HWIO_INTLOCK(); \ 1784 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1785 HWIO_INTFREE();\ 1786 } while (0) 1787 1788 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1789 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1790 1791 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1792 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1793 1794 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1795 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1796 1797 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 1798 1799 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000005a0) 1800 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000005a0) 1801 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1802 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1803 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1804 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1805 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1806 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1807 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1808 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1809 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1810 do {\ 1811 HWIO_INTLOCK(); \ 1812 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1813 HWIO_INTFREE();\ 1814 } while (0) 1815 1816 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1817 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1818 1819 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 1820 1821 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000005a4) 1822 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000005a4) 1823 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1824 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1825 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1826 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1827 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1828 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1829 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1830 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1831 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1832 do {\ 1833 HWIO_INTLOCK(); \ 1834 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1835 HWIO_INTFREE();\ 1836 } while (0) 1837 1838 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1839 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1840 1841 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 1842 1843 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000005a8) 1844 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000005a8) 1845 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1846 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1847 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1848 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1849 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1850 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1851 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1852 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1853 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1854 do {\ 1855 HWIO_INTLOCK(); \ 1856 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1857 HWIO_INTFREE();\ 1858 } while (0) 1859 1860 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1861 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1862 1863 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1864 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1865 1866 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 1867 1868 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000005ac) 1869 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000005ac) 1870 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1871 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 1872 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 1873 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 1874 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1875 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1876 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1877 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 1878 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1879 do {\ 1880 HWIO_INTLOCK(); \ 1881 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 1882 HWIO_INTFREE();\ 1883 } while (0) 1884 1885 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1886 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1887 1888 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 1889 1890 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000005b0) 1891 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000005b0) 1892 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1893 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 1894 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 1895 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 1896 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1897 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1898 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1899 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 1900 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1901 do {\ 1902 HWIO_INTLOCK(); \ 1903 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 1904 HWIO_INTFREE();\ 1905 } while (0) 1906 1907 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1908 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1909 1910 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1911 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1912 1913 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 1914 1915 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x000005b4) 1916 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x000005b4) 1917 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 1918 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 1919 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 1920 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 1921 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 1922 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 1923 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 1924 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 1925 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1926 do {\ 1927 HWIO_INTLOCK(); \ 1928 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 1929 HWIO_INTFREE();\ 1930 } while (0) 1931 1932 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1933 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 1934 1935 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 1936 1937 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005b8) 1938 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005b8) 1939 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1940 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 1941 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 1942 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 1943 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1944 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1945 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1946 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1947 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1948 do {\ 1949 HWIO_INTLOCK(); \ 1950 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1951 HWIO_INTFREE();\ 1952 } while (0) 1953 1954 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1955 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1956 1957 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 1958 1959 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x000005bc) 1960 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x000005bc) 1961 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 1962 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 1963 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 1964 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 1965 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 1966 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 1967 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 1968 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 1969 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 1970 do {\ 1971 HWIO_INTLOCK(); \ 1972 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 1973 HWIO_INTFREE();\ 1974 } while (0) 1975 1976 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1977 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1978 1979 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 1980 1981 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x000005c0) 1982 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x000005c0) 1983 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x00ffffff 1984 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 1985 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 1986 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 1987 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 1988 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 1989 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 1990 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 1991 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 1992 do {\ 1993 HWIO_INTLOCK(); \ 1994 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 1995 HWIO_INTFREE();\ 1996 } while (0) 1997 1998 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1999 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2000 2001 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2002 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2003 2004 //// Register TCL_R0_SW2TCL3_RING_ID //// 2005 2006 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x000005c4) 2007 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x000005c4) 2008 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 2009 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 2010 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 2011 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 2012 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 2013 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 2014 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 2015 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 2016 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 2017 do {\ 2018 HWIO_INTLOCK(); \ 2019 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 2020 HWIO_INTFREE();\ 2021 } while (0) 2022 2023 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2024 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 2025 2026 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 2027 2028 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x000005c8) 2029 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x000005c8) 2030 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 2031 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 2032 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 2033 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 2034 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 2035 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 2036 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 2037 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 2038 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 2039 do {\ 2040 HWIO_INTLOCK(); \ 2041 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 2042 HWIO_INTFREE();\ 2043 } while (0) 2044 2045 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2046 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2047 2048 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2049 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2050 2051 //// Register TCL_R0_SW2TCL3_RING_MISC //// 2052 2053 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x000005cc) 2054 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x000005cc) 2055 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 2056 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 2057 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 2058 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 2059 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 2060 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 2061 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 2062 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 2063 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 2064 do {\ 2065 HWIO_INTLOCK(); \ 2066 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 2067 HWIO_INTFREE();\ 2068 } while (0) 2069 2070 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2071 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 2072 2073 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2074 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2075 2076 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2077 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2078 2079 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2080 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2081 2082 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2083 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 2084 2085 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2086 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2087 2088 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2089 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2090 2091 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2092 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2093 2094 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2095 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 2096 2097 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2098 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2099 2100 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2101 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2102 2103 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 2104 2105 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x000005d8) 2106 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x000005d8) 2107 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2108 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2109 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2110 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2111 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2112 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2113 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2114 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2115 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2116 do {\ 2117 HWIO_INTLOCK(); \ 2118 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2119 HWIO_INTFREE();\ 2120 } while (0) 2121 2122 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2123 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2124 2125 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2126 2127 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x000005dc) 2128 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x000005dc) 2129 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2130 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2131 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2132 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2133 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2134 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2135 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2136 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2137 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2138 do {\ 2139 HWIO_INTLOCK(); \ 2140 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2141 HWIO_INTFREE();\ 2142 } while (0) 2143 2144 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2145 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2146 2147 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2148 2149 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000005ec) 2150 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000005ec) 2151 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2152 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2153 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2154 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2155 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2156 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2157 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2158 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2159 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2160 do {\ 2161 HWIO_INTLOCK(); \ 2162 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2163 HWIO_INTFREE();\ 2164 } while (0) 2165 2166 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2167 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2168 2169 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2170 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2171 2172 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2173 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2174 2175 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2176 2177 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000005f0) 2178 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000005f0) 2179 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2180 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2181 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2182 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2183 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2184 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2185 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2186 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2187 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2188 do {\ 2189 HWIO_INTLOCK(); \ 2190 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2191 HWIO_INTFREE();\ 2192 } while (0) 2193 2194 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2195 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2196 2197 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2198 2199 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000005f4) 2200 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000005f4) 2201 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2202 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2203 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2204 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2205 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2206 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2207 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2208 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2209 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2210 do {\ 2211 HWIO_INTLOCK(); \ 2212 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2213 HWIO_INTFREE();\ 2214 } while (0) 2215 2216 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2217 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2218 2219 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2220 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2221 2222 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2223 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2224 2225 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2226 2227 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000005f8) 2228 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000005f8) 2229 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2230 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2231 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2232 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2233 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2234 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2235 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2236 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2237 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2238 do {\ 2239 HWIO_INTLOCK(); \ 2240 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2241 HWIO_INTFREE();\ 2242 } while (0) 2243 2244 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2245 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2246 2247 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2248 2249 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000005fc) 2250 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000005fc) 2251 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2252 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2253 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2254 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2255 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2256 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2257 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2258 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2259 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2260 do {\ 2261 HWIO_INTLOCK(); \ 2262 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2263 HWIO_INTFREE();\ 2264 } while (0) 2265 2266 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2267 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2268 2269 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2270 2271 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000600) 2272 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000600) 2273 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2274 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2275 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2276 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2277 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2278 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2279 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2280 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2281 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2282 do {\ 2283 HWIO_INTLOCK(); \ 2284 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2285 HWIO_INTFREE();\ 2286 } while (0) 2287 2288 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2289 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2290 2291 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2292 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2293 2294 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2295 2296 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000604) 2297 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000604) 2298 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2299 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2300 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2301 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2302 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2303 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2304 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2305 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2306 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2307 do {\ 2308 HWIO_INTLOCK(); \ 2309 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2310 HWIO_INTFREE();\ 2311 } while (0) 2312 2313 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2314 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2315 2316 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2317 2318 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000608) 2319 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000608) 2320 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2321 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2322 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2323 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2324 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2325 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2326 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2327 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2328 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2329 do {\ 2330 HWIO_INTLOCK(); \ 2331 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2332 HWIO_INTFREE();\ 2333 } while (0) 2334 2335 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2336 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2337 2338 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2339 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2340 2341 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2342 2343 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x0000060c) 2344 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x0000060c) 2345 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2346 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2347 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2348 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2349 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2350 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2351 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2352 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2353 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2354 do {\ 2355 HWIO_INTLOCK(); \ 2356 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2357 HWIO_INTFREE();\ 2358 } while (0) 2359 2360 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2361 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2362 2363 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2364 2365 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000610) 2366 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000610) 2367 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2368 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2369 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2370 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2371 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2372 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2373 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2374 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2375 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2376 do {\ 2377 HWIO_INTLOCK(); \ 2378 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2379 HWIO_INTFREE();\ 2380 } while (0) 2381 2382 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2383 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2384 2385 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// 2386 2387 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000614) 2388 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000614) 2389 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff 2390 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 2391 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ 2392 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) 2393 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ 2394 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 2395 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ 2396 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) 2397 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2398 do {\ 2399 HWIO_INTLOCK(); \ 2400 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ 2401 HWIO_INTFREE();\ 2402 } while (0) 2403 2404 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2405 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2406 2407 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// 2408 2409 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x00000618) 2410 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x00000618) 2411 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x00ffffff 2412 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 2413 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ 2414 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) 2415 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ 2416 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 2417 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ 2418 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) 2419 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2420 do {\ 2421 HWIO_INTLOCK(); \ 2422 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ 2423 HWIO_INTFREE();\ 2424 } while (0) 2425 2426 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2427 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2428 2429 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2430 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2431 2432 //// Register TCL_R0_SW2TCL_CMD_RING_ID //// 2433 2434 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x0000061c) 2435 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x0000061c) 2436 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff 2437 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 2438 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ 2439 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) 2440 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ 2441 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 2442 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ 2443 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) 2444 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ 2445 do {\ 2446 HWIO_INTLOCK(); \ 2447 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ 2448 HWIO_INTFREE();\ 2449 } while (0) 2450 2451 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2452 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2453 2454 //// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// 2455 2456 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x00000620) 2457 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x00000620) 2458 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff 2459 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 2460 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ 2461 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) 2462 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ 2463 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 2464 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ 2465 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) 2466 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ 2467 do {\ 2468 HWIO_INTLOCK(); \ 2469 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ 2470 HWIO_INTFREE();\ 2471 } while (0) 2472 2473 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2474 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2475 2476 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2477 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2478 2479 //// Register TCL_R0_SW2TCL_CMD_RING_MISC //// 2480 2481 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x00000624) 2482 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x00000624) 2483 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x003fffff 2484 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 2485 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ 2486 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) 2487 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ 2488 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 2489 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ 2490 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) 2491 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ 2492 do {\ 2493 HWIO_INTLOCK(); \ 2494 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ 2495 HWIO_INTFREE();\ 2496 } while (0) 2497 2498 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2499 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 2500 2501 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2502 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2503 2504 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2505 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2506 2507 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2508 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2509 2510 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2511 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 2512 2513 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2514 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2515 2516 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2517 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2518 2519 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2520 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2521 2522 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2523 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2524 2525 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2526 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2527 2528 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2529 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2530 2531 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// 2532 2533 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000630) 2534 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000630) 2535 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2536 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 2537 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ 2538 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) 2539 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2540 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2541 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2542 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2543 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2544 do {\ 2545 HWIO_INTLOCK(); \ 2546 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2547 HWIO_INTFREE();\ 2548 } while (0) 2549 2550 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2551 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2552 2553 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// 2554 2555 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000634) 2556 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000634) 2557 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2558 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 2559 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ 2560 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) 2561 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2562 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2563 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2564 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2565 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2566 do {\ 2567 HWIO_INTLOCK(); \ 2568 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2569 HWIO_INTFREE();\ 2570 } while (0) 2571 2572 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2573 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2574 2575 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2576 2577 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000644) 2578 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000644) 2579 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2580 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2581 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2582 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2583 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2584 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2585 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2586 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2587 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2588 do {\ 2589 HWIO_INTLOCK(); \ 2590 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2591 HWIO_INTFREE();\ 2592 } while (0) 2593 2594 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2595 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2596 2597 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2598 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2599 2600 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2601 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2602 2603 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2604 2605 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000648) 2606 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000648) 2607 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2608 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2609 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2610 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2611 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2612 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2613 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2614 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2615 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2616 do {\ 2617 HWIO_INTLOCK(); \ 2618 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2619 HWIO_INTFREE();\ 2620 } while (0) 2621 2622 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2623 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2624 2625 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// 2626 2627 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000064c) 2628 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000064c) 2629 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2630 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2631 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2632 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2633 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2634 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2635 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2636 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2637 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2638 do {\ 2639 HWIO_INTLOCK(); \ 2640 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2641 HWIO_INTFREE();\ 2642 } while (0) 2643 2644 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2645 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2646 2647 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2648 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2649 2650 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2651 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2652 2653 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2654 2655 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000650) 2656 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000650) 2657 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2658 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2659 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2660 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2661 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2662 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2663 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2664 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2665 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2666 do {\ 2667 HWIO_INTLOCK(); \ 2668 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2669 HWIO_INTFREE();\ 2670 } while (0) 2671 2672 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2673 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2674 2675 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2676 2677 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000654) 2678 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000654) 2679 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2680 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2681 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2682 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2683 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2684 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2685 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2686 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2687 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2688 do {\ 2689 HWIO_INTLOCK(); \ 2690 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2691 HWIO_INTFREE();\ 2692 } while (0) 2693 2694 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2695 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2696 2697 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2698 2699 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000658) 2700 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000658) 2701 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 2702 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2703 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2704 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2705 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2706 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2707 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2708 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2709 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2710 do {\ 2711 HWIO_INTLOCK(); \ 2712 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2713 HWIO_INTFREE();\ 2714 } while (0) 2715 2716 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 2717 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 2718 2719 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 2720 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2721 2722 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// 2723 2724 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000065c) 2725 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000065c) 2726 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2727 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 2728 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2729 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) 2730 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2731 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2732 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2733 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2734 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2735 do {\ 2736 HWIO_INTLOCK(); \ 2737 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2738 HWIO_INTFREE();\ 2739 } while (0) 2740 2741 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2742 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2743 2744 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// 2745 2746 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000660) 2747 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000660) 2748 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2749 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 2750 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2751 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) 2752 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2753 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2754 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2755 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2756 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2757 do {\ 2758 HWIO_INTLOCK(); \ 2759 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2760 HWIO_INTFREE();\ 2761 } while (0) 2762 2763 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2764 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2765 2766 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2767 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2768 2769 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// 2770 2771 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000664) 2772 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000664) 2773 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2774 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 2775 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ 2776 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) 2777 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ 2778 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 2779 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ 2780 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) 2781 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2782 do {\ 2783 HWIO_INTLOCK(); \ 2784 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ 2785 HWIO_INTFREE();\ 2786 } while (0) 2787 2788 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2789 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2790 2791 //// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// 2792 2793 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000668) 2794 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000668) 2795 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2796 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2797 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2798 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2799 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2800 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2801 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2802 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2803 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2804 do {\ 2805 HWIO_INTLOCK(); \ 2806 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2807 HWIO_INTFREE();\ 2808 } while (0) 2809 2810 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2811 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2812 2813 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 2814 2815 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x0000066c) 2816 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x0000066c) 2817 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 2818 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 2819 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 2820 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 2821 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 2822 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 2823 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 2824 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 2825 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 2826 do {\ 2827 HWIO_INTLOCK(); \ 2828 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 2829 HWIO_INTFREE();\ 2830 } while (0) 2831 2832 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2833 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2834 2835 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 2836 2837 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000670) 2838 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000670) 2839 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 2840 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 2841 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 2842 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 2843 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 2844 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 2845 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 2846 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 2847 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 2848 do {\ 2849 HWIO_INTLOCK(); \ 2850 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 2851 HWIO_INTFREE();\ 2852 } while (0) 2853 2854 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2855 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2856 2857 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2858 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2859 2860 //// Register TCL_R0_FW2TCL1_RING_ID //// 2861 2862 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x00000674) 2863 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x00000674) 2864 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 2865 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 2866 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 2867 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 2868 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 2869 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 2870 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 2871 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 2872 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 2873 do {\ 2874 HWIO_INTLOCK(); \ 2875 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 2876 HWIO_INTFREE();\ 2877 } while (0) 2878 2879 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2880 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 2881 2882 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 2883 2884 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000678) 2885 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000678) 2886 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 2887 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 2888 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 2889 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 2890 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 2891 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 2892 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 2893 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 2894 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 2895 do {\ 2896 HWIO_INTLOCK(); \ 2897 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 2898 HWIO_INTFREE();\ 2899 } while (0) 2900 2901 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2902 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2903 2904 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2905 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2906 2907 //// Register TCL_R0_FW2TCL1_RING_MISC //// 2908 2909 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x0000067c) 2910 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x0000067c) 2911 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 2912 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 2913 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 2914 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 2915 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 2916 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 2917 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 2918 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 2919 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 2920 do {\ 2921 HWIO_INTLOCK(); \ 2922 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 2923 HWIO_INTFREE();\ 2924 } while (0) 2925 2926 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2927 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2928 2929 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2930 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2931 2932 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2933 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2934 2935 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2936 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2937 2938 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2939 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2940 2941 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2942 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2943 2944 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2945 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2946 2947 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2948 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2949 2950 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2951 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 2952 2953 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2954 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2955 2956 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2957 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2958 2959 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 2960 2961 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000688) 2962 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000688) 2963 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2964 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 2965 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 2966 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 2967 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 2968 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 2969 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 2970 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 2971 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2972 do {\ 2973 HWIO_INTLOCK(); \ 2974 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 2975 HWIO_INTFREE();\ 2976 } while (0) 2977 2978 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2979 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2980 2981 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 2982 2983 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000068c) 2984 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000068c) 2985 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 2986 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 2987 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 2988 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 2989 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 2990 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 2991 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 2992 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 2993 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2994 do {\ 2995 HWIO_INTLOCK(); \ 2996 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 2997 HWIO_INTFREE();\ 2998 } while (0) 2999 3000 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3001 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3002 3003 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 3004 3005 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000069c) 3006 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000069c) 3007 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3008 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3009 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3010 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3011 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3012 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3013 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3014 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3015 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3016 do {\ 3017 HWIO_INTLOCK(); \ 3018 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3019 HWIO_INTFREE();\ 3020 } while (0) 3021 3022 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3023 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3024 3025 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3026 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3027 3028 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3029 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3030 3031 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 3032 3033 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006a0) 3034 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006a0) 3035 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3036 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3037 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3038 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3039 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3040 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3041 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3042 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3043 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3044 do {\ 3045 HWIO_INTLOCK(); \ 3046 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3047 HWIO_INTFREE();\ 3048 } while (0) 3049 3050 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3051 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3052 3053 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 3054 3055 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006a4) 3056 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006a4) 3057 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3058 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 3059 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 3060 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 3061 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3062 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3063 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3064 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3065 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3066 do {\ 3067 HWIO_INTLOCK(); \ 3068 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3069 HWIO_INTFREE();\ 3070 } while (0) 3071 3072 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3073 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3074 3075 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3076 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3077 3078 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3079 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3080 3081 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 3082 3083 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006a8) 3084 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006a8) 3085 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3086 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3087 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3088 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3089 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3090 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3091 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3092 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3093 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3094 do {\ 3095 HWIO_INTLOCK(); \ 3096 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3097 HWIO_INTFREE();\ 3098 } while (0) 3099 3100 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3101 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3102 3103 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 3104 3105 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006ac) 3106 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006ac) 3107 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3108 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3109 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3110 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3111 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3112 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3113 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3114 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3115 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3116 do {\ 3117 HWIO_INTLOCK(); \ 3118 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3119 HWIO_INTFREE();\ 3120 } while (0) 3121 3122 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3123 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3124 3125 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3126 3127 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006b0) 3128 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006b0) 3129 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3130 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3131 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3132 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3133 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3134 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3135 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3136 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3137 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3138 do {\ 3139 HWIO_INTLOCK(); \ 3140 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3141 HWIO_INTFREE();\ 3142 } while (0) 3143 3144 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3145 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3146 3147 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3148 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3149 3150 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3151 3152 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006b4) 3153 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006b4) 3154 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3155 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3156 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3157 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3158 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3159 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3160 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3161 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3162 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3163 do {\ 3164 HWIO_INTLOCK(); \ 3165 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3166 HWIO_INTFREE();\ 3167 } while (0) 3168 3169 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3170 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3171 3172 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3173 3174 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006b8) 3175 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006b8) 3176 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3177 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3178 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3179 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3180 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3181 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3182 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3183 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3184 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3185 do {\ 3186 HWIO_INTLOCK(); \ 3187 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3188 HWIO_INTFREE();\ 3189 } while (0) 3190 3191 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3192 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3193 3194 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3195 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3196 3197 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3198 3199 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006bc) 3200 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006bc) 3201 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3202 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3203 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3204 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3205 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3206 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3207 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3208 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3209 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3210 do {\ 3211 HWIO_INTLOCK(); \ 3212 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3213 HWIO_INTFREE();\ 3214 } while (0) 3215 3216 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3217 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3218 3219 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3220 3221 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006c0) 3222 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006c0) 3223 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3224 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3225 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3226 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3227 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3228 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3229 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3230 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3231 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3232 do {\ 3233 HWIO_INTLOCK(); \ 3234 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3235 HWIO_INTFREE();\ 3236 } while (0) 3237 3238 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3239 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3240 3241 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3242 3243 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x000006c4) 3244 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x000006c4) 3245 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3246 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3247 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3248 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3249 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3250 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3251 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3252 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3253 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3254 do {\ 3255 HWIO_INTLOCK(); \ 3256 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3257 HWIO_INTFREE();\ 3258 } while (0) 3259 3260 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3261 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3262 3263 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3264 3265 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x000006c8) 3266 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x000006c8) 3267 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3268 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3269 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3270 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3271 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3272 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3273 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3274 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3275 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3276 do {\ 3277 HWIO_INTLOCK(); \ 3278 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3279 HWIO_INTFREE();\ 3280 } while (0) 3281 3282 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3283 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3284 3285 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3286 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3287 3288 //// Register TCL_R0_TCL2TQM_RING_ID //// 3289 3290 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x000006cc) 3291 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x000006cc) 3292 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3293 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3294 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3295 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3296 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3297 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3298 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3299 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3300 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3301 do {\ 3302 HWIO_INTLOCK(); \ 3303 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3304 HWIO_INTFREE();\ 3305 } while (0) 3306 3307 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3308 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3309 3310 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3311 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3312 3313 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3314 3315 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x000006d0) 3316 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x000006d0) 3317 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3318 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3319 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3320 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3321 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3322 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3323 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3324 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3325 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3326 do {\ 3327 HWIO_INTLOCK(); \ 3328 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3329 HWIO_INTFREE();\ 3330 } while (0) 3331 3332 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3333 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3334 3335 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3336 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3337 3338 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3339 3340 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x000006d4) 3341 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x000006d4) 3342 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3343 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3344 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3345 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3346 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3347 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3348 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3349 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3350 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3351 do {\ 3352 HWIO_INTLOCK(); \ 3353 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3354 HWIO_INTFREE();\ 3355 } while (0) 3356 3357 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3358 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3359 3360 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3361 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3362 3363 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3364 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3365 3366 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3367 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3368 3369 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3370 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3371 3372 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3373 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3374 3375 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3376 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3377 3378 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3379 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3380 3381 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3382 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3383 3384 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3385 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3386 3387 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3388 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3389 3390 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3391 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3392 3393 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3394 3395 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006d8) 3396 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006d8) 3397 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3398 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3399 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3400 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3401 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3402 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3403 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3404 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3405 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3406 do {\ 3407 HWIO_INTLOCK(); \ 3408 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3409 HWIO_INTFREE();\ 3410 } while (0) 3411 3412 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3413 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3414 3415 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3416 3417 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006dc) 3418 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006dc) 3419 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3420 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3421 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3422 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3423 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3424 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3425 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3426 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3427 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3428 do {\ 3429 HWIO_INTLOCK(); \ 3430 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3431 HWIO_INTFREE();\ 3432 } while (0) 3433 3434 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3435 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3436 3437 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3438 3439 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006e8) 3440 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006e8) 3441 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3442 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3443 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3444 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3445 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3446 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3447 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3448 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3449 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3450 do {\ 3451 HWIO_INTLOCK(); \ 3452 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3453 HWIO_INTFREE();\ 3454 } while (0) 3455 3456 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3457 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3458 3459 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3460 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3461 3462 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3463 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3464 3465 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3466 3467 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006ec) 3468 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006ec) 3469 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3470 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3471 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3472 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3473 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3474 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3475 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3476 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3477 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3478 do {\ 3479 HWIO_INTLOCK(); \ 3480 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3481 HWIO_INTFREE();\ 3482 } while (0) 3483 3484 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3485 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3486 3487 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3488 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3489 3490 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3491 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3492 3493 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3494 3495 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006f0) 3496 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006f0) 3497 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3498 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3499 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3500 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3501 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3502 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3503 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3504 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3505 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3506 do {\ 3507 HWIO_INTLOCK(); \ 3508 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3509 HWIO_INTFREE();\ 3510 } while (0) 3511 3512 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3513 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3514 3515 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3516 3517 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000718) 3518 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000718) 3519 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3520 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3521 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3522 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3523 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3524 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3525 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3526 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3527 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3528 do {\ 3529 HWIO_INTLOCK(); \ 3530 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3531 HWIO_INTFREE();\ 3532 } while (0) 3533 3534 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3535 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3536 3537 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3538 3539 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x0000071c) 3540 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x0000071c) 3541 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3542 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3543 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3544 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3545 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3546 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3547 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3548 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3549 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3550 do {\ 3551 HWIO_INTLOCK(); \ 3552 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3553 HWIO_INTFREE();\ 3554 } while (0) 3555 3556 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3557 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3558 3559 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3560 3561 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x00000720) 3562 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x00000720) 3563 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3564 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3565 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3566 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3567 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3568 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3569 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3570 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3571 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3572 do {\ 3573 HWIO_INTLOCK(); \ 3574 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3575 HWIO_INTFREE();\ 3576 } while (0) 3577 3578 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3579 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3580 3581 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3582 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3583 3584 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3585 3586 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x00000724) 3587 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x00000724) 3588 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3589 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3590 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3591 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3592 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3593 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3594 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 3595 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 3596 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 3597 do {\ 3598 HWIO_INTLOCK(); \ 3599 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 3600 HWIO_INTFREE();\ 3601 } while (0) 3602 3603 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 3604 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 3605 3606 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3607 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 3608 3609 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 3610 3611 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x00000728) 3612 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x00000728) 3613 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 3614 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 3615 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 3616 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 3617 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 3618 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 3619 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 3620 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 3621 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 3622 do {\ 3623 HWIO_INTLOCK(); \ 3624 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 3625 HWIO_INTFREE();\ 3626 } while (0) 3627 3628 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3629 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3630 3631 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3632 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3633 3634 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 3635 3636 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x0000072c) 3637 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x0000072c) 3638 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 3639 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 3640 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 3641 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 3642 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 3643 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 3644 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 3645 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 3646 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 3647 do {\ 3648 HWIO_INTLOCK(); \ 3649 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 3650 HWIO_INTFREE();\ 3651 } while (0) 3652 3653 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3654 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 3655 3656 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3657 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3658 3659 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3660 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3661 3662 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3663 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3664 3665 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3666 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3667 3668 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3669 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3670 3671 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3672 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3673 3674 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3675 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3676 3677 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3678 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3679 3680 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3681 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 3682 3683 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3684 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3685 3686 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3687 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3688 3689 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 3690 3691 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000730) 3692 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000730) 3693 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3694 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 3695 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 3696 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 3697 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 3698 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 3699 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 3700 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 3701 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3702 do {\ 3703 HWIO_INTLOCK(); \ 3704 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 3705 HWIO_INTFREE();\ 3706 } while (0) 3707 3708 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3709 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3710 3711 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 3712 3713 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000734) 3714 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000734) 3715 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3716 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 3717 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 3718 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 3719 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 3720 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 3721 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 3722 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 3723 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3724 do {\ 3725 HWIO_INTLOCK(); \ 3726 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 3727 HWIO_INTFREE();\ 3728 } while (0) 3729 3730 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3731 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3732 3733 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 3734 3735 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000740) 3736 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000740) 3737 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3738 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 3739 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 3740 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 3741 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3742 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3743 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3744 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3745 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3746 do {\ 3747 HWIO_INTLOCK(); \ 3748 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3749 HWIO_INTFREE();\ 3750 } while (0) 3751 3752 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3753 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3754 3755 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3756 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3757 3758 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3759 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3760 3761 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 3762 3763 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000744) 3764 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000744) 3765 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3766 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 3767 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 3768 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 3769 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3770 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3771 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3772 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3773 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3774 do {\ 3775 HWIO_INTLOCK(); \ 3776 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3777 HWIO_INTFREE();\ 3778 } while (0) 3779 3780 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3781 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3782 3783 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3784 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3785 3786 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3787 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3788 3789 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 3790 3791 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000748) 3792 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000748) 3793 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3794 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3795 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3796 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 3797 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3798 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3799 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3800 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3801 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3802 do {\ 3803 HWIO_INTLOCK(); \ 3804 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3805 HWIO_INTFREE();\ 3806 } while (0) 3807 3808 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3809 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3810 3811 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 3812 3813 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000764) 3814 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000764) 3815 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3816 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 3817 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 3818 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 3819 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3820 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3821 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3822 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 3823 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3824 do {\ 3825 HWIO_INTLOCK(); \ 3826 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 3827 HWIO_INTFREE();\ 3828 } while (0) 3829 3830 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3831 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3832 3833 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 3834 3835 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000768) 3836 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000768) 3837 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3838 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 3839 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 3840 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 3841 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3842 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3843 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3844 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 3845 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3846 do {\ 3847 HWIO_INTLOCK(); \ 3848 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 3849 HWIO_INTFREE();\ 3850 } while (0) 3851 3852 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3853 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3854 3855 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3856 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3857 3858 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 3859 3860 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x0000076c) 3861 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x0000076c) 3862 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 3863 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 3864 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 3865 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 3866 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 3867 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 3868 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 3869 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 3870 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3871 do {\ 3872 HWIO_INTLOCK(); \ 3873 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 3874 HWIO_INTFREE();\ 3875 } while (0) 3876 3877 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3878 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 3879 3880 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 3881 3882 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000770) 3883 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000770) 3884 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3885 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 3886 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 3887 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 3888 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3889 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3890 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3891 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3892 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3893 do {\ 3894 HWIO_INTLOCK(); \ 3895 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3896 HWIO_INTFREE();\ 3897 } while (0) 3898 3899 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3900 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3901 3902 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 3903 3904 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x00000774) 3905 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x00000774) 3906 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 3907 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 3908 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 3909 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 3910 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 3911 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 3912 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 3913 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 3914 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 3915 do {\ 3916 HWIO_INTLOCK(); \ 3917 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 3918 HWIO_INTFREE();\ 3919 } while (0) 3920 3921 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3922 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3923 3924 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 3925 3926 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000778) 3927 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000778) 3928 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 3929 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 3930 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 3931 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 3932 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 3933 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 3934 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 3935 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 3936 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 3937 do {\ 3938 HWIO_INTLOCK(); \ 3939 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 3940 HWIO_INTFREE();\ 3941 } while (0) 3942 3943 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3944 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3945 3946 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3947 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3948 3949 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 3950 3951 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x0000077c) 3952 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x0000077c) 3953 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 3954 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 3955 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 3956 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 3957 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 3958 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 3959 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 3960 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 3961 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 3962 do {\ 3963 HWIO_INTLOCK(); \ 3964 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 3965 HWIO_INTFREE();\ 3966 } while (0) 3967 3968 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 3969 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 3970 3971 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3972 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 3973 3974 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 3975 3976 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000780) 3977 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000780) 3978 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 3979 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 3980 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 3981 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 3982 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 3983 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 3984 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 3985 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 3986 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 3987 do {\ 3988 HWIO_INTLOCK(); \ 3989 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 3990 HWIO_INTFREE();\ 3991 } while (0) 3992 3993 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3994 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3995 3996 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3997 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3998 3999 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 4000 4001 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x00000784) 4002 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x00000784) 4003 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 4004 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 4005 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 4006 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 4007 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 4008 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 4009 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 4010 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 4011 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 4012 do {\ 4013 HWIO_INTLOCK(); \ 4014 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 4015 HWIO_INTFREE();\ 4016 } while (0) 4017 4018 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4019 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 4020 4021 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4022 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 4023 4024 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4025 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4026 4027 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4028 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4029 4030 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4031 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4032 4033 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4034 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 4035 4036 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4037 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4038 4039 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4040 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4041 4042 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4043 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4044 4045 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4046 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 4047 4048 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4049 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4050 4051 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4052 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4053 4054 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 4055 4056 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000788) 4057 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000788) 4058 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4059 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 4060 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 4061 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 4062 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 4063 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 4064 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 4065 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 4066 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4067 do {\ 4068 HWIO_INTLOCK(); \ 4069 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 4070 HWIO_INTFREE();\ 4071 } while (0) 4072 4073 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4074 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4075 4076 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 4077 4078 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000078c) 4079 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000078c) 4080 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4081 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 4082 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 4083 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 4084 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 4085 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 4086 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 4087 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 4088 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4089 do {\ 4090 HWIO_INTLOCK(); \ 4091 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 4092 HWIO_INTFREE();\ 4093 } while (0) 4094 4095 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4096 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4097 4098 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 4099 4100 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000798) 4101 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000798) 4102 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4103 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 4104 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 4105 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 4106 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4107 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4108 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4109 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4110 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4111 do {\ 4112 HWIO_INTLOCK(); \ 4113 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4114 HWIO_INTFREE();\ 4115 } while (0) 4116 4117 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4118 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4119 4120 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4121 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4122 4123 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4124 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4125 4126 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4127 4128 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000079c) 4129 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000079c) 4130 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4131 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4132 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4133 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4134 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4135 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4136 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4137 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4138 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4139 do {\ 4140 HWIO_INTLOCK(); \ 4141 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4142 HWIO_INTFREE();\ 4143 } while (0) 4144 4145 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4146 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4147 4148 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4149 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4150 4151 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4152 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4153 4154 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4155 4156 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007a0) 4157 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007a0) 4158 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4159 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4160 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4161 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4162 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4163 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4164 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4165 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4166 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4167 do {\ 4168 HWIO_INTLOCK(); \ 4169 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4170 HWIO_INTFREE();\ 4171 } while (0) 4172 4173 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4174 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4175 4176 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4177 4178 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007bc) 4179 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007bc) 4180 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4181 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4182 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4183 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4184 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4185 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4186 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4187 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4188 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4189 do {\ 4190 HWIO_INTLOCK(); \ 4191 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4192 HWIO_INTFREE();\ 4193 } while (0) 4194 4195 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4196 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4197 4198 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4199 4200 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007c0) 4201 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007c0) 4202 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4203 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4204 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4205 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4206 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4207 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4208 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4209 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4210 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4211 do {\ 4212 HWIO_INTLOCK(); \ 4213 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4214 HWIO_INTFREE();\ 4215 } while (0) 4216 4217 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4218 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4219 4220 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4221 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4222 4223 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4224 4225 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x000007c4) 4226 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x000007c4) 4227 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4228 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4229 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4230 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4231 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4232 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4233 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4234 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4235 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4236 do {\ 4237 HWIO_INTLOCK(); \ 4238 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4239 HWIO_INTFREE();\ 4240 } while (0) 4241 4242 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4243 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4244 4245 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4246 4247 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007c8) 4248 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007c8) 4249 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4250 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4251 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4252 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4253 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4254 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4255 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4256 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4257 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4258 do {\ 4259 HWIO_INTLOCK(); \ 4260 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4261 HWIO_INTFREE();\ 4262 } while (0) 4263 4264 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4265 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4266 4267 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4268 4269 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x000007cc) 4270 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x000007cc) 4271 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4272 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4273 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4274 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4275 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4276 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4277 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4278 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4279 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4280 do {\ 4281 HWIO_INTLOCK(); \ 4282 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4283 HWIO_INTFREE();\ 4284 } while (0) 4285 4286 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4287 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4288 4289 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4290 4291 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x000007d0) 4292 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x000007d0) 4293 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4294 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4295 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4296 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4297 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4298 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4299 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4300 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4301 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4302 do {\ 4303 HWIO_INTLOCK(); \ 4304 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4305 HWIO_INTFREE();\ 4306 } while (0) 4307 4308 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4309 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4310 4311 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4312 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4313 4314 //// Register TCL_R0_TCL2FW_RING_ID //// 4315 4316 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x000007d4) 4317 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x000007d4) 4318 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4319 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4320 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4321 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4322 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4323 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4324 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4325 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4326 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4327 do {\ 4328 HWIO_INTLOCK(); \ 4329 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4330 HWIO_INTFREE();\ 4331 } while (0) 4332 4333 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4334 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4335 4336 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4337 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4338 4339 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4340 4341 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x000007d8) 4342 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x000007d8) 4343 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4344 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4345 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4346 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4347 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4348 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4349 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4350 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4351 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4352 do {\ 4353 HWIO_INTLOCK(); \ 4354 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4355 HWIO_INTFREE();\ 4356 } while (0) 4357 4358 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4359 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4360 4361 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4362 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4363 4364 //// Register TCL_R0_TCL2FW_RING_MISC //// 4365 4366 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x000007dc) 4367 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x000007dc) 4368 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4369 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4370 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4371 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4372 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4373 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4374 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4375 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4376 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4377 do {\ 4378 HWIO_INTLOCK(); \ 4379 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4380 HWIO_INTFREE();\ 4381 } while (0) 4382 4383 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4384 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4385 4386 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4387 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4388 4389 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4390 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4391 4392 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4393 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4394 4395 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4396 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4397 4398 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4399 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4400 4401 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4402 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4403 4404 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4405 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4406 4407 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4408 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4409 4410 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4411 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4412 4413 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4414 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4415 4416 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4417 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4418 4419 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4420 4421 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007e0) 4422 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007e0) 4423 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4424 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4425 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4426 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4427 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4428 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4429 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4430 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4431 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4432 do {\ 4433 HWIO_INTLOCK(); \ 4434 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4435 HWIO_INTFREE();\ 4436 } while (0) 4437 4438 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4439 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4440 4441 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4442 4443 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007e4) 4444 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007e4) 4445 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4446 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4447 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4448 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4449 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4450 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4451 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4452 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4453 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4454 do {\ 4455 HWIO_INTLOCK(); \ 4456 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4457 HWIO_INTFREE();\ 4458 } while (0) 4459 4460 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4461 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4462 4463 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4464 4465 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007f0) 4466 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007f0) 4467 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4468 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4469 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4470 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4471 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4472 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4473 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4474 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4475 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4476 do {\ 4477 HWIO_INTLOCK(); \ 4478 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4479 HWIO_INTFREE();\ 4480 } while (0) 4481 4482 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4483 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4484 4485 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4486 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4487 4488 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4489 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4490 4491 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4492 4493 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007f4) 4494 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007f4) 4495 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4496 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4497 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4498 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4499 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4500 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4501 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4502 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4503 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4504 do {\ 4505 HWIO_INTLOCK(); \ 4506 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4507 HWIO_INTFREE();\ 4508 } while (0) 4509 4510 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4511 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4512 4513 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4514 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4515 4516 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4517 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4518 4519 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4520 4521 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007f8) 4522 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007f8) 4523 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4524 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4525 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4526 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4527 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4528 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4529 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4530 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4531 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4532 do {\ 4533 HWIO_INTLOCK(); \ 4534 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4535 HWIO_INTFREE();\ 4536 } while (0) 4537 4538 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4539 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4540 4541 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4542 4543 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000820) 4544 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000820) 4545 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4546 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4547 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4548 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4549 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4550 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4551 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4552 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4553 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4554 do {\ 4555 HWIO_INTLOCK(); \ 4556 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4557 HWIO_INTFREE();\ 4558 } while (0) 4559 4560 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4561 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4562 4563 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4564 4565 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000824) 4566 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000824) 4567 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4568 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4569 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4570 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4571 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4572 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4573 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4574 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4575 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4576 do {\ 4577 HWIO_INTLOCK(); \ 4578 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4579 HWIO_INTFREE();\ 4580 } while (0) 4581 4582 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4583 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4584 4585 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4586 4587 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000828) 4588 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000828) 4589 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4590 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4591 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4592 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4593 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4594 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4595 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4596 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4597 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4598 do {\ 4599 HWIO_INTLOCK(); \ 4600 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4601 HWIO_INTFREE();\ 4602 } while (0) 4603 4604 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4605 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4606 4607 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4608 4609 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000082c) 4610 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000082c) 4611 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4612 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4613 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4614 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4615 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4616 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4617 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4618 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4619 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4620 do {\ 4621 HWIO_INTLOCK(); \ 4622 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4623 HWIO_INTFREE();\ 4624 } while (0) 4625 4626 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4627 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4628 4629 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4630 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4631 4632 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4633 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4634 4635 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4636 4637 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000830) 4638 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000830) 4639 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4640 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4641 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4642 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4643 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4644 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4645 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4646 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4647 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4648 do {\ 4649 HWIO_INTLOCK(); \ 4650 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 4651 HWIO_INTFREE();\ 4652 } while (0) 4653 4654 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 4655 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 4656 4657 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 4658 4659 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000834) 4660 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000834) 4661 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 4662 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 4663 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 4664 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 4665 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 4666 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 4667 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 4668 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 4669 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 4670 do {\ 4671 HWIO_INTLOCK(); \ 4672 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 4673 HWIO_INTFREE();\ 4674 } while (0) 4675 4676 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 4677 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 4678 4679 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 4680 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 4681 4682 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 4683 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 4684 4685 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 4686 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 4687 4688 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 4689 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 4690 4691 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 4692 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 4693 4694 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 4695 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 4696 4697 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 4698 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 4699 4700 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 4701 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 4702 4703 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 4704 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 4705 4706 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 4707 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 4708 4709 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 4710 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 4711 4712 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 4713 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 4714 4715 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 4716 4717 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000838) 4718 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000838) 4719 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 4720 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 4721 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 4722 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 4723 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 4724 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 4725 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 4726 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 4727 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 4728 do {\ 4729 HWIO_INTLOCK(); \ 4730 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 4731 HWIO_INTFREE();\ 4732 } while (0) 4733 4734 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 4735 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 4736 4737 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 4738 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 4739 4740 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 4741 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 4742 4743 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 4744 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 4745 4746 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 4747 4748 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000083c) 4749 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000083c) 4750 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 4751 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 4752 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 4753 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 4754 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 4755 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 4756 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 4757 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 4758 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 4759 do {\ 4760 HWIO_INTLOCK(); \ 4761 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 4762 HWIO_INTFREE();\ 4763 } while (0) 4764 4765 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 4766 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 4767 4768 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 4769 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 4770 4771 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 4772 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 4773 4774 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 4775 4776 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000840) 4777 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000840) 4778 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 4779 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 4780 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 4781 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 4782 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 4783 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 4784 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 4785 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 4786 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 4787 do {\ 4788 HWIO_INTLOCK(); \ 4789 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 4790 HWIO_INTFREE();\ 4791 } while (0) 4792 4793 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 4794 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 4795 4796 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4797 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 4798 4799 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 4800 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 4801 4802 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 4803 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 4804 4805 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 4806 4807 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000844) 4808 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000844) 4809 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 4810 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 4811 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 4812 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 4813 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 4814 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 4815 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 4816 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 4817 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 4818 do {\ 4819 HWIO_INTLOCK(); \ 4820 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 4821 HWIO_INTFREE();\ 4822 } while (0) 4823 4824 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 4825 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 4826 4827 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4828 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 4829 4830 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 4831 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 4832 4833 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 4834 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 4835 4836 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 4837 4838 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000848) 4839 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000848) 4840 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x007fffff 4841 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 4842 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 4843 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 4844 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 4845 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 4846 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 4847 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 4848 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 4849 do {\ 4850 HWIO_INTLOCK(); \ 4851 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 4852 HWIO_INTFREE();\ 4853 } while (0) 4854 4855 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 4856 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 4857 4858 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 4859 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 4860 4861 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 4862 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 4863 4864 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 4865 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 4866 4867 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 4868 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 4869 4870 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 4871 4872 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000084c) 4873 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000084c) 4874 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 4875 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 4876 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 4877 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 4878 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 4879 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 4880 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 4881 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 4882 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 4883 do {\ 4884 HWIO_INTLOCK(); \ 4885 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 4886 HWIO_INTFREE();\ 4887 } while (0) 4888 4889 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 4890 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 4891 4892 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 4893 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 4894 4895 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 4896 4897 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000850) 4898 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000850) 4899 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 4900 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 4901 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 4902 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 4903 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 4904 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 4905 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 4906 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 4907 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 4908 do {\ 4909 HWIO_INTLOCK(); \ 4910 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 4911 HWIO_INTFREE();\ 4912 } while (0) 4913 4914 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 4915 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 4916 4917 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 4918 4919 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000854) 4920 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000854) 4921 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 4922 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 4923 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 4924 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 4925 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 4926 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 4927 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 4928 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 4929 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 4930 do {\ 4931 HWIO_INTLOCK(); \ 4932 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 4933 HWIO_INTFREE();\ 4934 } while (0) 4935 4936 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 4937 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 4938 4939 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 4940 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 4941 4942 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 4943 4944 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000858) 4945 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000858) 4946 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 4947 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 4948 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 4949 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 4950 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 4951 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 4952 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 4953 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 4954 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 4955 do {\ 4956 HWIO_INTLOCK(); \ 4957 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 4958 HWIO_INTFREE();\ 4959 } while (0) 4960 4961 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 4962 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 4963 4964 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 4965 4966 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x0000085c) 4967 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x0000085c) 4968 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 4969 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 4970 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 4971 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 4972 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 4973 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 4974 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 4975 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 4976 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 4977 do {\ 4978 HWIO_INTLOCK(); \ 4979 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 4980 HWIO_INTFREE();\ 4981 } while (0) 4982 4983 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 4984 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 4985 4986 //// Register TCL_R0_ASE_GST_SIZE //// 4987 4988 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000860) 4989 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000860) 4990 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 4991 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 4992 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 4993 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 4994 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 4995 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 4996 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 4997 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 4998 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 4999 do {\ 5000 HWIO_INTLOCK(); \ 5001 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5002 HWIO_INTFREE();\ 5003 } while (0) 5004 5005 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5006 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5007 5008 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5009 5010 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000864) 5011 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000864) 5012 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff07ff 5013 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5014 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5015 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5016 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5017 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5018 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5019 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5020 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5021 do {\ 5022 HWIO_INTLOCK(); \ 5023 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5024 HWIO_INTFREE();\ 5025 } while (0) 5026 5027 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5028 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5029 5030 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5031 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5032 5033 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5034 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5035 5036 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5037 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5038 5039 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5040 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5041 5042 //// Register TCL_R0_ASE_WATCHDOG //// 5043 5044 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000868) 5045 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000868) 5046 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5047 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5048 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5049 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5050 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5051 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5052 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5053 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5054 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5055 do {\ 5056 HWIO_INTLOCK(); \ 5057 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5058 HWIO_INTFREE();\ 5059 } while (0) 5060 5061 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5062 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5063 5064 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5065 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5066 5067 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5068 5069 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x0000086c) 5070 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x0000086c) 5071 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5072 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5073 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5074 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5075 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5076 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5077 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5078 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5079 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5080 do {\ 5081 HWIO_INTLOCK(); \ 5082 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5083 HWIO_INTFREE();\ 5084 } while (0) 5085 5086 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5087 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5088 5089 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5090 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5091 5092 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5093 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5094 5095 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000400 5096 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0xa 5097 5098 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000200 5099 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x9 5100 5101 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000100 5102 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x8 5103 5104 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5105 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5106 5107 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5108 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5109 5110 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5111 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5112 5113 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5114 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5115 5116 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5117 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5118 5119 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5120 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5121 5122 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5123 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5124 5125 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5126 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5127 5128 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5129 5130 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000870) 5131 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000870) 5132 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5133 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5134 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5135 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5136 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5137 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5138 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5139 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5140 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5141 do {\ 5142 HWIO_INTLOCK(); \ 5143 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5144 HWIO_INTFREE();\ 5145 } while (0) 5146 5147 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5148 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5149 5150 //// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// 5151 5152 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000874) 5153 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000874) 5154 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5155 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 5156 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ 5157 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) 5158 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5159 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5160 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5161 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) 5162 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5163 do {\ 5164 HWIO_INTLOCK(); \ 5165 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ 5166 HWIO_INTFREE();\ 5167 } while (0) 5168 5169 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5170 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5171 5172 //// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// 5173 5174 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000878) 5175 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000878) 5176 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5177 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 5178 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ 5179 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) 5180 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5181 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5182 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5183 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5184 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5185 do {\ 5186 HWIO_INTLOCK(); \ 5187 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ 5188 HWIO_INTFREE();\ 5189 } while (0) 5190 5191 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5192 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5193 5194 //// Register TCL_R0_FSE_GST_SIZE //// 5195 5196 #define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x0000087c) 5197 #define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x0000087c) 5198 #define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff 5199 #define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 5200 #define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ 5201 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) 5202 #define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ 5203 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 5204 #define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ 5205 out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) 5206 #define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ 5207 do {\ 5208 HWIO_INTLOCK(); \ 5209 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ 5210 HWIO_INTFREE();\ 5211 } while (0) 5212 5213 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff 5214 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 5215 5216 //// Register TCL_R0_FSE_SEARCH_CTRL //// 5217 5218 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x00000880) 5219 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x00000880) 5220 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff07ff 5221 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 5222 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ 5223 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) 5224 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ 5225 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 5226 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ 5227 out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) 5228 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ 5229 do {\ 5230 HWIO_INTLOCK(); \ 5231 out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ 5232 HWIO_INTFREE();\ 5233 } while (0) 5234 5235 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5236 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5237 5238 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5239 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5240 5241 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5242 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5243 5244 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5245 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5246 5247 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5248 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5249 5250 //// Register TCL_R0_FSE_WATCHDOG //// 5251 5252 #define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x00000884) 5253 #define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x00000884) 5254 #define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff 5255 #define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 5256 #define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ 5257 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) 5258 #define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ 5259 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 5260 #define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ 5261 out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) 5262 #define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ 5263 do {\ 5264 HWIO_INTLOCK(); \ 5265 out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ 5266 HWIO_INTFREE();\ 5267 } while (0) 5268 5269 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 5270 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 5271 5272 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5273 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 5274 5275 //// Register TCL_R0_FSE_CLKGATE_DISABLE //// 5276 5277 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000888) 5278 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000888) 5279 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff 5280 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 5281 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ 5282 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) 5283 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ 5284 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 5285 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ 5286 out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) 5287 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5288 do {\ 5289 HWIO_INTLOCK(); \ 5290 out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ 5291 HWIO_INTFREE();\ 5292 } while (0) 5293 5294 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5295 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5296 5297 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5298 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5299 5300 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5301 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5302 5303 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000400 5304 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_SHFT 0xa 5305 5306 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_BMSK 0x00000200 5307 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_SHFT 0x9 5308 5309 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000100 5310 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x8 5311 5312 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5313 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5314 5315 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5316 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5317 5318 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5319 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5320 5321 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5322 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5323 5324 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5325 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5326 5327 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5328 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5329 5330 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5331 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5332 5333 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5334 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5335 5336 //// Register TCL_R0_FSE_WRITE_BACK_PENDING //// 5337 5338 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x0000088c) 5339 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x0000088c) 5340 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 5341 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 5342 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ 5343 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) 5344 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ 5345 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 5346 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ 5347 out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) 5348 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5349 do {\ 5350 HWIO_INTLOCK(); \ 5351 out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ 5352 HWIO_INTFREE();\ 5353 } while (0) 5354 5355 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5356 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5357 5358 //// Register TCL_R1_SM_STATES_IX_0 //// 5359 5360 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) 5361 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) 5362 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5363 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5364 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5365 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5366 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5367 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5368 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5369 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5370 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5371 do {\ 5372 HWIO_INTLOCK(); \ 5373 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5374 HWIO_INTFREE();\ 5375 } while (0) 5376 5377 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5378 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5379 5380 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5381 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5382 5383 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5384 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5385 5386 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5387 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5388 5389 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 5390 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc 5391 5392 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5393 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5394 5395 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5396 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5397 5398 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5399 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5400 5401 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5402 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5403 5404 //// Register TCL_R1_SM_STATES_IX_1 //// 5405 5406 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) 5407 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) 5408 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff 5409 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5410 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5411 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5412 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5413 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5414 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5415 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5416 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5417 do {\ 5418 HWIO_INTLOCK(); \ 5419 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5420 HWIO_INTFREE();\ 5421 } while (0) 5422 5423 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 5424 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf 5425 5426 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5427 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5428 5429 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5430 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5431 5432 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5433 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5434 5435 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5436 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5437 5438 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5439 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5440 5441 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5442 5443 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) 5444 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) 5445 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x1fffffff 5446 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5447 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5448 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5449 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5450 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5451 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5452 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5453 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5454 do {\ 5455 HWIO_INTLOCK(); \ 5456 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5457 HWIO_INTFREE();\ 5458 } while (0) 5459 5460 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5461 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5462 5463 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5464 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5465 5466 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5467 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5468 5469 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5470 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5471 5472 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5473 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5474 5475 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5476 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5477 5478 //// Register TCL_R1_TESTBUS_LOW //// 5479 5480 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) 5481 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) 5482 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5483 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5484 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5485 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5486 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5487 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5488 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5489 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5490 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5491 do {\ 5492 HWIO_INTLOCK(); \ 5493 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5494 HWIO_INTFREE();\ 5495 } while (0) 5496 5497 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5498 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5499 5500 //// Register TCL_R1_TESTBUS_HIGH //// 5501 5502 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) 5503 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) 5504 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5505 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5506 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5507 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5508 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5509 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5510 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5511 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5512 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5513 do {\ 5514 HWIO_INTLOCK(); \ 5515 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5516 HWIO_INTFREE();\ 5517 } while (0) 5518 5519 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5520 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5521 5522 //// Register TCL_R1_EVENTMASK_IX_0 //// 5523 5524 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) 5525 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) 5526 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5527 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5528 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5529 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5530 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5531 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5532 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5533 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5534 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5535 do {\ 5536 HWIO_INTLOCK(); \ 5537 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5538 HWIO_INTFREE();\ 5539 } while (0) 5540 5541 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5542 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5543 5544 //// Register TCL_R1_EVENTMASK_IX_1 //// 5545 5546 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) 5547 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) 5548 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5549 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5550 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5551 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5552 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5553 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5554 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5555 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5556 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5557 do {\ 5558 HWIO_INTLOCK(); \ 5559 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5560 HWIO_INTFREE();\ 5561 } while (0) 5562 5563 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5564 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5565 5566 //// Register TCL_R1_EVENTMASK_IX_2 //// 5567 5568 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) 5569 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) 5570 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5571 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5572 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5573 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5574 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5575 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5576 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5577 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5578 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5579 do {\ 5580 HWIO_INTLOCK(); \ 5581 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5582 HWIO_INTFREE();\ 5583 } while (0) 5584 5585 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5586 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5587 5588 //// Register TCL_R1_EVENTMASK_IX_3 //// 5589 5590 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) 5591 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) 5592 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5593 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5594 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5595 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5596 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5597 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5598 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5599 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5600 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5601 do {\ 5602 HWIO_INTLOCK(); \ 5603 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5604 HWIO_INTFREE();\ 5605 } while (0) 5606 5607 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5608 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5609 5610 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5611 5612 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) 5613 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) 5614 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5615 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5616 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5617 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5618 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5619 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5620 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5621 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5622 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5623 do {\ 5624 HWIO_INTLOCK(); \ 5625 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5626 HWIO_INTFREE();\ 5627 } while (0) 5628 5629 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5630 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5631 5632 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5633 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5634 5635 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5636 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5637 5638 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5639 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5640 5641 //// Register TCL_R1_END_OF_TEST_CHECK //// 5642 5643 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) 5644 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) 5645 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5646 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5647 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5648 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5649 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5650 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5651 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5652 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5653 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5654 do {\ 5655 HWIO_INTLOCK(); \ 5656 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5657 HWIO_INTFREE();\ 5658 } while (0) 5659 5660 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5661 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5662 5663 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5664 5665 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 5666 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 5667 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5668 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5669 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5670 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5671 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5672 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5673 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5674 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5675 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5676 do {\ 5677 HWIO_INTLOCK(); \ 5678 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5679 HWIO_INTFREE();\ 5680 } while (0) 5681 5682 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5683 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5684 5685 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5686 5687 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) 5688 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) 5689 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5690 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5691 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5692 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5693 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5694 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5695 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5696 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5697 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5698 do {\ 5699 HWIO_INTLOCK(); \ 5700 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5701 HWIO_INTFREE();\ 5702 } while (0) 5703 5704 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5705 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5706 5707 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5708 5709 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) 5710 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) 5711 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5712 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5713 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5714 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5715 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5716 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5717 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5718 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5719 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5720 do {\ 5721 HWIO_INTLOCK(); \ 5722 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5723 HWIO_INTFREE();\ 5724 } while (0) 5725 5726 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5727 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5728 5729 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 5730 5731 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) 5732 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) 5733 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5734 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5735 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5736 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 5737 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 5738 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 5739 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 5740 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 5741 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 5742 do {\ 5743 HWIO_INTLOCK(); \ 5744 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 5745 HWIO_INTFREE();\ 5746 } while (0) 5747 5748 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 5749 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 5750 5751 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 5752 5753 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) 5754 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) 5755 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 5756 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 5757 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 5758 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 5759 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 5760 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 5761 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 5762 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 5763 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 5764 do {\ 5765 HWIO_INTLOCK(); \ 5766 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 5767 HWIO_INTFREE();\ 5768 } while (0) 5769 5770 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 5771 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 5772 5773 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 5774 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 5775 5776 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 5777 5778 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) 5779 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) 5780 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 5781 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 5782 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 5783 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 5784 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 5785 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 5786 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 5787 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 5788 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 5789 do {\ 5790 HWIO_INTLOCK(); \ 5791 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 5792 HWIO_INTFREE();\ 5793 } while (0) 5794 5795 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 5796 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 5797 5798 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 5799 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 5800 5801 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 5802 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 5803 5804 //// Register TCL_R1_ASE_SM_STATES //// 5805 5806 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) 5807 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) 5808 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff 5809 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 5810 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 5811 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 5812 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 5813 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 5814 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 5815 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 5816 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 5817 do {\ 5818 HWIO_INTLOCK(); \ 5819 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 5820 HWIO_INTFREE();\ 5821 } while (0) 5822 5823 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 5824 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 5825 5826 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 5827 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 5828 5829 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 5830 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 5831 5832 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 5833 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 5834 5835 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 5836 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 5837 5838 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 5839 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 5840 5841 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 5842 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 5843 5844 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 5845 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 5846 5847 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 5848 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 5849 5850 //// Register TCL_R1_ASE_CACHE_DEBUG //// 5851 5852 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) 5853 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) 5854 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 5855 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 5856 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 5857 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 5858 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 5859 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 5860 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 5861 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 5862 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 5863 do {\ 5864 HWIO_INTLOCK(); \ 5865 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 5866 HWIO_INTFREE();\ 5867 } while (0) 5868 5869 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 5870 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 5871 5872 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 5873 5874 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) 5875 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) 5876 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 5877 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 5878 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 5879 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 5880 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 5881 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 5882 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 5883 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 5884 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 5885 do {\ 5886 HWIO_INTLOCK(); \ 5887 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 5888 HWIO_INTFREE();\ 5889 } while (0) 5890 5891 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 5892 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 5893 5894 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 5895 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 5896 5897 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 5898 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 5899 5900 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 5901 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 5902 5903 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 5904 5905 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) 5906 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) 5907 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 5908 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 5909 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 5910 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 5911 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 5912 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 5913 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 5914 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 5915 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 5916 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 5917 do {\ 5918 HWIO_INTLOCK(); \ 5919 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 5920 HWIO_INTFREE();\ 5921 } while (0) 5922 5923 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 5924 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 5925 5926 //// Register TCL_R1_FSE_END_OF_TEST_CHECK //// 5927 5928 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) 5929 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) 5930 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 5931 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 5932 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ 5933 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) 5934 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ 5935 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 5936 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ 5937 out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) 5938 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5939 do {\ 5940 HWIO_INTLOCK(); \ 5941 out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ 5942 HWIO_INTFREE();\ 5943 } while (0) 5944 5945 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5946 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5947 5948 //// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// 5949 5950 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) 5951 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) 5952 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5953 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 5954 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5955 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) 5956 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5957 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5958 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5959 out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5960 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5961 do {\ 5962 HWIO_INTLOCK(); \ 5963 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5964 HWIO_INTFREE();\ 5965 } while (0) 5966 5967 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5968 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5969 5970 //// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5971 5972 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) 5973 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) 5974 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5975 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5976 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5977 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5978 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5979 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5980 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5981 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5982 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5983 do {\ 5984 HWIO_INTLOCK(); \ 5985 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5986 HWIO_INTFREE();\ 5987 } while (0) 5988 5989 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5990 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5991 5992 //// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// 5993 5994 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) 5995 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) 5996 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5997 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5998 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5999 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6000 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6001 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6002 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6003 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6004 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6005 do {\ 6006 HWIO_INTLOCK(); \ 6007 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6008 HWIO_INTFREE();\ 6009 } while (0) 6010 6011 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6012 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6013 6014 //// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6015 6016 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) 6017 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) 6018 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6019 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6020 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6021 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6022 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6023 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6024 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6025 out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6026 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6027 do {\ 6028 HWIO_INTLOCK(); \ 6029 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6030 HWIO_INTFREE();\ 6031 } while (0) 6032 6033 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6034 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6035 6036 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6037 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6038 6039 //// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// 6040 6041 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) 6042 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) 6043 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6044 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6045 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6046 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6047 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6048 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6049 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6050 out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6051 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6052 do {\ 6053 HWIO_INTLOCK(); \ 6054 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6055 HWIO_INTFREE();\ 6056 } while (0) 6057 6058 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6059 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6060 6061 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6062 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6063 6064 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6065 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6066 6067 //// Register TCL_R1_FSE_SM_STATES //// 6068 6069 #define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) 6070 #define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) 6071 #define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff 6072 #define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 6073 #define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ 6074 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) 6075 #define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ 6076 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 6077 #define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ 6078 out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) 6079 #define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ 6080 do {\ 6081 HWIO_INTLOCK(); \ 6082 out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ 6083 HWIO_INTFREE();\ 6084 } while (0) 6085 6086 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6087 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6088 6089 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6090 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6091 6092 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6093 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6094 6095 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6096 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6097 6098 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6099 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6100 6101 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6102 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6103 6104 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6105 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6106 6107 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6108 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6109 6110 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6111 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6112 6113 //// Register TCL_R1_FSE_CACHE_DEBUG //// 6114 6115 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) 6116 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) 6117 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff 6118 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 6119 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ 6120 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) 6121 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ 6122 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 6123 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ 6124 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) 6125 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ 6126 do {\ 6127 HWIO_INTLOCK(); \ 6128 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ 6129 HWIO_INTFREE();\ 6130 } while (0) 6131 6132 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6133 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6134 6135 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// 6136 6137 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) 6138 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) 6139 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6140 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6141 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6142 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6143 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6144 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6145 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6146 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6147 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6148 do {\ 6149 HWIO_INTLOCK(); \ 6150 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6151 HWIO_INTFREE();\ 6152 } while (0) 6153 6154 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6155 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6156 6157 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6158 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6159 6160 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6161 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6162 6163 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6164 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6165 6166 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// 6167 6168 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) 6169 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) 6170 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6171 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 6172 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 6173 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6174 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) 6175 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6176 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6177 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6178 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6179 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6180 do {\ 6181 HWIO_INTLOCK(); \ 6182 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6183 HWIO_INTFREE();\ 6184 } while (0) 6185 6186 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6187 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6188 6189 //// Register TCL_R2_SW2TCL1_RING_HP //// 6190 6191 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 6192 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 6193 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x0000ffff 6194 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 6195 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 6196 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 6197 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 6198 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 6199 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 6200 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 6201 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 6202 do {\ 6203 HWIO_INTLOCK(); \ 6204 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 6205 HWIO_INTFREE();\ 6206 } while (0) 6207 6208 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6209 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6210 6211 //// Register TCL_R2_SW2TCL1_RING_TP //// 6212 6213 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 6214 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 6215 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x0000ffff 6216 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 6217 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 6218 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 6219 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 6220 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 6221 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 6222 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 6223 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 6224 do {\ 6225 HWIO_INTLOCK(); \ 6226 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 6227 HWIO_INTFREE();\ 6228 } while (0) 6229 6230 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6231 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6232 6233 //// Register TCL_R2_SW2TCL2_RING_HP //// 6234 6235 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 6236 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 6237 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x0000ffff 6238 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 6239 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 6240 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 6241 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 6242 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 6243 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 6244 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 6245 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 6246 do {\ 6247 HWIO_INTLOCK(); \ 6248 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 6249 HWIO_INTFREE();\ 6250 } while (0) 6251 6252 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6253 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 6254 6255 //// Register TCL_R2_SW2TCL2_RING_TP //// 6256 6257 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 6258 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 6259 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x0000ffff 6260 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 6261 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 6262 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 6263 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 6264 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 6265 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 6266 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 6267 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 6268 do {\ 6269 HWIO_INTLOCK(); \ 6270 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 6271 HWIO_INTFREE();\ 6272 } while (0) 6273 6274 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6275 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 6276 6277 //// Register TCL_R2_SW2TCL3_RING_HP //// 6278 6279 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 6280 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 6281 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x0000ffff 6282 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 6283 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 6284 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 6285 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 6286 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 6287 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 6288 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 6289 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 6290 do {\ 6291 HWIO_INTLOCK(); \ 6292 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 6293 HWIO_INTFREE();\ 6294 } while (0) 6295 6296 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6297 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 6298 6299 //// Register TCL_R2_SW2TCL3_RING_TP //// 6300 6301 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 6302 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 6303 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x0000ffff 6304 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 6305 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 6306 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 6307 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 6308 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 6309 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 6310 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 6311 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 6312 do {\ 6313 HWIO_INTLOCK(); \ 6314 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 6315 HWIO_INTFREE();\ 6316 } while (0) 6317 6318 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6319 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 6320 6321 //// Register TCL_R2_SW2TCL_CMD_RING_HP //// 6322 6323 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) 6324 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) 6325 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x0000ffff 6326 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 6327 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ 6328 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) 6329 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ 6330 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 6331 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ 6332 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) 6333 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ 6334 do {\ 6335 HWIO_INTLOCK(); \ 6336 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ 6337 HWIO_INTFREE();\ 6338 } while (0) 6339 6340 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6341 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 6342 6343 //// Register TCL_R2_SW2TCL_CMD_RING_TP //// 6344 6345 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) 6346 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) 6347 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x0000ffff 6348 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 6349 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ 6350 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) 6351 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ 6352 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 6353 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ 6354 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) 6355 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ 6356 do {\ 6357 HWIO_INTLOCK(); \ 6358 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ 6359 HWIO_INTFREE();\ 6360 } while (0) 6361 6362 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6363 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 6364 6365 //// Register TCL_R2_FW2TCL1_RING_HP //// 6366 6367 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 6368 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 6369 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 6370 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 6371 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 6372 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 6373 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 6374 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 6375 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 6376 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 6377 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 6378 do {\ 6379 HWIO_INTLOCK(); \ 6380 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 6381 HWIO_INTFREE();\ 6382 } while (0) 6383 6384 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6385 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6386 6387 //// Register TCL_R2_FW2TCL1_RING_TP //// 6388 6389 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 6390 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 6391 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 6392 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 6393 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 6394 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 6395 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 6396 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 6397 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 6398 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 6399 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 6400 do {\ 6401 HWIO_INTLOCK(); \ 6402 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 6403 HWIO_INTFREE();\ 6404 } while (0) 6405 6406 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6407 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6408 6409 //// Register TCL_R2_TCL2TQM_RING_HP //// 6410 6411 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 6412 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 6413 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 6414 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 6415 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 6416 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 6417 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 6418 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 6419 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6420 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6421 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6422 do {\ 6423 HWIO_INTLOCK(); \ 6424 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6425 HWIO_INTFREE();\ 6426 } while (0) 6427 6428 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6429 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6430 6431 //// Register TCL_R2_TCL2TQM_RING_TP //// 6432 6433 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6434 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6435 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6436 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6437 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6438 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6439 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6440 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6441 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6442 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6443 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6444 do {\ 6445 HWIO_INTLOCK(); \ 6446 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 6447 HWIO_INTFREE();\ 6448 } while (0) 6449 6450 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6451 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 6452 6453 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 6454 6455 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 6456 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 6457 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 6458 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 6459 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 6460 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 6461 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 6462 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 6463 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 6464 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 6465 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 6466 do {\ 6467 HWIO_INTLOCK(); \ 6468 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 6469 HWIO_INTFREE();\ 6470 } while (0) 6471 6472 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6473 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 6474 6475 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 6476 6477 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 6478 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 6479 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 6480 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 6481 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 6482 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 6483 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 6484 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 6485 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 6486 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 6487 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 6488 do {\ 6489 HWIO_INTLOCK(); \ 6490 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 6491 HWIO_INTFREE();\ 6492 } while (0) 6493 6494 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6495 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 6496 6497 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 6498 6499 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 6500 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 6501 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 6502 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6503 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6504 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6505 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6506 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6507 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6508 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6509 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6510 do {\ 6511 HWIO_INTLOCK(); \ 6512 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6513 HWIO_INTFREE();\ 6514 } while (0) 6515 6516 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6517 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6518 6519 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6520 6521 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6522 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6523 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6524 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6525 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6526 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6527 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6528 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6529 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6530 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6531 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6532 do {\ 6533 HWIO_INTLOCK(); \ 6534 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6535 HWIO_INTFREE();\ 6536 } while (0) 6537 6538 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6539 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6540 6541 //// Register TCL_R2_TCL2FW_RING_HP //// 6542 6543 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6544 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6545 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6546 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6547 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6548 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6549 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6550 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6551 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6552 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6553 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6554 do {\ 6555 HWIO_INTLOCK(); \ 6556 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6557 HWIO_INTFREE();\ 6558 } while (0) 6559 6560 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6561 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6562 6563 //// Register TCL_R2_TCL2FW_RING_TP //// 6564 6565 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6566 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6567 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6568 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6569 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6570 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6571 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6572 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6573 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6574 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6575 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6576 do {\ 6577 HWIO_INTLOCK(); \ 6578 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6579 HWIO_INTFREE();\ 6580 } while (0) 6581 6582 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6583 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6584 6585 6586 #endif 6587 6588