1 
2 /*
3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4  * SPDX-License-Identifier: ISC
5  */
6 
7 
8 
9 
10 
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12 
13 
14 
15 
16 
17 
18 
19 #ifndef _WBM_RELEASE_RING_TX_H_
20 #define _WBM_RELEASE_RING_TX_H_
21 #if !defined(__ASSEMBLER__)
22 #endif
23 
24 #include "tx_rate_stats_info.h"
25 #include "buffer_addr_info.h"
26 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8
27 
28 
29 struct wbm_release_ring_tx {
30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
31              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
32              uint32_t release_source_module                                   :  3,
33                       bm_action                                               :  3,
34                       buffer_or_desc_type                                     :  3,
35                       first_msdu_index                                        :  4,
36                       tqm_release_reason                                      :  4,
37                       rbm_override_valid                                      :  1,
38                       rbm_override                                            :  4,
39                       reserved_2a                                             :  7,
40                       cache_id                                                :  1,
41                       cookie_conversion_status                                :  1,
42                       wbm_internal_error                                      :  1;
43              uint32_t tqm_status_number                                       : 24,
44                       transmit_count                                          :  7,
45                       sw_release_details_valid                                :  1;
46              uint32_t ack_frame_rssi                                          :  8,
47                       first_msdu                                              :  1,
48                       last_msdu                                               :  1,
49                       fw_tx_notify_frame                                      :  3,
50                       buffer_timestamp                                        : 19;
51              struct   tx_rate_stats_info                                        tx_rate_stats;
52              uint32_t sw_peer_id                                              : 16,
53                       tid                                                     :  4,
54                       tqm_status_number_31_24                                 :  8,
55                       looping_count                                           :  4;
56 #else
57              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
58              uint32_t wbm_internal_error                                      :  1,
59                       cookie_conversion_status                                :  1,
60                       cache_id                                                :  1,
61                       reserved_2a                                             :  7,
62                       rbm_override                                            :  4,
63                       rbm_override_valid                                      :  1,
64                       tqm_release_reason                                      :  4,
65                       first_msdu_index                                        :  4,
66                       buffer_or_desc_type                                     :  3,
67                       bm_action                                               :  3,
68                       release_source_module                                   :  3;
69              uint32_t sw_release_details_valid                                :  1,
70                       transmit_count                                          :  7,
71                       tqm_status_number                                       : 24;
72              uint32_t buffer_timestamp                                        : 19,
73                       fw_tx_notify_frame                                      :  3,
74                       last_msdu                                               :  1,
75                       first_msdu                                              :  1,
76                       ack_frame_rssi                                          :  8;
77              struct   tx_rate_stats_info                                        tx_rate_stats;
78              uint32_t looping_count                                           :  4,
79                       tqm_status_number_31_24                                 :  8,
80                       tid                                                     :  4,
81                       sw_peer_id                                              : 16;
82 #endif
83 };
84 
85 
86 
87 
88 
89 
90 
91 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
92 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
93 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
94 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
95 
96 
97 
98 
99 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
100 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
101 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
102 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
103 
104 
105 
106 
107 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
108 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
109 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
110 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
111 
112 
113 
114 
115 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
116 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
117 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
118 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
119 
120 
121 
122 
123 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
124 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
125 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
126 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
127 
128 
129 
130 
131 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET                                        0x00000008
132 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB                                           3
133 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB                                           5
134 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK                                          0x00000038
135 
136 
137 
138 
139 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
140 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 6
141 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 8
142 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
143 
144 
145 
146 
147 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
148 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB                                    9
149 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB                                    12
150 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
151 
152 
153 
154 
155 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET                               0x00000008
156 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB                                  13
157 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB                                  16
158 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK                                 0x0001e000
159 
160 
161 
162 
163 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET                               0x00000008
164 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB                                  17
165 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB                                  17
166 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK                                 0x00020000
167 
168 
169 
170 
171 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET                                     0x00000008
172 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB                                        18
173 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB                                        21
174 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK                                       0x003c0000
175 
176 
177 
178 
179 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
180 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         22
181 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         28
182 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0x1fc00000
183 
184 
185 
186 
187 #define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET                                         0x00000008
188 #define WBM_RELEASE_RING_TX_CACHE_ID_LSB                                            29
189 #define WBM_RELEASE_RING_TX_CACHE_ID_MSB                                            29
190 #define WBM_RELEASE_RING_TX_CACHE_ID_MASK                                           0x20000000
191 
192 
193 
194 
195 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
196 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB                            30
197 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB                            30
198 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK                           0x40000000
199 
200 
201 
202 
203 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
204 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB                                  31
205 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB                                  31
206 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
207 
208 
209 
210 
211 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
212 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
213 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   23
214 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0x00ffffff
215 
216 
217 
218 
219 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET                                   0x0000000c
220 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB                                      24
221 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB                                      30
222 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK                                     0x7f000000
223 
224 
225 
226 
227 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                         0x0000000c
228 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                            31
229 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                            31
230 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                           0x80000000
231 
232 
233 
234 
235 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET                                   0x00000010
236 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB                                      0
237 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB                                      7
238 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK                                     0x000000ff
239 
240 
241 
242 
243 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET                                       0x00000010
244 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB                                          8
245 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB                                          8
246 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK                                         0x00000100
247 
248 
249 
250 
251 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET                                        0x00000010
252 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB                                           9
253 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB                                           9
254 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK                                          0x00000200
255 
256 
257 
258 
259 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                               0x00000010
260 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB                                  10
261 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB                                  12
262 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK                                 0x00001c00
263 
264 
265 
266 
267 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET                                 0x00000010
268 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB                                    13
269 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB                                    31
270 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK                                   0xffffe000
271 
272 
273 
274 
275 
276 
277 
278 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET           0x00000014
279 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB              0
280 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB              0
281 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK             0x00000001
282 
283 
284 
285 
286 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                        0x00000014
287 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                           1
288 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                           3
289 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                          0x0000000e
290 
291 
292 
293 
294 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET                  0x00000014
295 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                     4
296 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                     7
297 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                    0x000000f0
298 
299 
300 
301 
302 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                      0x00000014
303 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                         8
304 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                         8
305 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                        0x00000100
306 
307 
308 
309 
310 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                      0x00000014
311 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                         9
312 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                         9
313 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                        0x00000200
314 
315 
316 
317 
318 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                       0x00000014
319 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                          10
320 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                          11
321 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                         0x00000c00
322 
323 
324 
325 
326 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                       0x00000014
327 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                          12
328 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                          15
329 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                         0x0000f000
330 
331 
332 
333 
334 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET                 0x00000014
335 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                    16
336 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                    16
337 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                   0x00010000
338 
339 
340 
341 
342 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                        0x00000014
343 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                           17
344 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                           28
345 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                          0x1ffe0000
346 
347 
348 
349 
350 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                       0x00000014
351 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                          29
352 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                          31
353 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                         0xe0000000
354 
355 
356 
357 
358 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET              0x00000018
359 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB                 0
360 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB                 31
361 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK                0xffffffff
362 
363 
364 
365 
366 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET                                       0x0000001c
367 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB                                          0
368 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB                                          15
369 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK                                         0x0000ffff
370 
371 
372 
373 
374 #define WBM_RELEASE_RING_TX_TID_OFFSET                                              0x0000001c
375 #define WBM_RELEASE_RING_TX_TID_LSB                                                 16
376 #define WBM_RELEASE_RING_TX_TID_MSB                                                 19
377 #define WBM_RELEASE_RING_TX_TID_MASK                                                0x000f0000
378 
379 
380 
381 
382 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET                          0x0000001c
383 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB                             20
384 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB                             27
385 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK                            0x0ff00000
386 
387 
388 
389 
390 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET                                    0x0000001c
391 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB                                       28
392 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB                                       31
393 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK                                      0xf0000000
394 
395 
396 
397 #endif
398