1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 20 #define _U_SIG_EHT_SU_MU_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 25 26 27 struct u_sig_eht_su_mu_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_version : 3, 30 transmit_bw : 3, 31 dl_ul_flag : 1, 32 bss_color_id : 6, 33 txop_duration : 7, 34 disregard_0a : 5, 35 validate_0b : 1, 36 reserved_0c : 6; 37 uint32_t eht_ppdu_sig_cmn_type : 2, 38 validate_1a : 1, 39 punctured_channel_information : 5, 40 validate_1b : 1, 41 mcs_of_eht_sig : 2, 42 num_eht_sig_symbols : 5, 43 crc : 4, 44 tail : 6, 45 dot11ax_su_extended : 1, 46 reserved_1d : 3, 47 rx_ndp : 1, 48 rx_integrity_check_passed : 1; 49 #else 50 uint32_t reserved_0c : 6, 51 validate_0b : 1, 52 disregard_0a : 5, 53 txop_duration : 7, 54 bss_color_id : 6, 55 dl_ul_flag : 1, 56 transmit_bw : 3, 57 phy_version : 3; 58 uint32_t rx_integrity_check_passed : 1, 59 rx_ndp : 1, 60 reserved_1d : 3, 61 dot11ax_su_extended : 1, 62 tail : 6, 63 crc : 4, 64 num_eht_sig_symbols : 5, 65 mcs_of_eht_sig : 2, 66 validate_1b : 1, 67 punctured_channel_information : 5, 68 validate_1a : 1, 69 eht_ppdu_sig_cmn_type : 2; 70 #endif 71 }; 72 73 74 75 76 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 77 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 78 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 79 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 80 81 82 83 84 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 85 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 86 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 87 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 88 89 90 91 92 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 93 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 94 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 95 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 96 97 98 99 100 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 101 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 102 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 103 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 104 105 106 107 108 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 109 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 110 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 111 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 112 113 114 115 116 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 117 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 118 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 119 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 120 121 122 123 124 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 125 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 126 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 127 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 128 129 130 131 132 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 133 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 134 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 135 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 136 137 138 139 140 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 141 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 142 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 143 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 144 145 146 147 148 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 149 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 150 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 151 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 152 153 154 155 156 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 157 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 158 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 159 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 160 161 162 163 164 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 165 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 166 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 167 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 168 169 170 171 172 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 173 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 174 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 175 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 176 177 178 179 180 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 181 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 182 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 183 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 184 185 186 187 188 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 189 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 190 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 191 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 192 193 194 195 196 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 197 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 198 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 199 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 200 201 202 203 204 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 205 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 206 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 207 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 208 209 210 211 212 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 213 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 214 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 215 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 216 217 218 219 220 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 221 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 222 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 223 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 224 225 226 227 228 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 229 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 230 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 231 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 232 233 234 235 #endif 236