1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TXPCU_BUFFER_BASICS_H_ 20 #define _TXPCU_BUFFER_BASICS_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 25 26 27 struct txpcu_buffer_basics { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t available_memory : 8, 30 partial_tx_data_tlv_count : 8, 31 tx_data_tlv_count : 16; 32 #else 33 uint32_t tx_data_tlv_count : 16, 34 partial_tx_data_tlv_count : 8, 35 available_memory : 8; 36 #endif 37 }; 38 39 40 41 42 #define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 43 #define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 44 #define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 45 #define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff 46 47 48 49 50 #define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 51 #define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 52 #define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 53 #define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 54 55 56 57 58 #define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 59 #define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 60 #define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 61 #define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 62 63 64 65 #endif 66