1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_MSDU_START_H_ 20 #define _TX_MSDU_START_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_MSDU_START 8 25 26 #define NUM_OF_QWORDS_TX_MSDU_START 4 27 28 29 struct tx_msdu_start { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t msdu_len : 14, 32 first_msdu : 1, 33 last_msdu : 1, 34 encap_type : 2, 35 epd_en : 1, 36 da_sa_present : 2, 37 ipv4_checksum_en : 1, 38 udp_over_ipv4_checksum_en : 1, 39 udp_over_ipv6_checksum_en : 1, 40 tcp_over_ipv4_checksum_en : 1, 41 tcp_over_ipv6_checksum_en : 1, 42 dummy_msdu_delimitation : 1, 43 reserved_0a : 5; 44 uint32_t tso_enable : 1, 45 reserved_1a : 6, 46 tcp_flag : 9, 47 tcp_flag_mask : 9, 48 mesh_enable : 1, 49 reserved_1b : 6; 50 uint32_t l2_length : 16, 51 ip_length : 16; 52 uint32_t tcp_seq_number : 32; 53 uint32_t ip_identification : 16, 54 checksum_offset : 13, 55 partial_checksum_en : 1, 56 reserved_4 : 2; 57 uint32_t payload_start_offset : 14, 58 reserved_5a : 2, 59 payload_end_offset : 14, 60 reserved_5b : 2; 61 uint32_t udp_length : 16, 62 reserved_6 : 16; 63 uint32_t tlv64_padding : 32; 64 #else 65 uint32_t reserved_0a : 5, 66 dummy_msdu_delimitation : 1, 67 tcp_over_ipv6_checksum_en : 1, 68 tcp_over_ipv4_checksum_en : 1, 69 udp_over_ipv6_checksum_en : 1, 70 udp_over_ipv4_checksum_en : 1, 71 ipv4_checksum_en : 1, 72 da_sa_present : 2, 73 epd_en : 1, 74 encap_type : 2, 75 last_msdu : 1, 76 first_msdu : 1, 77 msdu_len : 14; 78 uint32_t reserved_1b : 6, 79 mesh_enable : 1, 80 tcp_flag_mask : 9, 81 tcp_flag : 9, 82 reserved_1a : 6, 83 tso_enable : 1; 84 uint32_t ip_length : 16, 85 l2_length : 16; 86 uint32_t tcp_seq_number : 32; 87 uint32_t reserved_4 : 2, 88 partial_checksum_en : 1, 89 checksum_offset : 13, 90 ip_identification : 16; 91 uint32_t reserved_5b : 2, 92 payload_end_offset : 14, 93 reserved_5a : 2, 94 payload_start_offset : 14; 95 uint32_t reserved_6 : 16, 96 udp_length : 16; 97 uint32_t tlv64_padding : 32; 98 #endif 99 }; 100 101 102 103 104 #define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 105 #define TX_MSDU_START_MSDU_LEN_LSB 0 106 #define TX_MSDU_START_MSDU_LEN_MSB 13 107 #define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff 108 109 110 111 112 #define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 113 #define TX_MSDU_START_FIRST_MSDU_LSB 14 114 #define TX_MSDU_START_FIRST_MSDU_MSB 14 115 #define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 116 117 118 119 120 #define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 121 #define TX_MSDU_START_LAST_MSDU_LSB 15 122 #define TX_MSDU_START_LAST_MSDU_MSB 15 123 #define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 124 125 126 127 128 #define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 129 #define TX_MSDU_START_ENCAP_TYPE_LSB 16 130 #define TX_MSDU_START_ENCAP_TYPE_MSB 17 131 #define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 132 133 134 135 136 #define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 137 #define TX_MSDU_START_EPD_EN_LSB 18 138 #define TX_MSDU_START_EPD_EN_MSB 18 139 #define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 140 141 142 143 144 #define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 145 #define TX_MSDU_START_DA_SA_PRESENT_LSB 19 146 #define TX_MSDU_START_DA_SA_PRESENT_MSB 20 147 #define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 148 149 150 151 152 #define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 153 #define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 154 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 155 #define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 156 157 158 159 160 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 161 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 162 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 163 #define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 164 165 166 167 168 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 169 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 170 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 171 #define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 172 173 174 175 176 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 177 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 178 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 179 #define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 180 181 182 183 184 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 185 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 186 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 187 #define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 188 189 190 191 192 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 193 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 194 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 195 #define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 196 197 198 199 200 #define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 201 #define TX_MSDU_START_RESERVED_0A_LSB 27 202 #define TX_MSDU_START_RESERVED_0A_MSB 31 203 #define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 204 205 206 207 208 #define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 209 #define TX_MSDU_START_TSO_ENABLE_LSB 32 210 #define TX_MSDU_START_TSO_ENABLE_MSB 32 211 #define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 212 213 214 215 216 #define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 217 #define TX_MSDU_START_RESERVED_1A_LSB 33 218 #define TX_MSDU_START_RESERVED_1A_MSB 38 219 #define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 220 221 222 223 224 #define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 225 #define TX_MSDU_START_TCP_FLAG_LSB 39 226 #define TX_MSDU_START_TCP_FLAG_MSB 47 227 #define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 228 229 230 231 232 #define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 233 #define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 234 #define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 235 #define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 236 237 238 239 240 #define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 241 #define TX_MSDU_START_MESH_ENABLE_LSB 57 242 #define TX_MSDU_START_MESH_ENABLE_MSB 57 243 #define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 244 245 246 247 248 #define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 249 #define TX_MSDU_START_RESERVED_1B_LSB 58 250 #define TX_MSDU_START_RESERVED_1B_MSB 63 251 #define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 252 253 254 255 256 #define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 257 #define TX_MSDU_START_L2_LENGTH_LSB 0 258 #define TX_MSDU_START_L2_LENGTH_MSB 15 259 #define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff 260 261 262 263 264 #define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 265 #define TX_MSDU_START_IP_LENGTH_LSB 16 266 #define TX_MSDU_START_IP_LENGTH_MSB 31 267 #define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 268 269 270 271 272 #define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 273 #define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 274 #define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 275 #define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 276 277 278 279 280 #define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 281 #define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 282 #define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 283 #define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff 284 285 286 287 288 #define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 289 #define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 290 #define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 291 #define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 292 293 294 295 296 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 297 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 298 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 299 #define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 300 301 302 303 304 #define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 305 #define TX_MSDU_START_RESERVED_4_LSB 30 306 #define TX_MSDU_START_RESERVED_4_MSB 31 307 #define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 308 309 310 311 312 #define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 313 #define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 314 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 315 #define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 316 317 318 319 320 #define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 321 #define TX_MSDU_START_RESERVED_5A_LSB 46 322 #define TX_MSDU_START_RESERVED_5A_MSB 47 323 #define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 324 325 326 327 328 #define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 329 #define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 330 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 331 #define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 332 333 334 335 336 #define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 337 #define TX_MSDU_START_RESERVED_5B_LSB 62 338 #define TX_MSDU_START_RESERVED_5B_MSB 63 339 #define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 340 341 342 343 344 #define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 345 #define TX_MSDU_START_UDP_LENGTH_LSB 0 346 #define TX_MSDU_START_UDP_LENGTH_MSB 15 347 #define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff 348 349 350 351 352 #define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 353 #define TX_MSDU_START_RESERVED_6_LSB 16 354 #define TX_MSDU_START_RESERVED_6_MSB 31 355 #define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 356 357 358 359 360 #define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 361 #define TX_MSDU_START_TLV64_PADDING_LSB 32 362 #define TX_MSDU_START_TLV64_PADDING_MSB 63 363 #define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 364 365 366 367 #endif 368