1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_MSDU_EXTENSION_H_ 20 #define _TX_MSDU_EXTENSION_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 25 26 27 struct tx_msdu_extension { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t tso_enable : 1, 30 reserved_0a : 6, 31 tcp_flag : 9, 32 tcp_flag_mask : 9, 33 reserved_0b : 7; 34 uint32_t l2_length : 16, 35 ip_length : 16; 36 uint32_t tcp_seq_number : 32; 37 uint32_t ip_identification : 16, 38 udp_length : 16; 39 uint32_t checksum_offset : 14, 40 partial_checksum_en : 1, 41 reserved_4a : 1, 42 payload_start_offset : 14, 43 reserved_4b : 2; 44 uint32_t payload_end_offset : 14, 45 reserved_5a : 2, 46 wds : 1, 47 reserved_5b : 15; 48 uint32_t buf0_ptr_31_0 : 32; 49 uint32_t buf0_ptr_39_32 : 8, 50 extn_override : 1, 51 encap_type : 2, 52 encrypt_type : 4, 53 tqm_no_drop : 1, 54 buf0_len : 16; 55 uint32_t buf1_ptr_31_0 : 32; 56 uint32_t buf1_ptr_39_32 : 8, 57 epd : 1, 58 mesh_enable : 2, 59 reserved_9a : 5, 60 buf1_len : 16; 61 uint32_t buf2_ptr_31_0 : 32; 62 uint32_t buf2_ptr_39_32 : 8, 63 dscp_tid_table_num : 6, 64 reserved_11a : 2, 65 buf2_len : 16; 66 uint32_t buf3_ptr_31_0 : 32; 67 uint32_t buf3_ptr_39_32 : 8, 68 reserved_13a : 8, 69 buf3_len : 16; 70 uint32_t buf4_ptr_31_0 : 32; 71 uint32_t buf4_ptr_39_32 : 8, 72 reserved_15a : 8, 73 buf4_len : 16; 74 uint32_t buf5_ptr_31_0 : 32; 75 uint32_t buf5_ptr_39_32 : 8, 76 reserved_17a : 8, 77 buf5_len : 16; 78 #else 79 uint32_t reserved_0b : 7, 80 tcp_flag_mask : 9, 81 tcp_flag : 9, 82 reserved_0a : 6, 83 tso_enable : 1; 84 uint32_t ip_length : 16, 85 l2_length : 16; 86 uint32_t tcp_seq_number : 32; 87 uint32_t udp_length : 16, 88 ip_identification : 16; 89 uint32_t reserved_4b : 2, 90 payload_start_offset : 14, 91 reserved_4a : 1, 92 partial_checksum_en : 1, 93 checksum_offset : 14; 94 uint32_t reserved_5b : 15, 95 wds : 1, 96 reserved_5a : 2, 97 payload_end_offset : 14; 98 uint32_t buf0_ptr_31_0 : 32; 99 uint32_t buf0_len : 16, 100 tqm_no_drop : 1, 101 encrypt_type : 4, 102 encap_type : 2, 103 extn_override : 1, 104 buf0_ptr_39_32 : 8; 105 uint32_t buf1_ptr_31_0 : 32; 106 uint32_t buf1_len : 16, 107 reserved_9a : 5, 108 mesh_enable : 2, 109 epd : 1, 110 buf1_ptr_39_32 : 8; 111 uint32_t buf2_ptr_31_0 : 32; 112 uint32_t buf2_len : 16, 113 reserved_11a : 2, 114 dscp_tid_table_num : 6, 115 buf2_ptr_39_32 : 8; 116 uint32_t buf3_ptr_31_0 : 32; 117 uint32_t buf3_len : 16, 118 reserved_13a : 8, 119 buf3_ptr_39_32 : 8; 120 uint32_t buf4_ptr_31_0 : 32; 121 uint32_t buf4_len : 16, 122 reserved_15a : 8, 123 buf4_ptr_39_32 : 8; 124 uint32_t buf5_ptr_31_0 : 32; 125 uint32_t buf5_len : 16, 126 reserved_17a : 8, 127 buf5_ptr_39_32 : 8; 128 #endif 129 }; 130 131 132 133 134 #define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 135 #define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 136 #define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 137 #define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 138 139 140 141 142 #define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 143 #define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 144 #define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 145 #define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e 146 147 148 149 150 #define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 151 #define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 152 #define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 153 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 154 155 156 157 158 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 159 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 160 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 161 #define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 162 163 164 165 166 #define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 167 #define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 168 #define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 169 #define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 170 171 172 173 174 #define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 175 #define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 176 #define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 177 #define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff 178 179 180 181 182 #define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 183 #define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 184 #define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 185 #define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 186 187 188 189 190 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 191 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 192 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 193 #define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff 194 195 196 197 198 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c 199 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 200 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 201 #define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff 202 203 204 205 206 #define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c 207 #define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 208 #define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 209 #define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 210 211 212 213 214 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 215 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 216 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 217 #define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff 218 219 220 221 222 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 223 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 224 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 225 #define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 226 227 228 229 230 #define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 231 #define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 232 #define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 233 #define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 234 235 236 237 238 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 239 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 240 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 241 #define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 242 243 244 245 246 #define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 247 #define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 248 #define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 249 #define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 250 251 252 253 254 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 255 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 256 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 257 #define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff 258 259 260 261 262 #define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 263 #define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 264 #define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 265 #define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 266 267 268 269 270 #define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 271 #define TX_MSDU_EXTENSION_WDS_LSB 16 272 #define TX_MSDU_EXTENSION_WDS_MSB 16 273 #define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 274 275 276 277 278 #define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 279 #define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 280 #define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 281 #define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 282 283 284 285 286 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 287 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 288 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 289 #define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff 290 291 292 293 294 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c 295 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 296 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 297 #define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff 298 299 300 301 302 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c 303 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 304 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 305 #define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 306 307 308 309 310 #define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c 311 #define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 312 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 313 #define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 314 315 316 317 318 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c 319 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 320 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 321 #define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 322 323 324 325 326 #define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c 327 #define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 328 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 329 #define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 330 331 332 333 334 #define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c 335 #define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 336 #define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 337 #define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 338 339 340 341 342 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 343 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 344 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 345 #define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff 346 347 348 349 350 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 351 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 352 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 353 #define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff 354 355 356 357 358 #define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 359 #define TX_MSDU_EXTENSION_EPD_LSB 8 360 #define TX_MSDU_EXTENSION_EPD_MSB 8 361 #define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 362 363 364 365 366 #define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 367 #define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 368 #define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 369 #define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 370 371 372 373 374 #define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 375 #define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 376 #define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 377 #define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 378 379 380 381 382 #define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 383 #define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 384 #define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 385 #define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 386 387 388 389 390 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 391 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 392 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 393 #define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff 394 395 396 397 398 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c 399 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 400 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 401 #define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff 402 403 404 405 406 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c 407 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 408 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 409 #define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 410 411 412 413 414 #define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c 415 #define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 416 #define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 417 #define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 418 419 420 421 422 #define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c 423 #define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 424 #define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 425 #define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 426 427 428 429 430 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 431 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 432 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 433 #define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff 434 435 436 437 438 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 439 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 440 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 441 #define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff 442 443 444 445 446 #define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 447 #define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 448 #define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 449 #define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 450 451 452 453 454 #define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 455 #define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 456 #define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 457 #define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 458 459 460 461 462 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 463 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 464 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 465 #define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff 466 467 468 469 470 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c 471 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 472 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 473 #define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff 474 475 476 477 478 #define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c 479 #define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 480 #define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 481 #define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 482 483 484 485 486 #define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c 487 #define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 488 #define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 489 #define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 490 491 492 493 494 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 495 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 496 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 497 #define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff 498 499 500 501 502 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 503 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 504 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 505 #define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff 506 507 508 509 510 #define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 511 #define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 512 #define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 513 #define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 514 515 516 517 518 #define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 519 #define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 520 #define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 521 #define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 522 523 524 525 #endif 526