1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FLUSH_REQ_H_ 20 #define _TX_FLUSH_REQ_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_FLUSH_REQ 2 25 26 #define NUM_OF_QWORDS_TX_FLUSH_REQ 1 27 28 29 struct tx_flush_req { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t flush_req_reason : 8, 32 phytx_abort_reason : 8, 33 flush_req_user_number_or_link_id : 6, 34 mlo_abort_reason : 5, 35 reserved_0a : 5; 36 uint32_t tlv64_padding : 32; 37 #else 38 uint32_t reserved_0a : 5, 39 mlo_abort_reason : 5, 40 flush_req_user_number_or_link_id : 6, 41 phytx_abort_reason : 8, 42 flush_req_reason : 8; 43 uint32_t tlv64_padding : 32; 44 #endif 45 }; 46 47 48 49 50 #define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 51 #define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 52 #define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 53 #define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff 54 55 56 57 58 #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 59 #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 60 #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 61 #define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 62 63 64 65 66 #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 67 #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 68 #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 69 #define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 70 71 72 73 74 #define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 75 #define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 76 #define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 77 #define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 78 79 80 81 82 #define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 83 #define TX_FLUSH_REQ_RESERVED_0A_LSB 27 84 #define TX_FLUSH_REQ_RESERVED_0A_MSB 31 85 #define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 86 87 88 89 90 #define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 91 #define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 92 #define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 93 #define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 94 95 96 97 #endif 98