1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_STATUS_ACK_OR_BA_H_ 20 #define _TX_FES_STATUS_ACK_OR_BA_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 25 26 #define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 27 28 29 struct tx_fes_status_ack_or_ba { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t ack_ba_status_type : 1, 32 ba_type : 1, 33 ba_tid : 4, 34 unexpected_ack_or_ba : 1, 35 response_timeout : 1, 36 ack_frame_rssi : 8, 37 ssn : 12, 38 reserved_0b : 4; 39 uint32_t sw_peer_id : 16, 40 reserved_1a : 16; 41 uint32_t ba_bitmap_31_0 : 32; 42 uint32_t ba_bitmap_63_32 : 32; 43 uint32_t ba_bitmap_95_64 : 32; 44 uint32_t ba_bitmap_127_96 : 32; 45 uint32_t ba_bitmap_159_128 : 32; 46 uint32_t ba_bitmap_191_160 : 32; 47 uint32_t ba_bitmap_223_192 : 32; 48 uint32_t ba_bitmap_255_224 : 32; 49 #else 50 uint32_t reserved_0b : 4, 51 ssn : 12, 52 ack_frame_rssi : 8, 53 response_timeout : 1, 54 unexpected_ack_or_ba : 1, 55 ba_tid : 4, 56 ba_type : 1, 57 ack_ba_status_type : 1; 58 uint32_t reserved_1a : 16, 59 sw_peer_id : 16; 60 uint32_t ba_bitmap_31_0 : 32; 61 uint32_t ba_bitmap_63_32 : 32; 62 uint32_t ba_bitmap_95_64 : 32; 63 uint32_t ba_bitmap_127_96 : 32; 64 uint32_t ba_bitmap_159_128 : 32; 65 uint32_t ba_bitmap_191_160 : 32; 66 uint32_t ba_bitmap_223_192 : 32; 67 uint32_t ba_bitmap_255_224 : 32; 68 #endif 69 }; 70 71 72 73 74 #define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 75 #define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 76 #define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 77 #define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 78 79 80 81 82 #define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 83 #define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 84 #define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 85 #define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 86 87 88 89 90 #define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 91 #define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 92 #define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 93 #define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c 94 95 96 97 98 #define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 99 #define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 100 #define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 101 #define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 102 103 104 105 106 #define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 107 #define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 108 #define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 109 #define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 110 111 112 113 114 #define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 115 #define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 116 #define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 117 #define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 118 119 120 121 122 #define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 123 #define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 124 #define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 125 #define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 126 127 128 129 130 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 131 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 132 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 133 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 134 135 136 137 138 #define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 139 #define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 140 #define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 141 #define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 142 143 144 145 146 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 147 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 148 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 149 #define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 150 151 152 153 154 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 155 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 156 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 157 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 158 159 160 161 162 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 163 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 164 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 165 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 166 167 168 169 170 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 171 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 172 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 173 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 174 175 176 177 178 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 179 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 180 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 181 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 182 183 184 185 186 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 187 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 188 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 189 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 190 191 192 193 194 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 195 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 196 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 197 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 198 199 200 201 202 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 203 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 204 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 205 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 206 207 208 209 210 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 211 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 212 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 213 #define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 214 215 216 217 #endif 218