1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_STATUS_1K_BA_H_ 20 #define _TX_FES_STATUS_1K_BA_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 25 26 #define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 27 28 29 struct tx_fes_status_1k_ba { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t ack_ba_status_type : 1, 32 ba_type : 1, 33 ba_tid : 4, 34 unexpected_ack_or_ba : 1, 35 response_timeout : 1, 36 ack_frame_rssi : 8, 37 ssn : 12, 38 reserved_0b : 4; 39 uint32_t sw_peer_id : 16, 40 reserved_1a : 16; 41 uint32_t ba_bitmap_31_0 : 32; 42 uint32_t ba_bitmap_63_32 : 32; 43 uint32_t ba_bitmap_95_64 : 32; 44 uint32_t ba_bitmap_127_96 : 32; 45 uint32_t ba_bitmap_159_128 : 32; 46 uint32_t ba_bitmap_191_160 : 32; 47 uint32_t ba_bitmap_223_192 : 32; 48 uint32_t ba_bitmap_255_224 : 32; 49 uint32_t ba_bitmap_287_256 : 32; 50 uint32_t ba_bitmap_319_288 : 32; 51 uint32_t ba_bitmap_351_320 : 32; 52 uint32_t ba_bitmap_383_352 : 32; 53 uint32_t ba_bitmap_415_384 : 32; 54 uint32_t ba_bitmap_447_416 : 32; 55 uint32_t ba_bitmap_479_448 : 32; 56 uint32_t ba_bitmap_511_480 : 32; 57 uint32_t ba_bitmap_543_512 : 32; 58 uint32_t ba_bitmap_575_544 : 32; 59 uint32_t ba_bitmap_607_576 : 32; 60 uint32_t ba_bitmap_639_608 : 32; 61 uint32_t ba_bitmap_671_640 : 32; 62 uint32_t ba_bitmap_703_672 : 32; 63 uint32_t ba_bitmap_735_704 : 32; 64 uint32_t ba_bitmap_767_736 : 32; 65 uint32_t ba_bitmap_799_768 : 32; 66 uint32_t ba_bitmap_831_800 : 32; 67 uint32_t ba_bitmap_863_832 : 32; 68 uint32_t ba_bitmap_895_864 : 32; 69 uint32_t ba_bitmap_927_896 : 32; 70 uint32_t ba_bitmap_959_928 : 32; 71 uint32_t ba_bitmap_991_960 : 32; 72 uint32_t ba_bitmap_1023_992 : 32; 73 #else 74 uint32_t reserved_0b : 4, 75 ssn : 12, 76 ack_frame_rssi : 8, 77 response_timeout : 1, 78 unexpected_ack_or_ba : 1, 79 ba_tid : 4, 80 ba_type : 1, 81 ack_ba_status_type : 1; 82 uint32_t reserved_1a : 16, 83 sw_peer_id : 16; 84 uint32_t ba_bitmap_31_0 : 32; 85 uint32_t ba_bitmap_63_32 : 32; 86 uint32_t ba_bitmap_95_64 : 32; 87 uint32_t ba_bitmap_127_96 : 32; 88 uint32_t ba_bitmap_159_128 : 32; 89 uint32_t ba_bitmap_191_160 : 32; 90 uint32_t ba_bitmap_223_192 : 32; 91 uint32_t ba_bitmap_255_224 : 32; 92 uint32_t ba_bitmap_287_256 : 32; 93 uint32_t ba_bitmap_319_288 : 32; 94 uint32_t ba_bitmap_351_320 : 32; 95 uint32_t ba_bitmap_383_352 : 32; 96 uint32_t ba_bitmap_415_384 : 32; 97 uint32_t ba_bitmap_447_416 : 32; 98 uint32_t ba_bitmap_479_448 : 32; 99 uint32_t ba_bitmap_511_480 : 32; 100 uint32_t ba_bitmap_543_512 : 32; 101 uint32_t ba_bitmap_575_544 : 32; 102 uint32_t ba_bitmap_607_576 : 32; 103 uint32_t ba_bitmap_639_608 : 32; 104 uint32_t ba_bitmap_671_640 : 32; 105 uint32_t ba_bitmap_703_672 : 32; 106 uint32_t ba_bitmap_735_704 : 32; 107 uint32_t ba_bitmap_767_736 : 32; 108 uint32_t ba_bitmap_799_768 : 32; 109 uint32_t ba_bitmap_831_800 : 32; 110 uint32_t ba_bitmap_863_832 : 32; 111 uint32_t ba_bitmap_895_864 : 32; 112 uint32_t ba_bitmap_927_896 : 32; 113 uint32_t ba_bitmap_959_928 : 32; 114 uint32_t ba_bitmap_991_960 : 32; 115 uint32_t ba_bitmap_1023_992 : 32; 116 #endif 117 }; 118 119 120 121 122 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 123 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 124 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 125 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 126 127 128 129 130 #define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 131 #define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 132 #define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 133 #define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 134 135 136 137 138 #define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 139 #define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 140 #define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 141 #define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c 142 143 144 145 146 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 147 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 148 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 149 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 150 151 152 153 154 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 155 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 156 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 157 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 158 159 160 161 162 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 163 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 164 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 165 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 166 167 168 169 170 #define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 171 #define TX_FES_STATUS_1K_BA_SSN_LSB 16 172 #define TX_FES_STATUS_1K_BA_SSN_MSB 27 173 #define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 174 175 176 177 178 #define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 179 #define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 180 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 181 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 182 183 184 185 186 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 187 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 188 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 189 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 190 191 192 193 194 #define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 195 #define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 196 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 197 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 198 199 200 201 202 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 203 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 204 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 205 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 206 207 208 209 210 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 211 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 212 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 213 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 214 215 216 217 218 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 219 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 220 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 221 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 222 223 224 225 226 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 227 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 228 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 229 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 230 231 232 233 234 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 235 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 236 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 237 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 238 239 240 241 242 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 243 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 244 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 245 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 246 247 248 249 250 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 251 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 252 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 253 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 254 255 256 257 258 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 259 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 260 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 261 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 262 263 264 265 266 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 267 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 268 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 269 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff 270 271 272 273 274 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 275 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 276 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 277 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 278 279 280 281 282 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 283 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 284 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 285 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff 286 287 288 289 290 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 291 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 292 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 293 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 294 295 296 297 298 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 299 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 300 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 301 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff 302 303 304 305 306 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 307 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 308 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 309 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 310 311 312 313 314 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 315 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 316 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 317 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff 318 319 320 321 322 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 323 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 324 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 325 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 326 327 328 329 330 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 331 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 332 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 333 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff 334 335 336 337 338 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 339 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 340 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 341 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 342 343 344 345 346 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 347 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 348 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 349 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff 350 351 352 353 354 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 355 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 356 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 357 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 358 359 360 361 362 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 363 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 364 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 365 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff 366 367 368 369 370 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 371 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 372 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 373 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 374 375 376 377 378 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 379 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 380 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 381 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff 382 383 384 385 386 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 387 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 388 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 389 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 390 391 392 393 394 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 395 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 396 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 397 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff 398 399 400 401 402 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 403 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 404 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 405 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 406 407 408 409 410 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 411 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 412 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 413 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff 414 415 416 417 418 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 419 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 420 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 421 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 422 423 424 425 426 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 427 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 428 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 429 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff 430 431 432 433 434 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 435 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 436 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 437 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 438 439 440 441 442 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 443 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 444 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 445 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff 446 447 448 449 450 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 451 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 452 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 453 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 454 455 456 457 #endif 458