1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TX_FES_SETUP_H_ 20 #define _TX_FES_SETUP_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TX_FES_SETUP 10 25 26 #define NUM_OF_QWORDS_TX_FES_SETUP 5 27 28 29 struct tx_fes_setup { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t schedule_id : 32; 32 uint32_t fes_in_11ax_trigger_response_config : 1, 33 bo_based_tid_aggregation_limit : 4, 34 ranging : 1, 35 expect_i2r_lmr : 1, 36 transmit_start_reason : 3, 37 use_alt_power_sr : 1, 38 static_2_pwr_mode_status : 1, 39 obss_srg_opport_transmit_status : 1, 40 srp_based_transmit_status : 1, 41 obss_pd_based_transmit_status : 1, 42 puncture_from_all_allowed_modes : 1, 43 schedule_cmd_ring_id : 5, 44 fes_control_mode : 2, 45 number_of_users : 6, 46 mu_type : 1, 47 ofdma_triggered_response : 1, 48 response_to_response_cmd : 1; 49 uint32_t schedule_try : 4, 50 ndp_frame : 2, 51 txbf : 1, 52 allow_txop_exceed_in_1st_pkt : 1, 53 ignore_bw_available : 1, 54 ignore_tbtt : 1, 55 static_bandwidth : 3, 56 set_txop_duration_all_ones : 1, 57 transmission_contains_mu_rts : 1, 58 bw_restricted_frames_embedded : 1, 59 ast_index : 16; 60 uint32_t cv_id : 8, 61 trigger_resp_txpdu_ppdu_boundary : 2, 62 rxpcu_setup_complete_present : 1, 63 rbo_must_have_data_user_limit : 4, 64 mu_ndp : 1, 65 bf_type : 2, 66 cbf_nc_index_mask : 1, 67 cbf_nc_index : 3, 68 cbf_nr_index_mask : 1, 69 cbf_nr_index : 3, 70 secure_ranging_ista : 1, 71 ndpa : 1, 72 wait_sifs : 2, 73 cbf_feedback_type_mask : 1, 74 cbf_feedback_type : 1; 75 uint32_t cbf_sounding_token : 6, 76 cbf_sounding_token_mask : 1, 77 cbf_bw_mask : 1, 78 cbf_bw : 3, 79 use_static_bw : 1, 80 coex_nack_count : 5, 81 sch_tx_burst_ongoing : 1, 82 gen_tqm_update_mpdu_count_tlv : 1, 83 transmit_vif : 4, 84 optimal_bw_retry_count : 4, 85 fes_continuation_ratio_threshold : 5; 86 uint32_t transmit_cca_bitmap : 32; 87 uint32_t tb_ranging : 1, 88 ranging_trigger_subtype : 4, 89 min_cts2self_count : 4, 90 max_cts2self_count : 4, 91 wifi_radar_enable : 1, 92 reserved_6a : 18; 93 uint32_t monitor_override_sta_31_0 : 32; 94 uint32_t monitor_override_sta_36_32 : 5, 95 reserved_8a : 27; 96 uint32_t fw2sw_info : 32; 97 #else 98 uint32_t schedule_id : 32; 99 uint32_t response_to_response_cmd : 1, 100 ofdma_triggered_response : 1, 101 mu_type : 1, 102 number_of_users : 6, 103 fes_control_mode : 2, 104 schedule_cmd_ring_id : 5, 105 puncture_from_all_allowed_modes : 1, 106 obss_pd_based_transmit_status : 1, 107 srp_based_transmit_status : 1, 108 obss_srg_opport_transmit_status : 1, 109 static_2_pwr_mode_status : 1, 110 use_alt_power_sr : 1, 111 transmit_start_reason : 3, 112 expect_i2r_lmr : 1, 113 ranging : 1, 114 bo_based_tid_aggregation_limit : 4, 115 fes_in_11ax_trigger_response_config : 1; 116 uint32_t ast_index : 16, 117 bw_restricted_frames_embedded : 1, 118 transmission_contains_mu_rts : 1, 119 set_txop_duration_all_ones : 1, 120 static_bandwidth : 3, 121 ignore_tbtt : 1, 122 ignore_bw_available : 1, 123 allow_txop_exceed_in_1st_pkt : 1, 124 txbf : 1, 125 ndp_frame : 2, 126 schedule_try : 4; 127 uint32_t cbf_feedback_type : 1, 128 cbf_feedback_type_mask : 1, 129 wait_sifs : 2, 130 ndpa : 1, 131 secure_ranging_ista : 1, 132 cbf_nr_index : 3, 133 cbf_nr_index_mask : 1, 134 cbf_nc_index : 3, 135 cbf_nc_index_mask : 1, 136 bf_type : 2, 137 mu_ndp : 1, 138 rbo_must_have_data_user_limit : 4, 139 rxpcu_setup_complete_present : 1, 140 trigger_resp_txpdu_ppdu_boundary : 2, 141 cv_id : 8; 142 uint32_t fes_continuation_ratio_threshold : 5, 143 optimal_bw_retry_count : 4, 144 transmit_vif : 4, 145 gen_tqm_update_mpdu_count_tlv : 1, 146 sch_tx_burst_ongoing : 1, 147 coex_nack_count : 5, 148 use_static_bw : 1, 149 cbf_bw : 3, 150 cbf_bw_mask : 1, 151 cbf_sounding_token_mask : 1, 152 cbf_sounding_token : 6; 153 uint32_t transmit_cca_bitmap : 32; 154 uint32_t reserved_6a : 18, 155 wifi_radar_enable : 1, 156 max_cts2self_count : 4, 157 min_cts2self_count : 4, 158 ranging_trigger_subtype : 4, 159 tb_ranging : 1; 160 uint32_t monitor_override_sta_31_0 : 32; 161 uint32_t reserved_8a : 27, 162 monitor_override_sta_36_32 : 5; 163 uint32_t fw2sw_info : 32; 164 #endif 165 }; 166 167 168 169 170 #define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 171 #define TX_FES_SETUP_SCHEDULE_ID_LSB 0 172 #define TX_FES_SETUP_SCHEDULE_ID_MSB 31 173 #define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff 174 175 176 177 178 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 179 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 180 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 181 #define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 182 183 184 185 186 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 187 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 188 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 189 #define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 190 191 192 193 194 #define TX_FES_SETUP_RANGING_OFFSET 0x0000000000000000 195 #define TX_FES_SETUP_RANGING_LSB 37 196 #define TX_FES_SETUP_RANGING_MSB 37 197 #define TX_FES_SETUP_RANGING_MASK 0x0000002000000000 198 199 200 201 202 #define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 203 #define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 204 #define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 205 #define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 206 207 208 209 210 #define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 211 #define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 212 #define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 213 #define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 214 215 216 217 218 #define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 219 #define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 220 #define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 221 #define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 222 223 224 225 226 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 227 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 228 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 229 #define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 230 231 232 233 234 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 235 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 236 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 237 #define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 238 239 240 241 242 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 243 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 244 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 245 #define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 246 247 248 249 250 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 251 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 252 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 253 #define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 254 255 256 257 258 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 259 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 260 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 261 #define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 262 263 264 265 266 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 267 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 268 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 269 #define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 270 271 272 273 274 #define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 275 #define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 276 #define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 277 #define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 278 279 280 281 282 #define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 283 #define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 284 #define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 285 #define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 286 287 288 289 290 #define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 291 #define TX_FES_SETUP_MU_TYPE_LSB 61 292 #define TX_FES_SETUP_MU_TYPE_MSB 61 293 #define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 294 295 296 297 298 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 299 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 300 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 301 #define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 302 303 304 305 306 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 307 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 308 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 309 #define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 310 311 312 313 314 #define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 315 #define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 316 #define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 317 #define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f 318 319 320 321 322 #define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 323 #define TX_FES_SETUP_NDP_FRAME_LSB 4 324 #define TX_FES_SETUP_NDP_FRAME_MSB 5 325 #define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 326 327 328 329 330 #define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 331 #define TX_FES_SETUP_TXBF_LSB 6 332 #define TX_FES_SETUP_TXBF_MSB 6 333 #define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 334 335 336 337 338 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 339 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 340 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 341 #define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 342 343 344 345 346 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 347 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 348 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 349 #define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 350 351 352 353 354 #define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 355 #define TX_FES_SETUP_IGNORE_TBTT_LSB 9 356 #define TX_FES_SETUP_IGNORE_TBTT_MSB 9 357 #define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 358 359 360 361 362 #define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 363 #define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 364 #define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 365 #define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 366 367 368 369 370 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 371 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 372 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 373 #define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 374 375 376 377 378 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 379 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 380 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 381 #define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 382 383 384 385 386 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 387 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 388 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 389 #define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 390 391 392 393 394 #define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 395 #define TX_FES_SETUP_AST_INDEX_LSB 16 396 #define TX_FES_SETUP_AST_INDEX_MSB 31 397 #define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 398 399 400 401 402 #define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 403 #define TX_FES_SETUP_CV_ID_LSB 32 404 #define TX_FES_SETUP_CV_ID_MSB 39 405 #define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 406 407 408 409 410 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 411 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 412 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 413 #define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 414 415 416 417 418 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 419 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 420 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 421 #define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 422 423 424 425 426 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 427 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 428 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 429 #define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 430 431 432 433 434 #define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 435 #define TX_FES_SETUP_MU_NDP_LSB 47 436 #define TX_FES_SETUP_MU_NDP_MSB 47 437 #define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 438 439 440 441 442 #define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 443 #define TX_FES_SETUP_BF_TYPE_LSB 48 444 #define TX_FES_SETUP_BF_TYPE_MSB 49 445 #define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 446 447 448 449 450 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 451 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 452 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 453 #define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 454 455 456 457 458 #define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 459 #define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 460 #define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 461 #define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 462 463 464 465 466 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 467 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 468 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 469 #define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 470 471 472 473 474 #define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 475 #define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 476 #define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 477 #define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 478 479 480 481 482 #define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 483 #define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 484 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 485 #define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 486 487 488 489 490 #define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 491 #define TX_FES_SETUP_NDPA_LSB 59 492 #define TX_FES_SETUP_NDPA_MSB 59 493 #define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 494 495 496 497 498 #define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 499 #define TX_FES_SETUP_WAIT_SIFS_LSB 60 500 #define TX_FES_SETUP_WAIT_SIFS_MSB 61 501 #define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 502 503 504 505 506 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 507 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 508 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 509 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 510 511 512 513 514 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 515 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 516 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 517 #define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 518 519 520 521 522 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 523 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 524 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 525 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f 526 527 528 529 530 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 531 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 532 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 533 #define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 534 535 536 537 538 #define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 539 #define TX_FES_SETUP_CBF_BW_MASK_LSB 7 540 #define TX_FES_SETUP_CBF_BW_MASK_MSB 7 541 #define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 542 543 544 545 546 #define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 547 #define TX_FES_SETUP_CBF_BW_LSB 8 548 #define TX_FES_SETUP_CBF_BW_MSB 10 549 #define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 550 551 552 553 554 #define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 555 #define TX_FES_SETUP_USE_STATIC_BW_LSB 11 556 #define TX_FES_SETUP_USE_STATIC_BW_MSB 11 557 #define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 558 559 560 561 562 #define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 563 #define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 564 #define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 565 #define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 566 567 568 569 570 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 571 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 572 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 573 #define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 574 575 576 577 578 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 579 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 580 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 581 #define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 582 583 584 585 586 #define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 587 #define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 588 #define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 589 #define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 590 591 592 593 594 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 595 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 596 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 597 #define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 598 599 600 601 602 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 603 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 604 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 605 #define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 606 607 608 609 610 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 611 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 612 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 613 #define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 614 615 616 617 618 #define TX_FES_SETUP_TB_RANGING_OFFSET 0x0000000000000018 619 #define TX_FES_SETUP_TB_RANGING_LSB 0 620 #define TX_FES_SETUP_TB_RANGING_MSB 0 621 #define TX_FES_SETUP_TB_RANGING_MASK 0x0000000000000001 622 623 624 625 626 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 627 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 628 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 629 #define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e 630 631 632 633 634 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 635 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 636 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 637 #define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 638 639 640 641 642 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 643 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 644 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 645 #define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 646 647 648 649 650 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 651 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 652 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 653 #define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 654 655 656 657 658 #define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 659 #define TX_FES_SETUP_RESERVED_6A_LSB 14 660 #define TX_FES_SETUP_RESERVED_6A_MSB 31 661 #define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 662 663 664 665 666 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 667 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 668 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 669 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 670 671 672 673 674 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 675 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 676 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 677 #define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f 678 679 680 681 682 #define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 683 #define TX_FES_SETUP_RESERVED_8A_LSB 5 684 #define TX_FES_SETUP_RESERVED_8A_MSB 31 685 #define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 686 687 688 689 690 #define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 691 #define TX_FES_SETUP_FW2SW_INFO_LSB 32 692 #define TX_FES_SETUP_FW2SW_INFO_MSB 63 693 #define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 694 695 696 697 #endif 698