1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ 20 #define _TCL_ENTRANCE_FROM_PPE_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 25 26 27 struct tcl_entrance_from_ppe_ring { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t buffer_addr_lo : 32; 30 uint32_t buffer_addr_hi : 8, 31 drop_prec : 2, 32 fake_mac_header : 1, 33 known_ind : 1, 34 cpu_code_valid : 1, 35 tunnel_term_ind : 1, 36 tunnel_type : 1, 37 wifi_qos_flag : 1, 38 service_code : 9, 39 reserved_1b : 1, 40 int_pri : 4, 41 more : 1, 42 reserved_1a : 1; 43 uint32_t opaque_lo : 32; 44 uint32_t opaque_hi : 32; 45 uint32_t src_info : 16, 46 dst_info : 16; 47 uint32_t data_length : 18, 48 pool_id : 6, 49 wifi_qos : 8; 50 uint32_t data_offset : 12, 51 l4_csum_status : 1, 52 l3_csum_status : 1, 53 hash_flag : 2, 54 hash_value : 16; 55 uint32_t dscp : 8, 56 valid_toggle : 1, 57 pppoe_flag : 1, 58 svlan_flag : 1, 59 cvlan_flag : 1, 60 pid : 4, 61 l3_offset : 8, 62 l4_offset : 8; 63 #else 64 uint32_t buffer_addr_lo : 32; 65 uint32_t reserved_1a : 1, 66 more : 1, 67 int_pri : 4, 68 reserved_1b : 1, 69 service_code : 9, 70 wifi_qos_flag : 1, 71 tunnel_type : 1, 72 tunnel_term_ind : 1, 73 cpu_code_valid : 1, 74 known_ind : 1, 75 fake_mac_header : 1, 76 drop_prec : 2, 77 buffer_addr_hi : 8; 78 uint32_t opaque_lo : 32; 79 uint32_t opaque_hi : 32; 80 uint32_t dst_info : 16, 81 src_info : 16; 82 uint32_t wifi_qos : 8, 83 pool_id : 6, 84 data_length : 18; 85 uint32_t hash_value : 16, 86 hash_flag : 2, 87 l3_csum_status : 1, 88 l4_csum_status : 1, 89 data_offset : 12; 90 uint32_t l4_offset : 8, 91 l3_offset : 8, 92 pid : 4, 93 cvlan_flag : 1, 94 svlan_flag : 1, 95 pppoe_flag : 1, 96 valid_toggle : 1, 97 dscp : 8; 98 #endif 99 }; 100 101 102 103 104 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 105 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 106 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 107 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff 108 109 110 111 112 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 113 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 114 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 115 #define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff 116 117 118 119 120 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 121 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 122 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 123 #define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 124 125 126 127 128 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 129 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 130 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 131 #define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 132 133 134 135 136 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 137 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 138 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 139 #define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 140 141 142 143 144 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 145 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 146 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 147 #define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 148 149 150 151 152 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 153 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 154 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 155 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 156 157 158 159 160 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 161 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 162 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 163 #define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 164 165 166 167 168 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 169 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 170 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 171 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 172 173 174 175 176 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 177 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 178 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 179 #define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 180 181 182 183 184 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 185 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 186 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 187 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 188 189 190 191 192 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 193 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 194 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 195 #define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 196 197 198 199 200 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 201 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 202 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 203 #define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 204 205 206 207 208 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 209 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 210 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 211 #define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 212 213 214 215 216 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 217 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 218 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 219 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff 220 221 222 223 224 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c 225 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 226 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 227 #define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff 228 229 230 231 232 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 233 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 234 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 235 #define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff 236 237 238 239 240 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 241 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 242 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 243 #define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 244 245 246 247 248 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 249 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 250 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 251 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff 252 253 254 255 256 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 257 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 258 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 259 #define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 260 261 262 263 264 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 265 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 266 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 267 #define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 268 269 270 271 272 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 273 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 274 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 275 #define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff 276 277 278 279 280 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 281 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 282 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 283 #define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 284 285 286 287 288 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 289 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 290 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 291 #define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 292 293 294 295 296 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 297 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 298 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 299 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 300 301 302 303 304 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 305 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 306 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 307 #define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 308 309 310 311 312 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c 313 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 314 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 315 #define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff 316 317 318 319 320 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c 321 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 322 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 323 #define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 324 325 326 327 328 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c 329 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 330 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 331 #define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 332 333 334 335 336 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c 337 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 338 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 339 #define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 340 341 342 343 344 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c 345 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 346 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 347 #define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 348 349 350 351 352 #define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c 353 #define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 354 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 355 #define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 356 357 358 359 360 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c 361 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 362 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 363 #define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 364 365 366 367 368 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c 369 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 370 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 371 #define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 372 373 374 375 #endif 376