1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _TCL_DATA_CMD_H_ 20 #define _TCL_DATA_CMD_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "buffer_addr_info.h" 25 #define NUM_OF_DWORDS_TCL_DATA_CMD 8 26 27 28 struct tcl_data_cmd { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info buf_addr_info; 31 uint32_t tcl_cmd_type : 1, 32 buf_or_ext_desc_type : 1, 33 bank_id : 6, 34 tx_notify_frame : 3, 35 header_length_read_sel : 1, 36 buffer_timestamp : 19, 37 buffer_timestamp_valid : 1; 38 uint32_t reserved_3a : 16, 39 tcl_cmd_number : 16; 40 uint32_t data_length : 16, 41 ipv4_checksum_en : 1, 42 udp_over_ipv4_checksum_en : 1, 43 udp_over_ipv6_checksum_en : 1, 44 tcp_over_ipv4_checksum_en : 1, 45 tcp_over_ipv6_checksum_en : 1, 46 to_fw : 1, 47 reserved_4a : 1, 48 packet_offset : 9; 49 uint32_t hlos_tid_overwrite : 1, 50 flow_override_enable : 1, 51 who_classify_info_sel : 2, 52 hlos_tid : 4, 53 flow_override : 1, 54 pmac_id : 2, 55 msdu_color : 2, 56 reserved_5a : 11, 57 vdev_id : 8; 58 uint32_t search_index : 20, 59 cache_set_num : 4, 60 index_lookup_override : 1, 61 reserved_6a : 7; 62 uint32_t reserved_7a : 20, 63 ring_id : 8, 64 looping_count : 4; 65 #else 66 struct buffer_addr_info buf_addr_info; 67 uint32_t buffer_timestamp_valid : 1, 68 buffer_timestamp : 19, 69 header_length_read_sel : 1, 70 tx_notify_frame : 3, 71 bank_id : 6, 72 buf_or_ext_desc_type : 1, 73 tcl_cmd_type : 1; 74 uint32_t tcl_cmd_number : 16, 75 reserved_3a : 16; 76 uint32_t packet_offset : 9, 77 reserved_4a : 1, 78 to_fw : 1, 79 tcp_over_ipv6_checksum_en : 1, 80 tcp_over_ipv4_checksum_en : 1, 81 udp_over_ipv6_checksum_en : 1, 82 udp_over_ipv4_checksum_en : 1, 83 ipv4_checksum_en : 1, 84 data_length : 16; 85 uint32_t vdev_id : 8, 86 reserved_5a : 11, 87 msdu_color : 2, 88 pmac_id : 2, 89 flow_override : 1, 90 hlos_tid : 4, 91 who_classify_info_sel : 2, 92 flow_override_enable : 1, 93 hlos_tid_overwrite : 1; 94 uint32_t reserved_6a : 7, 95 index_lookup_override : 1, 96 cache_set_num : 4, 97 search_index : 20; 98 uint32_t looping_count : 4, 99 ring_id : 8, 100 reserved_7a : 20; 101 #endif 102 }; 103 104 105 106 107 108 109 110 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 111 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 112 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 113 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 114 115 116 117 118 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 119 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 120 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 121 #define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 122 123 124 125 126 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 127 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 128 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 129 #define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 130 131 132 133 134 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 135 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 136 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 137 #define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 138 139 140 141 142 #define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 143 #define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 144 #define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 145 #define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 146 147 148 149 150 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 151 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 152 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 153 #define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 154 155 156 157 158 #define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 159 #define TCL_DATA_CMD_BANK_ID_LSB 2 160 #define TCL_DATA_CMD_BANK_ID_MSB 7 161 #define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc 162 163 164 165 166 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 167 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 168 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 169 #define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 170 171 172 173 174 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 175 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 176 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 177 #define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 178 179 180 181 182 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 183 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 184 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 185 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 186 187 188 189 190 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 191 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 192 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 193 #define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 194 195 196 197 198 #define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c 199 #define TCL_DATA_CMD_RESERVED_3A_LSB 0 200 #define TCL_DATA_CMD_RESERVED_3A_MSB 15 201 #define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff 202 203 204 205 206 #define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c 207 #define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 208 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 209 #define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 210 211 212 213 214 #define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 215 #define TCL_DATA_CMD_DATA_LENGTH_LSB 0 216 #define TCL_DATA_CMD_DATA_LENGTH_MSB 15 217 #define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff 218 219 220 221 222 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 223 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 224 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 225 #define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 226 227 228 229 230 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 231 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 232 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 233 #define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 234 235 236 237 238 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 239 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 240 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 241 #define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 242 243 244 245 246 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 247 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 248 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 249 #define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 250 251 252 253 254 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 255 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 256 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 257 #define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 258 259 260 261 262 #define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 263 #define TCL_DATA_CMD_TO_FW_LSB 21 264 #define TCL_DATA_CMD_TO_FW_MSB 21 265 #define TCL_DATA_CMD_TO_FW_MASK 0x00200000 266 267 268 269 270 #define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 271 #define TCL_DATA_CMD_RESERVED_4A_LSB 22 272 #define TCL_DATA_CMD_RESERVED_4A_MSB 22 273 #define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 274 275 276 277 278 #define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 279 #define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 280 #define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 281 #define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 282 283 284 285 286 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 287 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 288 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 289 #define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 290 291 292 293 294 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 295 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 296 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 297 #define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 298 299 300 301 302 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 303 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 304 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 305 #define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c 306 307 308 309 310 #define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 311 #define TCL_DATA_CMD_HLOS_TID_LSB 4 312 #define TCL_DATA_CMD_HLOS_TID_MSB 7 313 #define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 314 315 316 317 318 #define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 319 #define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 320 #define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 321 #define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 322 323 324 325 326 #define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 327 #define TCL_DATA_CMD_PMAC_ID_LSB 9 328 #define TCL_DATA_CMD_PMAC_ID_MSB 10 329 #define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 330 331 332 333 334 #define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 335 #define TCL_DATA_CMD_MSDU_COLOR_LSB 11 336 #define TCL_DATA_CMD_MSDU_COLOR_MSB 12 337 #define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 338 339 340 341 342 #define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 343 #define TCL_DATA_CMD_RESERVED_5A_LSB 13 344 #define TCL_DATA_CMD_RESERVED_5A_MSB 23 345 #define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 346 347 348 349 350 #define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 351 #define TCL_DATA_CMD_VDEV_ID_LSB 24 352 #define TCL_DATA_CMD_VDEV_ID_MSB 31 353 #define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 354 355 356 357 358 #define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 359 #define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 360 #define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 361 #define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff 362 363 364 365 366 #define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 367 #define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 368 #define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 369 #define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 370 371 372 373 374 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 375 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 376 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 377 #define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 378 379 380 381 382 #define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 383 #define TCL_DATA_CMD_RESERVED_6A_LSB 25 384 #define TCL_DATA_CMD_RESERVED_6A_MSB 31 385 #define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 386 387 388 389 390 #define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c 391 #define TCL_DATA_CMD_RESERVED_7A_LSB 0 392 #define TCL_DATA_CMD_RESERVED_7A_MSB 19 393 #define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff 394 395 396 397 398 #define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c 399 #define TCL_DATA_CMD_RING_ID_LSB 20 400 #define TCL_DATA_CMD_RING_ID_MSB 27 401 #define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 402 403 404 405 406 #define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c 407 #define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 408 #define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 409 #define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 410 411 412 413 #endif 414