1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _SW_MONITOR_RING_H_ 20 #define _SW_MONITOR_RING_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #include "buffer_addr_info.h" 25 #include "rx_mpdu_details.h" 26 #define NUM_OF_DWORDS_SW_MONITOR_RING 8 27 28 29 struct sw_monitor_ring { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 struct rx_mpdu_details reo_level_mpdu_frame_info; 32 struct buffer_addr_info status_buff_addr_info; 33 uint32_t rxdma_push_reason : 2, 34 rxdma_error_code : 5, 35 mpdu_fragment_number : 4, 36 frameless_bar : 1, 37 status_buf_count : 4, 38 end_of_ppdu : 1, 39 reserved_6a : 15; 40 uint32_t phy_ppdu_id : 16, 41 reserved_7a : 4, 42 ring_id : 8, 43 looping_count : 4; 44 #else 45 struct rx_mpdu_details reo_level_mpdu_frame_info; 46 struct buffer_addr_info status_buff_addr_info; 47 uint32_t reserved_6a : 15, 48 end_of_ppdu : 1, 49 status_buf_count : 4, 50 frameless_bar : 1, 51 mpdu_fragment_number : 4, 52 rxdma_error_code : 5, 53 rxdma_push_reason : 2; 54 uint32_t looping_count : 4, 55 ring_id : 8, 56 reserved_7a : 4, 57 phy_ppdu_id : 16; 58 #endif 59 }; 60 61 62 63 64 65 66 67 68 69 70 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 71 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 72 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 73 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 74 75 76 77 78 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 79 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 80 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 81 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 82 83 84 85 86 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 87 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 88 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 89 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 90 91 92 93 94 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 95 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 96 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 97 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 98 99 100 101 102 103 104 105 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 106 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 107 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 108 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 109 110 111 112 113 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 114 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 115 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 116 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 117 118 119 120 121 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 122 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 123 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 124 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 125 126 127 128 129 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 130 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 131 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 132 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 133 134 135 136 137 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 138 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 139 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 140 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 141 142 143 144 145 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 146 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 147 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 148 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 149 150 151 152 153 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 154 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 155 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 156 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 157 158 159 160 161 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 162 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 163 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 164 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 165 166 167 168 169 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 170 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 171 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 172 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 173 174 175 176 177 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 178 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 179 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 180 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 181 182 183 184 185 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 186 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 187 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 188 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 189 190 191 192 193 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 194 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 195 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 196 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 197 198 199 200 201 202 203 204 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 205 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 206 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 207 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 208 209 210 211 212 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 213 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 214 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 215 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 216 217 218 219 220 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 221 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 222 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 223 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 224 225 226 227 228 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 229 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 230 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 231 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 232 233 234 235 236 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 237 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB 0 238 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB 1 239 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK 0x00000003 240 241 242 243 244 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 245 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB 2 246 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB 6 247 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 248 249 250 251 252 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 253 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB 7 254 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB 10 255 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 256 257 258 259 260 #define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET 0x00000018 261 #define SW_MONITOR_RING_FRAMELESS_BAR_LSB 11 262 #define SW_MONITOR_RING_FRAMELESS_BAR_MSB 11 263 #define SW_MONITOR_RING_FRAMELESS_BAR_MASK 0x00000800 264 265 266 267 268 #define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET 0x00000018 269 #define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB 12 270 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB 15 271 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK 0x0000f000 272 273 274 275 276 #define SW_MONITOR_RING_END_OF_PPDU_OFFSET 0x00000018 277 #define SW_MONITOR_RING_END_OF_PPDU_LSB 16 278 #define SW_MONITOR_RING_END_OF_PPDU_MSB 16 279 #define SW_MONITOR_RING_END_OF_PPDU_MASK 0x00010000 280 281 282 283 284 #define SW_MONITOR_RING_RESERVED_6A_OFFSET 0x00000018 285 #define SW_MONITOR_RING_RESERVED_6A_LSB 17 286 #define SW_MONITOR_RING_RESERVED_6A_MSB 31 287 #define SW_MONITOR_RING_RESERVED_6A_MASK 0xfffe0000 288 289 290 291 292 #define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET 0x0000001c 293 #define SW_MONITOR_RING_PHY_PPDU_ID_LSB 0 294 #define SW_MONITOR_RING_PHY_PPDU_ID_MSB 15 295 #define SW_MONITOR_RING_PHY_PPDU_ID_MASK 0x0000ffff 296 297 298 299 300 #define SW_MONITOR_RING_RESERVED_7A_OFFSET 0x0000001c 301 #define SW_MONITOR_RING_RESERVED_7A_LSB 16 302 #define SW_MONITOR_RING_RESERVED_7A_MSB 19 303 #define SW_MONITOR_RING_RESERVED_7A_MASK 0x000f0000 304 305 306 307 308 #define SW_MONITOR_RING_RING_ID_OFFSET 0x0000001c 309 #define SW_MONITOR_RING_RING_ID_LSB 20 310 #define SW_MONITOR_RING_RING_ID_MSB 27 311 #define SW_MONITOR_RING_RING_ID_MASK 0x0ff00000 312 313 314 315 316 #define SW_MONITOR_RING_LOOPING_COUNT_OFFSET 0x0000001c 317 #define SW_MONITOR_RING_LOOPING_COUNT_LSB 28 318 #define SW_MONITOR_RING_LOOPING_COUNT_MSB 31 319 #define SW_MONITOR_RING_LOOPING_COUNT_MASK 0xf0000000 320 321 322 323 #endif 324