1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_TRIG_INFO_H_ 20 #define _RX_TRIG_INFO_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_TRIG_INFO 2 25 26 #define NUM_OF_QWORDS_RX_TRIG_INFO 1 27 28 29 struct rx_trig_info { 30 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 31 uint32_t rx_trigger_frame_type : 2, 32 trigger_resp_type : 3, 33 reserved_0 : 27; 34 uint32_t ppdu_duration : 16, 35 unique_destination_id : 16; 36 #else 37 uint32_t reserved_0 : 27, 38 trigger_resp_type : 3, 39 rx_trigger_frame_type : 2; 40 uint32_t unique_destination_id : 16, 41 ppdu_duration : 16; 42 #endif 43 }; 44 45 46 47 48 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 49 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 50 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 51 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 52 53 54 55 56 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 57 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 58 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 59 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c 60 61 62 63 64 #define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 65 #define RX_TRIG_INFO_RESERVED_0_LSB 5 66 #define RX_TRIG_INFO_RESERVED_0_MSB 31 67 #define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 68 69 70 71 72 #define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 73 #define RX_TRIG_INFO_PPDU_DURATION_LSB 32 74 #define RX_TRIG_INFO_PPDU_DURATION_MSB 47 75 #define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 76 77 78 79 80 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 81 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 82 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 83 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 84 85 86 87 #endif 88