1 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * SPDX-License-Identifier: ISC 5 */ 6 7 8 9 10 11 12 13 14 15 16 17 18 19 #ifndef _RX_REO_QUEUE_REFERENCE_H_ 20 #define _RX_REO_QUEUE_REFERENCE_H_ 21 #if !defined(__ASSEMBLER__) 22 #endif 23 24 #define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 25 26 27 struct rx_reo_queue_reference { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 30 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 31 reserved_1 : 8, 32 receive_queue_number : 16; 33 #else 34 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 35 uint32_t receive_queue_number : 16, 36 reserved_1 : 8, 37 rx_reo_queue_desc_addr_39_32 : 8; 38 #endif 39 }; 40 41 42 43 44 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 45 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 46 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 47 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 48 49 50 51 52 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 53 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 54 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 55 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 56 57 58 59 60 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 61 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 62 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 63 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 64 65 66 67 68 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 69 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 70 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 71 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 72 73 74 75 #endif 76